bslathi19/super6502
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Revert sdram state machine upgrade

Browse Source
This commit is contained in:
Byron Lathi
2023-11-24 17:54:03 -08:00
parent 8c6b262f0c
commit 89a1a70917
2 changed files with 126 additions and 150 deletions
Download Patch File Download Diff File Expand all files Collapse all files

105
hw/efinix_fpga/src/sdram_adapter.sv
View File

@@ -70,11 +70,10 @@ assign o_sdr_DQM = w_sdr_DQM[0+:2];
// But basically if we are in access, and cpuclk goes low, go back to wait. // But basically if we are in access, and cpuclk goes low, go back to wait.
// If something actually happened, we would be in one of the read/write states. // If something actually happened, we would be in one of the read/write states.
enum bit [2:0] {ACCESS, PRE_READ, READ_WAIT, PRE_WRITE, WRITE_WAIT, WAIT} state, next_state; enum bit [1:0] {ACCESS, READ_WAIT, WRITE_WAIT, WAIT} state, next_state;
logic w_read, w_write, w_last; logic w_read, w_write, w_last;
logic [23:0] w_read_addr, w_write_addr; logic [23:0] w_addr, r_addr;
logic [23:0] r_read_addr, r_write_addr;
logic [31:0] w_data_i, w_data_o; logic [31:0] w_data_i, w_data_o;
logic [3:0] w_dm, r_dm; logic [3:0] w_dm, r_dm;
@@ -87,15 +86,25 @@ logic [31:0] r_write_data;
logic [1:0] counter, next_counter; logic [1:0] counter, next_counter;
logic [7:0] o_data_next; always @(posedge i_sysclk) begin
if (i_arst) begin
logic [23:0] addr_mux_out; state <= WAIT;
counter <= '0;
logic slow_mem; end else begin
state <= next_state;
counter <= next_counter;
r_write_data <= w_data_i;
r_addr <= w_addr;
r_dm <= w_dm;
end
if (w_data_valid)
o_data <= _data;
end
logic r_wait; logic r_wait;
logic _r_wait; logic _r_wait;
assign o_wait = (r_wait | slow_mem) & i_cs; assign o_wait = r_wait & i_cs;
// we need to assert rdy low until a falling edge if a reset happens // we need to assert rdy low until a falling edge if a reset happens
@@ -117,20 +126,6 @@ always @(posedge i_sysclk or posedge i_arst) begin
end end
end end
end end
if (i_arst) begin
state <= WAIT;
counter <= '0;
end else begin
state <= next_state;
counter <= next_counter;
r_write_data <= w_data_i;
r_read_addr <= w_read_addr;
r_write_addr <= w_write_addr;
r_dm <= w_dm;
end
o_data <= o_data_next;
end end
//because of timing issues, We really need to trigger //because of timing issues, We really need to trigger
@@ -162,12 +157,10 @@ end
always_comb begin always_comb begin
slow_mem = '0;
next_state = state; next_state = state;
next_counter = counter; next_counter = counter;
w_read_addr = '0; w_addr = '0;
w_write_addr = '0;
w_dm = '0; w_dm = '0;
w_read = '0; w_read = '0;
w_write = '0; w_write = '0;
@@ -178,81 +171,65 @@ always_comb begin
unique case (state) unique case (state)
WAIT: begin WAIT: begin
if (i_cs & ~i_cpuclk) if (i_cs & i_cpuclk)
next_state = ACCESS; next_state = ACCESS;
end end
ACCESS: begin ACCESS: begin
// only do something if selected // only do something if selected
if (i_cs) begin if (i_cs) begin
w_read_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0 w_addr = {{i_addr[24:2]}, {1'b0}};; // divide by 2, set last bit to 0
w_write_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0
addr_mux_out = w_read_addr;
if (i_rwb) begin //read if (i_rwb) begin //read
next_state = PRE_READ; w_read = '1;
w_last = '1;
// dm is not needed for reads?
if (w_rd_ack) next_state = READ_WAIT;
end else begin //write end else begin //write
w_data_i = i_data << (8*i_addr[1:0]); w_data_i = i_data << (8*i_addr[1:0]);
//w_data_i = {4{i_data}}; //does anything get through?
w_dm = ~(4'b1 << i_addr[1:0]); w_dm = ~(4'b1 << i_addr[1:0]);
next_state = PRE_WRITE; if (~i_cpuclk) begin
w_write = '1;
w_last = '1;
next_state = WRITE_WAIT;
end
end end
end end
end end
PRE_WRITE: begin
w_data_i = r_write_data;
w_write_addr = r_write_addr;
addr_mux_out = w_write_addr;
w_dm = r_dm;
//w_data_i = {4{i_data}}; //does anything get through?
if (~i_cpuclk) begin
w_write = '1;
w_last = '1;
next_state = WRITE_WAIT;
end
end
WRITE_WAIT: begin WRITE_WAIT: begin
// stay in this state until write is acknowledged. // stay in this state until write is acknowledged.
w_write_addr = r_write_addr;
addr_mux_out = w_write_addr;
w_write = '1; w_write = '1;
w_last = '1; w_last = '1;
w_data_i = r_write_data; w_data_i = r_write_data;
w_dm = r_dm; w_dm = r_dm;
w_addr = r_addr;
if (w_wr_ack) next_state = WAIT; if (w_wr_ack) next_state = WAIT;
end end
PRE_READ: begin
w_read_addr = r_read_addr;
addr_mux_out = w_read_addr;
w_read = '1;
w_last = '1;
slow_mem = '1;
// dm is not needed for reads?
if (w_rd_ack) next_state = READ_WAIT;
end
READ_WAIT: begin READ_WAIT: begin
w_read_addr = r_read_addr;
addr_mux_out = w_read_addr;
slow_mem = '1;
if (w_rd_valid) begin if (w_rd_valid) begin
w_data_valid = '1; w_data_valid = '1;
_data = w_data_o[8*i_addr[1:0]+:8]; _data = w_data_o[8*i_addr[1:0]+:8];
end end
// you must wait until the next cycle! // you must wait until the next cycle!
if (w_data_valid) begin if (~i_cpuclk) begin
next_state = WAIT; next_state = WAIT;
end end
end end
endcase endcase
end
if (w_data_valid) begin //this seems scuffed
o_data_next = _data; logic [23:0] addr_mux_out;
always_comb begin
if (state == ACCESS) begin
addr_mux_out = w_addr;
end else begin end else begin
o_data_next = o_data; addr_mux_out = r_addr;
end end
end end

171
hw/efinix_fpga/super6502.xml
View File

@@ -1,108 +1,107 @@
<?xml version="1.0" encoding="UTF-8"?> <efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Fri Nov 24 2023 17:49:43" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Thu November 23 2023 12:03:00" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info> <efx:device_info>
<efx:family name="Trion"/> <efx:family name="Trion" />
<efx:device name="T20F256"/> <efx:device name="T20F256" />
<efx:timing_model name="C4"/> <efx:timing_model name="C4" />
</efx:device_info> </efx:device_info>
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008"> <efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
<efx:top_module name="super6502"/> <efx:top_module name="super6502" />
<efx:design_file name="src/super6502.sv" version="default" library="default"/> <efx:design_file name="src/super6502.sv" version="default" library="default" />
<efx:design_file name="src/leds.sv" version="default" library="default"/> <efx:design_file name="src/leds.sv" version="default" library="default" />
<efx:design_file name="src/sdram_adapter.sv" version="default" library="default"/> <efx:design_file name="src/sdram_adapter.sv" version="default" library="default" />
<efx:design_file name="src/timer.sv" version="default" library="default"/> <efx:design_file name="src/timer.sv" version="default" library="default" />
<efx:design_file name="src/interrupt_controller.sv" version="default" library="default"/> <efx:design_file name="src/interrupt_controller.sv" version="default" library="default" />
<efx:design_file name="src/multiplier.sv" version="default" library="default"/> <efx:design_file name="src/multiplier.sv" version="default" library="default" />
<efx:design_file name="src/divider_wrapper.sv" version="default" library="default"/> <efx:design_file name="src/divider_wrapper.sv" version="default" library="default" />
<efx:design_file name="src/uart_wrapper.sv" version="default" library="default"/> <efx:design_file name="src/uart_wrapper.sv" version="default" library="default" />
<efx:design_file name="src/sd_controller.sv" version="default" library="default"/> <efx:design_file name="src/sd_controller.sv" version="default" library="default" />
<efx:design_file name="src/crc7.sv" version="default" library="default"/> <efx:design_file name="src/crc7.sv" version="default" library="default" />
<efx:design_file name="src/rom.sv" version="default" library="default"/> <efx:design_file name="src/rom.sv" version="default" library="default" />
<efx:design_file name="src/spi_controller.sv" version="default" library="default"/> <efx:design_file name="src/spi_controller.sv" version="default" library="default" />
<efx:design_file name="src/mapper.sv" version="default" library="default"/> <efx:design_file name="src/mapper.sv" version="default" library="default" />
<efx:design_file name="src/byte_sel_register.sv" version="default" library="default"/> <efx:design_file name="src/byte_sel_register.sv" version="default" library="default" />
<efx:design_file name="src/rtc.sv" version="default" library="default"/> <efx:design_file name="src/rtc.sv" version="default" library="default" />
<efx:top_vhdl_arch name=""/> <efx:top_vhdl_arch name="" />
</efx:design_info> </efx:design_info>
<efx:constraint_info> <efx:constraint_info>
<efx:sdc_file name="constraints/super6502.pt.sdc"/> <efx:sdc_file name="constraints/super6502.pt.sdc" />
<efx:inter_file name=""/> <efx:inter_file name="" />
</efx:constraint_info> </efx:constraint_info>
<efx:sim_info/> <efx:sim_info />
<efx:misc_info/> <efx:misc_info />
<efx:ip_info> <efx:ip_info>
<efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json"> <efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json">
<efx:ip_src_file name="sdram_controller.v"/> <efx:ip_src_file name="sdram_controller.v" />
</efx:ip> </efx:ip>
<efx:ip instance_name="divider" path="ip/divider/settings.json"> <efx:ip instance_name="divider" path="ip/divider/settings.json">
<efx:ip_src_file name="divider.v"/> <efx:ip_src_file name="divider.v" />
</efx:ip> </efx:ip>
<efx:ip instance_name="uart" path="ip/uart/settings.json"> <efx:ip instance_name="uart" path="ip/uart/settings.json">
<efx:ip_src_file name="uart.v"/> <efx:ip_src_file name="uart.v" />
</efx:ip> </efx:ip>
</efx:ip_info> </efx:ip_info>
<efx:synthesis tool_name="efx_map"> <efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string"/> <efx:param name="work_dir" value="work_syn" value_type="e_string" />
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/> <efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
<efx:param name="mode" value="speed" value_type="e_option"/> <efx:param name="mode" value="speed" value_type="e_option" />
<efx:param name="max_ram" value="-1" value_type="e_integer"/> <efx:param name="max_ram" value="-1" value_type="e_integer" />
<efx:param name="max_mult" value="-1" value_type="e_integer"/> <efx:param name="max_mult" value="-1" value_type="e_integer" />
<efx:param name="infer-clk-enable" value="3" value_type="e_option"/> <efx:param name="infer-clk-enable" value="3" value_type="e_option" />
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/> <efx:param name="infer-sync-set-reset" value="1" value_type="e_option" />
<efx:param name="fanout-limit" value="0" value_type="e_integer"/> <efx:param name="fanout-limit" value="0" value_type="e_integer" />
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/> <efx:param name="bram_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="retiming" value="1" value_type="e_option"/> <efx:param name="retiming" value="1" value_type="e_option" />
<efx:param name="seq_opt" value="1" value_type="e_option"/> <efx:param name="seq_opt" value="1" value_type="e_option" />
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/> <efx:param name="blast_const_operand_adders" value="1" value_type="e_option" />
<efx:param name="operator-sharing" value="0" value_type="e_option"/> <efx:param name="operator-sharing" value="0" value_type="e_option" />
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/> <efx:param name="optimize-adder-tree" value="0" value_type="e_option" />
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/> <efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/> <efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="min-sr-fanout" value="0" value_type="e_option"/> <efx:param name="min-sr-fanout" value="0" value_type="e_option" />
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/> <efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
<efx:param name="blackbox-error" value="1" value_type="e_option"/> <efx:param name="blackbox-error" value="1" value_type="e_option" />
<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/> <efx:param name="allow-const-ram-index" value="0" value_type="e_option" />
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/> <efx:param name="hdl-compile-unit" value="1" value_type="e_option" />
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/> <efx:param name="create-onehot-fsms" value="0" value_type="e_option" />
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/> <efx:param name="min-ce-fanout" value="0" value_type="e_integer" />
<efx:param name="mult-decomp-retime" value="0" value_type="e_option"/> <efx:param name="mult-decomp-retime" value="0" value_type="e_option" />
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option"/> <efx:param name="optimize-zero-init-rom" value="1" value_type="e_option" />
<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/> <efx:param name="include" value="ip/sdram_controller" value_type="e_string" />
<efx:param name="include" value="ip/divider" value_type="e_string"/> <efx:param name="include" value="ip/divider" value_type="e_string" />
<efx:param name="include" value="ip/uart" value_type="e_string"/> <efx:param name="include" value="ip/uart" value_type="e_string" />
</efx:synthesis> </efx:synthesis>
<efx:place_and_route tool_name="efx_pnr"> <efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/> <efx:param name="work_dir" value="work_pnr" value_type="e_string" />
<efx:param name="verbose" value="off" value_type="e_bool"/> <efx:param name="verbose" value="off" value_type="e_bool" />
<efx:param name="load_delaym" value="on" value_type="e_bool"/> <efx:param name="load_delaym" value="on" value_type="e_bool" />
<efx:param name="optimization_level" value="NULL" value_type="e_option"/> <efx:param name="optimization_level" value="NULL" value_type="e_option" />
<efx:param name="seed" value="1" value_type="e_integer"/> <efx:param name="seed" value="1" value_type="e_integer" />
<efx:param name="placer_effort_level" value="2" value_type="e_option"/> <efx:param name="placer_effort_level" value="2" value_type="e_option" />
<efx:param name="max_threads" value="-1" value_type="e_integer"/> <efx:param name="max_threads" value="-1" value_type="e_integer" />
</efx:place_and_route> </efx:place_and_route>
<efx:bitstream_generation tool_name="efx_pgm"> <efx:bitstream_generation tool_name="efx_pgm">
<efx:param name="mode" value="active" value_type="e_option"/> <efx:param name="mode" value="active" value_type="e_option" />
<efx:param name="width" value="1" value_type="e_option"/> <efx:param name="width" value="1" value_type="e_option" />
<efx:param name="enable_roms" value="smart" value_type="e_option"/> <efx:param name="enable_roms" value="smart" value_type="e_option" />
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/> <efx:param name="spi_low_power_mode" value="on" value_type="e_bool" />
<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/> <efx:param name="io_weak_pullup" value="on" value_type="e_bool" />
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/> <efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option" />
<efx:param name="bitstream_compression" value="off" value_type="e_bool"/> <efx:param name="bitstream_compression" value="off" value_type="e_bool" />
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/> <efx:param name="enable_external_master_clock" value="off" value_type="e_bool" />
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option"/> <efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option" />
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/> <efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string" />
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/> <efx:param name="release_tri_then_reset" value="on" value_type="e_bool" />
<efx:param name="cold_boot" value="off" value_type="e_bool"/> <efx:param name="cold_boot" value="off" value_type="e_bool" />
<efx:param name="cascade" value="off" value_type="e_option"/> <efx:param name="cascade" value="off" value_type="e_option" />
<efx:param name="generate_bit" value="on" value_type="e_bool"/> <efx:param name="generate_bit" value="on" value_type="e_bool" />
<efx:param name="generate_bitbin" value="off" value_type="e_bool"/> <efx:param name="generate_bitbin" value="off" value_type="e_bool" />
<efx:param name="generate_hex" value="on" value_type="e_bool"/> <efx:param name="generate_hex" value="on" value_type="e_bool" />
<efx:param name="generate_hexbin" value="off" value_type="e_bool"/> <efx:param name="generate_hexbin" value="off" value_type="e_bool" />
<efx:param name="four_byte_addressing" value="off" value_type="e_bool"/> <efx:param name="four_byte_addressing" value="off" value_type="e_bool" />
</efx:bitstream_generation> </efx:bitstream_generation>
<efx:debugger> <efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/> <efx:param name="work_dir" value="work_dbg" value_type="e_string" />
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/> <efx:param name="auto_instantiation" value="off" value_type="e_bool" />
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/> <efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string" />
</efx:debugger> </efx:debugger>
</efx:project> </efx:project>