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Revert sdram state machine upgrade

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This commit is contained in:
Byron Lathi
2023-11-24 17:54:03 -08:00
parent 8c6b262f0c
commit 89a1a70917
2 changed files with 126 additions and 150 deletions
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97
hw/efinix_fpga/src/sdram_adapter.sv
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@@ -70,11 +70,10 @@ assign o_sdr_DQM = w_sdr_DQM[0+:2];
// But basically if we are in access, and cpuclk goes low, go back to wait.
// If something actually happened, we would be in one of the read/write states.
enum bit [2:0] {ACCESS, PRE_READ, READ_WAIT, PRE_WRITE, WRITE_WAIT, WAIT} state, next_state;
enum bit [1:0] {ACCESS, READ_WAIT, WRITE_WAIT, WAIT} state, next_state;
logic w_read, w_write, w_last;
logic [23:0] w_read_addr, w_write_addr;
logic [23:0] r_read_addr, r_write_addr;
logic [23:0] w_addr, r_addr;
logic [31:0] w_data_i, w_data_o;
logic [3:0] w_dm, r_dm;
@@ -87,15 +86,25 @@ logic [31:0] r_write_data;
logic [1:0] counter, next_counter;
logic [7:0] o_data_next;
always @(posedge i_sysclk) begin
if (i_arst) begin
state <= WAIT;
counter <= '0;
end else begin
state <= next_state;
counter <= next_counter;
r_write_data <= w_data_i;
r_addr <= w_addr;
r_dm <= w_dm;
end
logic [23:0] addr_mux_out;
logic slow_mem;
if (w_data_valid)
o_data <= _data;
end
logic r_wait;
logic _r_wait;
assign o_wait = (r_wait | slow_mem) & i_cs;
assign o_wait = r_wait & i_cs;
// we need to assert rdy low until a falling edge if a reset happens
@@ -117,20 +126,6 @@ always @(posedge i_sysclk or posedge i_arst) begin
end
end
end
if (i_arst) begin
state <= WAIT;
counter <= '0;
end else begin
state <= next_state;
counter <= next_counter;
r_write_data <= w_data_i;
r_read_addr <= w_read_addr;
r_write_addr <= w_write_addr;
r_dm <= w_dm;
end
o_data <= o_data_next;
end
//because of timing issues, We really need to trigger
@@ -162,12 +157,10 @@ end
always_comb begin
slow_mem = '0;
next_state = state;
next_counter = counter;
w_read_addr = '0;
w_write_addr = '0;
w_addr = '0;
w_dm = '0;
w_read = '0;
w_write = '0;
@@ -178,81 +171,65 @@ always_comb begin
unique case (state)
WAIT: begin
if (i_cs & ~i_cpuclk)
if (i_cs & i_cpuclk)
next_state = ACCESS;
end
ACCESS: begin
// only do something if selected
if (i_cs) begin
w_read_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0
w_write_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0
addr_mux_out = w_read_addr;
w_addr = {{i_addr[24:2]}, {1'b0}};; // divide by 2, set last bit to 0
if (i_rwb) begin //read
next_state = PRE_READ;
w_read = '1;
w_last = '1;
// dm is not needed for reads?
if (w_rd_ack) next_state = READ_WAIT;
end else begin //write
w_data_i = i_data << (8*i_addr[1:0]);
w_dm = ~(4'b1 << i_addr[1:0]);
next_state = PRE_WRITE;
end
end
end
PRE_WRITE: begin
w_data_i = r_write_data;
w_write_addr = r_write_addr;
addr_mux_out = w_write_addr;
w_dm = r_dm;
//w_data_i = {4{i_data}}; //does anything get through?
w_dm = ~(4'b1 << i_addr[1:0]);
if (~i_cpuclk) begin
w_write = '1;
w_last = '1;
next_state = WRITE_WAIT;
end
end
end
end
WRITE_WAIT: begin
// stay in this state until write is acknowledged.
w_write_addr = r_write_addr;
addr_mux_out = w_write_addr;
w_write = '1;
w_last = '1;
w_data_i = r_write_data;
w_dm = r_dm;
w_addr = r_addr;
if (w_wr_ack) next_state = WAIT;
end
PRE_READ: begin
w_read_addr = r_read_addr;
addr_mux_out = w_read_addr;
w_read = '1;
w_last = '1;
slow_mem = '1;
// dm is not needed for reads?
if (w_rd_ack) next_state = READ_WAIT;
end
READ_WAIT: begin
w_read_addr = r_read_addr;
addr_mux_out = w_read_addr;
slow_mem = '1;
if (w_rd_valid) begin
w_data_valid = '1;
_data = w_data_o[8*i_addr[1:0]+:8];
end
// you must wait until the next cycle!
if (w_data_valid) begin
if (~i_cpuclk) begin
next_state = WAIT;
end
end
endcase
end
if (w_data_valid) begin
o_data_next = _data;
//this seems scuffed
logic [23:0] addr_mux_out;
always_comb begin
if (state == ACCESS) begin
addr_mux_out = w_addr;
end else begin
o_data_next = o_data;
addr_mux_out = r_addr;
end
end

3
hw/efinix_fpga/super6502.xml
View File

@@ -1,5 +1,4 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Thu November 23 2023 12:03:00" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Fri Nov 24 2023 17:49:43" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion" />
<efx:device name="T20F256" />