Change segment order to make o65 layout valid

VECTORS was messing things up

hw/efinix_fpga/super6502.xml

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="super6502" description="" last_change_date="Tue August 15 2023 22:44:54" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="super6502" description="" last_change_date="Mon August 21 2023 19:23:14" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion"/>
         <efx:device name="T20F256"/>

sw/kernel/boot.s

@@ -17,7 +17,7 @@
 ; ---------------------------------------------------------------------------
 ; Place the startup code in a special segment
 
-.segment "CODE"
+.segment "STARTUP"
 
 ; ---------------------------------------------------------------------------
 ; A little light 6502 housekeeping

sw/kernel/link.ld

@@ -11,13 +11,12 @@ MEMORY
 SEGMENTS {
     ZEROPAGE:   load = ZP,      type = zp, define = yes; 
     STARTUP:    load = KERNEL,  type = ro;
-    CODE:       load = KERNEL,  type = ro;
     ONCE:       load = KERNEL,  type = ro, optional = yes;
+    CODE:       load = KERNEL,  type = ro;
+    RODATA:     load = KERNEL,  type = ro;
     DATA:       load = KERNEL,  type = rw, define = yes;
     BSS:        load = KERNEL,  type = rw, define = yes;
     HEAP:       load = KERNEL,  type = rw, define = yes, optional = yes;
-    RODATA:     load = KERNEL,  type = ro;
-    VECTORS:    load = ROM,     type = ro,  start    = $FFFA;
 }
 
 FILES
@@ -27,7 +26,7 @@ FILES
 
 FORMATS
 {
-    o65: os = super, version = 0, type = small,
+    o65: os = lunix, version = 0, type = small,
             export = _init;
 }
 

sw/kernel/vectors.s

@@ -1,16 +0,0 @@
-.segment "VECTORS"
-
-.addr      _nmi_int    ; NMI vector
-.addr      _na         ; Reset vector (Doesn't matter, will go back to ROM)
-.addr      _irq_int    ; IRQ/BRK vector
-
-.segment "CODE"
-
-_na:
-    rti
-
-_nmi_int:
-    rti
-
-_irq_int:
-    rti

sw/script/o65dump.py

@@ -1,6 +1,43 @@
 #!/usr/bin/python
 
 import sys
+import io
+
+class O65():
+
+    header: dict[str, int] = {}
+    options: list[(int, int, bytes)] = []
+    text: bytes
+    data: bytes
+
+    def __init__(self, filename: str) -> None:
+        with open(filename, "rb") as _file:
+            self.header["no_c64"]   = int.from_bytes(_file.read(2))
+            self.header["magic"]    = int.from_bytes(_file.read(3))
+            self.header["version"]  = int.from_bytes(_file.read(1))
+            self.header["mode"]     = int.from_bytes(_file.read(2), byteorder="little")
+            self.header["tbase"]    = int.from_bytes(_file.read(2), byteorder="little")
+            self.header["tlen"]     = int.from_bytes(_file.read(2), byteorder="little")
+            self.header["dbase"]    = int.from_bytes(_file.read(2), byteorder="little")
+            self.header["dlen"]     = int.from_bytes(_file.read(2), byteorder="little")
+            self.header["bbase"]    = int.from_bytes(_file.read(2), byteorder="little")
+            self.header["blen"]     = int.from_bytes(_file.read(2), byteorder="little")
+            self.header["zbase"]    = int.from_bytes(_file.read(2), byteorder="little")
+            self.header["zlen"]     = int.from_bytes(_file.read(2), byteorder="little")
+            self.header["stack"]    = int.from_bytes(_file.read(2), byteorder="little")
+
+            olen = int.from_bytes(_file.read(1))
+            while olen != 0:
+                otype = int.from_bytes(_file.read(1))
+                obytes = _file.read(olen - 2)
+                self.options.append((olen, otype, obytes))
+                olen = int.from_bytes(_file.read(1))
+
+            self.text = _file.read(self.header["tlen"])
+            self.data = _file.read(self.header["dlen"])
+
+
+
 
 def main() -> None:
     if len(sys.argv) < 2:
@@ -8,8 +45,15 @@ def main() -> None:
         return
     filename = sys.argv[1]
     print(filename)
-    with open(filename, "rb") as file:
+    o65 = O65(filename)
-        print(file.read(1))
+    for item, value in o65.header.items():
+        print(f"{item}:\t{value:x}")
+    
+    for option in o65.options:
+        print(f"Type: {option[1]}, Data: {option[2]}")
+
+    with open("text.bin", "wb") as textfile:
+        textfile.write(o65.text)
 
 if __name__ == "__main__":
     main()

sw/test_exec/Makefile

@@ -1,4 +1,4 @@
-CC=cl65
+CC=../cc65/bin/cl65
 CFLAGS=-T -t super6502 -I. --cpu "65C02"
 test: CFLAGS=-T -t sim65c02 -I.
 LDFLAGS=-C link.ld -m $(NAME).map

sw/test_exec/link.ld

@@ -10,13 +10,13 @@ FILES {
 
 SEGMENTS {
     ZEROPAGE: load = ZP,  type = zp,  define   = yes;
-    DATA:     load = SDRAM, type = rw,  define   = yes, run = SDRAM;
-    BSS:      load = SDRAM, type = bss, define   = yes;
-    HEAP:     load = SDRAM, type = bss, optional = yes;
     STARTUP:  load = SDRAM, type = ro;
     ONCE:     load = SDRAM, type = ro,  optional = yes;
     CODE:     load = SDRAM, type = ro;
     RODATA:   load = SDRAM, type = ro;
+    DATA:     load = SDRAM, type = rw,  define   = yes, run = SDRAM;
+    BSS:      load = SDRAM, type = bss, define   = yes;
+    HEAP:     load = SDRAM, type = bss, optional = yes;
 }
 
 FEATURES {