From 8c4102612fc427250b0854db5a56725db8f2d1a9 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 29 Dec 2022 11:51:38 -0500 Subject: [PATCH] Add timer and test program --- hw/efinix_fpga/addr_decode.sv | 2 + hw/efinix_fpga/debug_profile.wizard.json | 2275 +--------------------- hw/efinix_fpga/ip/bram/bram_ini.vh | 6 +- hw/efinix_fpga/ip/bram/init_hex.mem | 56 +- hw/efinix_fpga/super6502.sv | 17 +- hw/efinix_fpga/super6502.xml | 2 +- hw/efinix_fpga/test_programs/Makefile | 4 +- hw/efinix_fpga/test_programs/timer.s | 38 + hw/efinix_fpga/timer.sv | 4 +- 9 files changed, 98 insertions(+), 2306 deletions(-) create mode 100644 hw/efinix_fpga/test_programs/timer.s diff --git a/hw/efinix_fpga/addr_decode.sv b/hw/efinix_fpga/addr_decode.sv index a6f1121..a725971 100644 --- a/hw/efinix_fpga/addr_decode.sv +++ b/hw/efinix_fpga/addr_decode.sv @@ -4,11 +4,13 @@ module addr_decode output o_rom_cs, output o_leds_cs, + output o_timer_cs, output o_sdram_cs ); assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff; assign o_leds_cs = i_addr == 16'hefff; +assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffe; assign o_sdram_cs = i_addr < 16'h8000; endmodule \ No newline at end of file diff --git a/hw/efinix_fpga/debug_profile.wizard.json b/hw/efinix_fpga/debug_profile.wizard.json index 6054f16..6a81375 100644 --- a/hw/efinix_fpga/debug_profile.wizard.json +++ b/hw/efinix_fpga/debug_profile.wizard.json @@ -3,7 +3,7 @@ { "name": "la0", "type": "la", - "uuid": "fa82fd4c09e84dddbd54b75ec5018eca", + "uuid": "0783f8a7edf7498d8f9e6d19f8bd60d1", "trigin_en": false, "trigout_en": false, "auto_inserted": true, @@ -30,151 +30,6 @@ "name": "cpu_sync", "width": 1, "probe_type": 1 - }, - { - "name": "u_sdram_adapter/addr_mux_out", - "width": 24, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/counter", - "width": 2, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/data", - "width": 8, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/i_addr", - "width": 25, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/i_arst", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/i_cpuclk", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/i_cs", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/i_data", - "width": 8, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/i_rwb", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/next_counter", - "width": 2, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/next_state", - "width": 2, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/o_data", - "width": 8, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/o_sdr_state", - "width": 4, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/r_addr", - "width": 24, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/r_dm", - "width": 4, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/r_write_data", - "width": 32, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/state", - "width": 2, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_addr", - "width": 24, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_data_i", - "width": 32, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_data_o", - "width": 32, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_data_valid", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_dm", - "width": 4, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_last", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_rd_ack", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_rd_valid", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_read", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_write", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_wr_ack", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/_data", - "width": 8, - "probe_type": 1 } ] } @@ -302,7 +157,7 @@ }, { "name": "la0_clk", - "net": "i_sysclk", + "net": "clk_2", "path": [] }, { @@ -434,1798 +289,6 @@ "name": "la0_probe3", "net": "cpu_sync", "path": [] - }, - { - "name": "la0_probe4[0]", - "net": "addr_mux_out[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[1]", - "net": "addr_mux_out[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[2]", - "net": "addr_mux_out[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[3]", - "net": "addr_mux_out[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[4]", - "net": "addr_mux_out[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[5]", - "net": "addr_mux_out[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[6]", - "net": "addr_mux_out[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[7]", - "net": "addr_mux_out[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[8]", - "net": "addr_mux_out[8]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[9]", - "net": "addr_mux_out[9]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[10]", - "net": "addr_mux_out[10]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[11]", - "net": "addr_mux_out[11]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[12]", - "net": "addr_mux_out[12]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[13]", - "net": "addr_mux_out[13]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[14]", - "net": "addr_mux_out[14]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[15]", - "net": "addr_mux_out[15]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[16]", - "net": "addr_mux_out[16]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[17]", - "net": "addr_mux_out[17]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[18]", - "net": "addr_mux_out[18]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[19]", - "net": "addr_mux_out[19]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[20]", - "net": "addr_mux_out[20]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[21]", - "net": "addr_mux_out[21]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[22]", - "net": "addr_mux_out[22]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe4[23]", - "net": "addr_mux_out[23]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe5[0]", - "net": "counter[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe5[1]", - "net": "counter[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe6[0]", - "net": "data[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe6[1]", - "net": "data[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe6[2]", - "net": "data[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe6[3]", - "net": "data[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe6[4]", - "net": "data[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe6[5]", - "net": "data[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe6[6]", - "net": "data[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe6[7]", - "net": "data[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[0]", - "net": "i_addr[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[1]", - "net": "i_addr[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[2]", - "net": "i_addr[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[3]", - "net": "i_addr[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[4]", - "net": "i_addr[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[5]", - "net": "i_addr[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[6]", - "net": "i_addr[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[7]", - "net": "i_addr[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[8]", - "net": "i_addr[8]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[9]", - "net": "i_addr[9]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[10]", - "net": "i_addr[10]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[11]", - "net": "i_addr[11]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[12]", - "net": "i_addr[12]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[13]", - "net": "i_addr[13]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[14]", - "net": "i_addr[14]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[15]", - "net": "i_addr[15]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[16]", - "net": "i_addr[16]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[17]", - "net": "i_addr[17]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[18]", - "net": "i_addr[18]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[19]", - "net": "i_addr[19]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[20]", - "net": "i_addr[20]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[21]", - "net": "i_addr[21]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[22]", - "net": "i_addr[22]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[23]", - "net": "i_addr[23]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe7[24]", - "net": "i_addr[24]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe8", - "net": "i_arst", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe9", - "net": "i_cpuclk", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe10", - "net": "i_cs", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[0]", - "net": "i_data[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[1]", - "net": "i_data[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[2]", - "net": "i_data[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[3]", - "net": "i_data[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[4]", - "net": "i_data[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[5]", - "net": "i_data[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[6]", - "net": "i_data[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[7]", - "net": "i_data[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe12", - "net": "i_rwb", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[0]", - "net": "next_counter[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[1]", - "net": "next_counter[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe14[0]", - "net": "next_state[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe14[1]", - "net": "next_state[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[0]", - "net": "o_data[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[1]", - "net": "o_data[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[2]", - "net": "o_data[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[3]", - "net": "o_data[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[4]", - "net": "o_data[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[5]", - "net": "o_data[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[6]", - "net": "o_data[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[7]", - "net": "o_data[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[0]", - "net": "o_sdr_state[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[1]", - "net": "o_sdr_state[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[2]", - "net": "o_sdr_state[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[3]", - "net": "o_sdr_state[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[0]", - "net": "r_addr[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[1]", - "net": "r_addr[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[2]", - "net": "r_addr[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[3]", - "net": "r_addr[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[4]", - "net": "r_addr[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[5]", - "net": "r_addr[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[6]", - "net": "r_addr[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[7]", - "net": "r_addr[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[8]", - "net": "r_addr[8]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[9]", - "net": "r_addr[9]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[10]", - "net": "r_addr[10]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[11]", - "net": "r_addr[11]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[12]", - "net": "r_addr[12]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[13]", - "net": "r_addr[13]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[14]", - "net": "r_addr[14]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[15]", - "net": "r_addr[15]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[16]", - "net": "r_addr[16]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[17]", - "net": "r_addr[17]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[18]", - "net": "r_addr[18]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[19]", - "net": "r_addr[19]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[20]", - "net": "r_addr[20]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[21]", - "net": "r_addr[21]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[22]", - "net": "r_addr[22]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17[23]", - "net": "r_addr[23]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe18[0]", - "net": "r_dm[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe18[1]", - "net": "r_dm[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe18[2]", - "net": "r_dm[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe18[3]", - "net": "r_dm[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[0]", - "net": "r_write_data[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[1]", - "net": "r_write_data[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[2]", - "net": "r_write_data[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[3]", - "net": "r_write_data[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[4]", - "net": "r_write_data[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[5]", - "net": "r_write_data[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[6]", - "net": "r_write_data[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[7]", - "net": "r_write_data[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[8]", - "net": "r_write_data[8]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[9]", - "net": "r_write_data[9]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[10]", - "net": "r_write_data[10]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[11]", - "net": "r_write_data[11]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[12]", - "net": "r_write_data[12]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[13]", - "net": "r_write_data[13]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[14]", - "net": "r_write_data[14]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[15]", - "net": "r_write_data[15]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[16]", - "net": "r_write_data[16]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[17]", - "net": "r_write_data[17]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[18]", - "net": "r_write_data[18]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[19]", - "net": "r_write_data[19]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[20]", - "net": "r_write_data[20]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[21]", - "net": "r_write_data[21]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[22]", - "net": "r_write_data[22]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[23]", - "net": "r_write_data[23]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[24]", - "net": "r_write_data[24]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[25]", - "net": "r_write_data[25]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[26]", - "net": "r_write_data[26]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[27]", - "net": "r_write_data[27]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[28]", - "net": "r_write_data[28]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[29]", - "net": "r_write_data[29]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[30]", - "net": "r_write_data[30]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[31]", - "net": "r_write_data[31]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe20[0]", - "net": "state[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe20[1]", - "net": "state[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[0]", - "net": "w_addr[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[1]", - "net": "w_addr[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[2]", - "net": "w_addr[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[3]", - "net": "w_addr[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[4]", - "net": "w_addr[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[5]", - "net": "w_addr[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[6]", - "net": "w_addr[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[7]", - "net": "w_addr[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[8]", - "net": "w_addr[8]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[9]", - "net": "w_addr[9]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[10]", - "net": "w_addr[10]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[11]", - "net": "w_addr[11]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[12]", - "net": "w_addr[12]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[13]", - "net": "w_addr[13]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[14]", - "net": "w_addr[14]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[15]", - "net": "w_addr[15]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[16]", - "net": "w_addr[16]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[17]", - "net": "w_addr[17]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[18]", - "net": "w_addr[18]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[19]", - "net": "w_addr[19]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[20]", - "net": "w_addr[20]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[21]", - "net": "w_addr[21]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[22]", - "net": "w_addr[22]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21[23]", - "net": "w_addr[23]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[0]", - "net": "w_data_i[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[1]", - "net": "w_data_i[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[2]", - "net": "w_data_i[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[3]", - "net": "w_data_i[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[4]", - "net": "w_data_i[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[5]", - "net": "w_data_i[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[6]", - "net": "w_data_i[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[7]", - "net": "w_data_i[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[8]", - "net": "w_data_i[8]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[9]", - "net": "w_data_i[9]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[10]", - "net": "w_data_i[10]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[11]", - "net": "w_data_i[11]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[12]", - "net": "w_data_i[12]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[13]", - "net": "w_data_i[13]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[14]", - "net": "w_data_i[14]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[15]", - "net": "w_data_i[15]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[16]", - "net": "w_data_i[16]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[17]", - "net": "w_data_i[17]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[18]", - "net": "w_data_i[18]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[19]", - "net": "w_data_i[19]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[20]", - "net": "w_data_i[20]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[21]", - "net": "w_data_i[21]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[22]", - "net": "w_data_i[22]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[23]", - "net": "w_data_i[23]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[24]", - "net": "w_data_i[24]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[25]", - "net": "w_data_i[25]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[26]", - "net": "w_data_i[26]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[27]", - "net": "w_data_i[27]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[28]", - "net": "w_data_i[28]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[29]", - "net": "w_data_i[29]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[30]", - "net": "w_data_i[30]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22[31]", - "net": "w_data_i[31]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[0]", - "net": "w_data_o[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[1]", - "net": "w_data_o[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[2]", - "net": "w_data_o[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[3]", - "net": "w_data_o[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[4]", - "net": "w_data_o[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[5]", - "net": "w_data_o[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[6]", - "net": "w_data_o[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[7]", - "net": "w_data_o[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[8]", - "net": "w_data_o[8]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[9]", - "net": "w_data_o[9]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[10]", - "net": "w_data_o[10]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[11]", - "net": "w_data_o[11]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[12]", - "net": "w_data_o[12]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[13]", - "net": "w_data_o[13]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[14]", - "net": "w_data_o[14]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[15]", - "net": "w_data_o[15]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[16]", - "net": "w_data_o[16]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[17]", - "net": "w_data_o[17]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[18]", - "net": "w_data_o[18]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[19]", - "net": "w_data_o[19]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[20]", - "net": "w_data_o[20]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[21]", - "net": "w_data_o[21]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[22]", - "net": "w_data_o[22]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[23]", - "net": "w_data_o[23]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[24]", - "net": "w_data_o[24]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[25]", - "net": "w_data_o[25]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[26]", - "net": "w_data_o[26]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[27]", - "net": "w_data_o[27]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[28]", - "net": "w_data_o[28]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[29]", - "net": "w_data_o[29]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[30]", - "net": "w_data_o[30]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23[31]", - "net": "w_data_o[31]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe24", - "net": "w_data_valid", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe25[0]", - "net": "w_dm[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe25[1]", - "net": "w_dm[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe25[2]", - "net": "w_dm[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe25[3]", - "net": "w_dm[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe26", - "net": "w_last", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe27", - "net": "w_rd_ack", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe28", - "net": "w_rd_valid", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe29", - "net": "w_read", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe30", - "net": "w_write", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe31", - "net": "w_wr_ack", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe32[0]", - "net": "_data[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe32[1]", - "net": "_data[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe32[2]", - "net": "_data[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe32[3]", - "net": "_data[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe32[4]", - "net": "_data[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe32[5]", - "net": "_data[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe32[6]", - "net": "_data[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe32[7]", - "net": "_data[7]", - "path": [ - "u_sdram_adapter" - ] } ] } @@ -2245,7 +308,7 @@ { "name": "cpu_addr", "width": 16, - "clk_domain": "i_sysclk", + "clk_domain": "clk_2", "selected_probe_type": "DATA AND TRIGGER", "child": [], "path": [], @@ -2255,7 +318,7 @@ { "name": "cpu_data_in", "width": 8, - "clk_domain": "i_sysclk", + "clk_domain": "clk_2", "selected_probe_type": "DATA AND TRIGGER", "child": [], "path": [], @@ -2265,7 +328,7 @@ { "name": "cpu_rwb", "width": 1, - "clk_domain": "i_sysclk", + "clk_domain": "clk_2", "selected_probe_type": "DATA AND TRIGGER", "child": [], "path": [] @@ -2273,336 +336,10 @@ { "name": "cpu_sync", "width": 1, - "clk_domain": "i_sysclk", + "clk_domain": "clk_2", "selected_probe_type": "DATA AND TRIGGER", "child": [], "path": [] - }, - { - "name": "addr_mux_out", - "width": 24, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 23, - "net_idx_right": 0 - }, - { - "name": "counter", - "width": 2, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 1, - "net_idx_right": 0 - }, - { - "name": "data", - "width": 8, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 7, - "net_idx_right": 0 - }, - { - "name": "i_addr", - "width": 25, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 24, - "net_idx_right": 0 - }, - { - "name": "i_arst", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "i_cpuclk", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "i_cs", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "i_data", - "width": 8, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 7, - "net_idx_right": 0 - }, - { - "name": "i_rwb", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "next_counter", - "width": 2, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 1, - "net_idx_right": 0 - }, - { - "name": "next_state", - "width": 2, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 1, - "net_idx_right": 0 - }, - { - "name": "o_data", - "width": 8, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 7, - "net_idx_right": 0 - }, - { - "name": "o_sdr_state", - "width": 4, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 3, - "net_idx_right": 0 - }, - { - "name": "r_addr", - "width": 24, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 23, - "net_idx_right": 0 - }, - { - "name": "r_dm", - "width": 4, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 3, - "net_idx_right": 0 - }, - { - "name": "r_write_data", - "width": 32, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 31, - "net_idx_right": 0 - }, - { - "name": "state", - "width": 2, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 1, - "net_idx_right": 0 - }, - { - "name": "w_addr", - "width": 24, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 23, - "net_idx_right": 0 - }, - { - "name": "w_data_i", - "width": 32, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 31, - "net_idx_right": 0 - }, - { - "name": "w_data_o", - "width": 32, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 31, - "net_idx_right": 0 - }, - { - "name": "w_data_valid", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_dm", - "width": 4, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 3, - "net_idx_right": 0 - }, - { - "name": "w_last", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_rd_ack", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_rd_valid", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_read", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_write", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_wr_ack", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "_data", - "width": 8, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 7, - "net_idx_right": 0 } ], "top_module": "super6502", diff --git a/hw/efinix_fpga/ip/bram/bram_ini.vh b/hw/efinix_fpga/ip/bram/bram_ini.vh index 54fba75..fb9ba57 100644 --- a/hw/efinix_fpga/ip/bram/bram_ini.vh +++ b/hw/efinix_fpga/ip/bram/bram_ini.vh @@ -4,9 +4,9 @@ input integer index;//Mode type input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved case (index) 0: bram_ini_table= -(val_== 0)?256'h000000020000f700010000ca00010000000009d000ff00010000bd0000a000a2: -(val_== 1)?256'h060000ef000ff0008d0006800000000a90004800055000a9000fe00080000100: -(val_== 2)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_== 0)?256'h00ef000ff0009c0001000085000ef000f8000ad000ef000fd0008d000ff000a9: +(val_== 1)?256'h086000f40009000020000e90003800010000e500038000aa000ef000f8000ad0: +(val_== 2)?256'h00000000000000000000000000000000000ed00080000ef000ff000ee0001000: (val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000: (val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000: (val_== 5)?256'h0000000000000000000000000000000000000000000000000000000000000000: diff --git a/hw/efinix_fpga/ip/bram/init_hex.mem b/hw/efinix_fpga/ip/bram/init_hex.mem index 9d0ca45..7e115d3 100644 --- a/hw/efinix_fpga/ip/bram/init_hex.mem +++ b/hw/efinix_fpga/ip/bram/init_hex.mem @@ -1,35 +1,35 @@ -a2 -0a -bd -10 +a9 ff -9d -00 -10 -ca -10 -f7 -20 -00 -10 -80 -fe -a9 -55 -48 -a9 -00 -68 8d +fd +ef +ad +f8 +ef +85 +10 +9c ff ef -60 -00 -00 -00 -00 -00 -00 +ad +f8 +ef +aa +38 +e5 +10 +38 +e9 +20 +90 +f4 +86 +10 +ee +ff +ef +80 +ed 00 00 00 diff --git a/hw/efinix_fpga/super6502.sv b/hw/efinix_fpga/super6502.sv index 21c814a..bfcb4fa 100644 --- a/hw/efinix_fpga/super6502.sv +++ b/hw/efinix_fpga/super6502.sv @@ -66,23 +66,28 @@ end logic w_rom_cs; logic w_leds_cs; logic w_sdram_cs; +logic w_timer_cs; addr_decode u_addr_decode( .i_addr(cpu_addr), .o_rom_cs(w_rom_cs), .o_leds_cs(w_leds_cs), + .o_timer_cs(w_timer_cs), .o_sdram_cs(w_sdram_cs) ); logic [7:0] w_rom_data_out; logic [7:0] w_leds_data_out; +logic [7:0] w_timer_data_out; logic [7:0] w_sdram_data_out; always_comb begin if (w_rom_cs) cpu_data_out = w_rom_data_out; else if (w_leds_cs) - cpu_data_out = w_leds_data_out; + cpu_data_out = w_leds_data_out; + else if (w_timer_cs) + cpu_data_out = w_timer_data_out; else if (w_sdram_cs) cpu_data_out = w_sdram_data_out; else @@ -110,6 +115,16 @@ leds u_leds( .o_leds(leds) ); +timer u_timer( + .clk(clk_2), + .reset(~cpu_resb), + .i_data(cpu_data_in), + .o_data(w_timer_data_out), + .cs(w_timer_cs), + .rwb(cpu_rwb), + .addr(cpu_addr[2:0]) +); + sdram_adapter u_sdram_adapter( .i_cpuclk(clk_2), .i_arst(~button_reset), diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index 81d0831..d62979b 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,5 +1,5 @@ - + diff --git a/hw/efinix_fpga/test_programs/Makefile b/hw/efinix_fpga/test_programs/Makefile index 955951e..f042c1c 100644 --- a/hw/efinix_fpga/test_programs/Makefile +++ b/hw/efinix_fpga/test_programs/Makefile @@ -1,4 +1,4 @@ -TARGETS=stacktest runram +TARGETS=stacktest runram timer all: $(TARGETS) @@ -7,6 +7,6 @@ $(TARGETS): xxd -ps $@ | fold -w 2 > $@.hex clean: - rm $(TARGETS) + rm -f $(TARGETS) rm *.hex rm *.list diff --git a/hw/efinix_fpga/test_programs/timer.s b/hw/efinix_fpga/test_programs/timer.s new file mode 100644 index 0000000..6e8590d --- /dev/null +++ b/hw/efinix_fpga/test_programs/timer.s @@ -0,0 +1,38 @@ +.code + +LEDS = $efff +TIMER_BASE = $eff8 +TIMER_DIVISOR = 5 + +TIMER_OLD = $10 + +main: + lda #$ff + sta TIMER_BASE+TIMER_DIVISOR + lda TIMER_BASE + sta TIMER_OLD + stz LEDS + + +; load the new value of the timer in a +; subtract the old value of the timer +; if the result is greater than 30, then do something + +loop: + lda TIMER_BASE + tax + sec + sbc TIMER_OLD + sec + sbc #$20 + bcc loop + + stx TIMER_OLD + inc LEDS + bra loop + +.segment "VECTORS" + +.addr main +.addr main +.addr main diff --git a/hw/efinix_fpga/timer.sv b/hw/efinix_fpga/timer.sv index 05c0f51..106e788 100644 --- a/hw/efinix_fpga/timer.sv +++ b/hw/efinix_fpga/timer.sv @@ -22,13 +22,13 @@ logic [7:0] divisor, status, control; // -------------------------------- // | 3 | IRQ Counter High | // -------------------------------- -// | 4 | Reserved | +// | 4 | Control | // -------------------------------- // | 5 | Divisor | // -------------------------------- // | 6 | Status | // -------------------------------- -// | 7 | Control | +// | 7 | Reserved | // --------------------------------