From aba37ec98d4d3062d450dccfe41c133cf0305a2a Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 23 Nov 2023 11:47:33 -0800
Subject: [PATCH 1/2] Decouple spi_clk from cpu_clk

---
 hw/efinix_fpga/src/spi_controller.sv | 56 +++++++++++++++++-----------
 hw/efinix_fpga/src/super6502.sv      |  3 +-
 2 files changed, 37 insertions(+), 22 deletions(-)

diff --git a/hw/efinix_fpga/src/spi_controller.sv b/hw/efinix_fpga/src/spi_controller.sv
index 9f5c09d..7175191 100644
--- a/hw/efinix_fpga/src/spi_controller.sv
+++ b/hw/efinix_fpga/src/spi_controller.sv
@@ -1,5 +1,6 @@
 module spi_controller(
-    input i_clk,
+    input i_clk_cpu,
+    input i_clk_50,
     input i_rst,
 
     input i_cs,
@@ -37,7 +38,9 @@ assign o_spi_cs = ~r_control[0];
 assign o_spi_clk = spi_clk;
 assign o_spi_mosi = r_spi_mosi;
 
-always @(negedge i_clk) begin
+logic working;
+
+always @(negedge i_clk_cpu) begin
     if (i_rst) begin
         r_baud_rate <= 8'h1;
         r_input_data <= '0;
@@ -48,6 +51,7 @@ always @(negedge i_clk) begin
         spi_clk <= '0;
         active <= '0;
     end else begin
+        active <= '0;
         if (~i_rwb & i_cs) begin
             unique case (i_addr)
                 0: r_baud_rate <= i_data;
@@ -59,28 +63,38 @@ always @(negedge i_clk) begin
                 3: r_control <= i_data;
             endcase
         end
+        working <= active_f;
+    end
 
-        if (active) begin
-            r_spi_mosi <= r_output_data[7];
-            r_clock_counter <= r_clock_counter + 9'b1;
-            if (r_clock_counter >= r_baud_rate) begin
-                r_clock_counter <= '0;
-                spi_clk <= ~spi_clk;
-                // rising edge
-                if (spi_clk == '0) begin
-                    r_output_data <= r_output_data << 1;
-                    count <= count + 1;
-                end
-                // falling edge
-                if (spi_clk == '1) begin
-                    r_input_data <= {r_input_data[6:0], i_spi_miso};
-                    if (count == '0) begin
-                        active <= '0;
-                    end
+end
+
+logic active_f;
+logic [7:0] r_output_data_f;
+
+
+always @(posedge i_clk_50) begin
+    if (active_f) begin
+        r_spi_mosi <= r_output_data_f[7];
+        r_clock_counter <= r_clock_counter + 9'b1;
+        if (r_clock_counter >= r_baud_rate) begin
+            r_clock_counter <= '0;
+            spi_clk <= ~spi_clk;
+            // rising edge
+            if (spi_clk == '0) begin
+                r_output_data_f <= r_output_data_f << 1;
+                count <= count + 1;
+            end
+            // falling edge
+            if (spi_clk == '1) begin
+                r_input_data <= {r_input_data[6:0], i_spi_miso};
+                if (count == '0) begin
+                    active_f <= '0;
                 end
             end
-
         end
+    end else begin
+        r_output_data_f <= r_output_data;
+        active_f <= active;
     end
 end
 
@@ -89,7 +103,7 @@ always_comb begin
         0: o_data = r_baud_rate;
         1: o_data = r_input_data;
         2:;
-        3: o_data = {active, r_control[6:0]};
+        3: o_data = {working, r_control[6:0]};
         default: o_data = 'x;
     endcase
 end
diff --git a/hw/efinix_fpga/src/super6502.sv b/hw/efinix_fpga/src/super6502.sv
index d33827e..28b07f1 100644
--- a/hw/efinix_fpga/src/super6502.sv
+++ b/hw/efinix_fpga/src/super6502.sv
@@ -250,7 +250,8 @@ uart_wrapper u_uart(
 assign w_int_in[1] = w_uart_irq;
 
 spi_controller spi_controller(
-    .i_clk(clk_cpu),
+    .i_clk_cpu(clk_cpu),
+    .i_clk_50(clk_50),
     .i_rst(~cpu_resb),
     .i_cs(w_spi_cs),
     .i_rwb(cpu_rwb),

From 8721c816fcdbb09d71434ac90767b220de407541 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 23 Nov 2023 12:06:19 -0800
Subject: [PATCH 2/2] Move fast signals to fast reset

---
 hw/efinix_fpga/src/spi_controller.sv | 15 +++++++++++----
 hw/efinix_fpga/super6502.xml         |  2 +-
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/hw/efinix_fpga/src/spi_controller.sv b/hw/efinix_fpga/src/spi_controller.sv
index 7175191..316de82 100644
--- a/hw/efinix_fpga/src/spi_controller.sv
+++ b/hw/efinix_fpga/src/spi_controller.sv
@@ -43,12 +43,8 @@ logic working;
 always @(negedge i_clk_cpu) begin
     if (i_rst) begin
         r_baud_rate <= 8'h1;
-        r_input_data <= '0;
         r_output_data <= '0;
         r_control <= '0;
-        r_clock_counter <= '0;
-        count <= '0;
-        spi_clk <= '0;
         active <= '0;
     end else begin
         active <= '0;
@@ -71,8 +67,19 @@ end
 logic active_f;
 logic [7:0] r_output_data_f;
 
+logic reset_f;
+always @(posedge i_clk_50) begin
+    reset_f <= i_rst;
+end
 
 always @(posedge i_clk_50) begin
+    if (reset_f) begin
+        r_input_data <= '0;
+        r_clock_counter <= '0;
+        count <= '0;
+        spi_clk <= '0;
+    end
+
     if (active_f) begin
         r_spi_mosi <= r_output_data_f[7];
         r_clock_counter <= r_clock_counter + 9'b1;
diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml
index abac6c2..da80207 100644
--- a/hw/efinix_fpga/super6502.xml
+++ b/hw/efinix_fpga/super6502.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="super6502" description="" last_change_date="Sun November 19 2023 15:04:04" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="super6502" description="" last_change_date="Thu November 23 2023 12:03:00" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion"/>
         <efx:device name="T20F256"/>