From 8e87345f222772e54e71a0749df25b2c4dbacf96 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Mon, 19 Aug 2024 17:40:05 -0700
Subject: [PATCH] Add verilog ethernet

---
 .gitmodules                                | 3 +++
 hw/super6502_fpga/src/sub/verilog-ethernet | 1 +
 2 files changed, 4 insertions(+)
 create mode 160000 hw/super6502_fpga/src/sub/verilog-ethernet

diff --git a/.gitmodules b/.gitmodules
index ef62624..fb789b9 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -13,3 +13,6 @@
 [submodule "hw/super6502_fpga/src/sub/sdspi"]
 	path = hw/super6502_fpga/src/sub/sd_controller_wrapper/sdspi
 	url = ../sdspi.git
+[submodule "hw/super6502_fpga/src/sub/verilog-ethernet"]
+	path = hw/super6502_fpga/src/sub/verilog-ethernet
+	url = ../verilog-ethernet.git
diff --git a/hw/super6502_fpga/src/sub/verilog-ethernet b/hw/super6502_fpga/src/sub/verilog-ethernet
new file mode 160000
index 0000000..2542187
--- /dev/null
+++ b/hw/super6502_fpga/src/sub/verilog-ethernet
@@ -0,0 +1 @@
+Subproject commit 2542187ec93b7bf1c1dbdfc02981aad0eb01054a