Add up dest parser

This commit is contained in:
Byron Lathi
2024-09-08 14:25:00 -07:00
parent ef20f1477d
commit 945889e542
8 changed files with 202 additions and 9 deletions

View File

@@ -62,8 +62,8 @@ async def test_simple(dut):
dut_ip = "172.0.0.2"
tb_ip = "172.0.0.1"
dut_port = 1234
tb_port = 5678
dut_port = 0x1234
tb_port = 0x5678
tb_mac = "02:00:00:11:22:33"
@@ -129,7 +129,7 @@ async def test_simple(dut):
dut_seq = tcp_packet.seq
tb_seq = 0x12345678
tb_seq = 0x11111111
tcp_synack = Ether(dst=dut_mac, src=tb_mac)
tcp_synack /= IP(src=tb_ip, dst=dut_ip)

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@@ -15,4 +15,6 @@ src/tcp_stream.sv
src/tcp.sv
src/eth_wrapper.sv
src/ip_arb_mux_wrapper.sv
src/ip_demux_wrapper.sv
src/ip_demux_wrapper.sv
src/tcp_dest_decap.sv
src/tcp_parser.sv

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@@ -31,9 +31,9 @@ module network_processor #(
`define PROTO_TCP 8'h6
`define PROTO_UDP 8'h11
localparam ICMP_IDX = 0;
localparam ICMP_IDX = 2;
localparam UDP_IDX = 1;
localparam TCP_IDX = 2;
localparam TCP_IDX = 0;
localparam MAC_DATA_WIDTH = 8;
localparam AXIS_DATA_WIDTH = 8;

View File

@@ -65,11 +65,9 @@ localparam DEST_WIDTH = 8;
localparam ID_WIDTH = 8;
ip_intf #(.DATA_WIDTH(8)) tcp_stream_tx_ip [NUM_TCP]();
ip_intf #(.DATA_WIDTH(8)) tcp_rx_ip [NUM_TCP]();
ip_intf #(.DATA_WIDTH(8)) tcp_delayed_rx_ip();
ip_intf #(.DATA_WIDTH(8)) tcp_stream_rx_ip [NUM_TCP]();
axis_intf #(.DATA_WIDTH(8)) tcp_stream_rx_axis [NUM_TCP]();
axil_intf m2s_stream_axil[NUM_TCP]();
axil_intf s2m_stream_axil[NUM_TCP]();
@@ -186,9 +184,48 @@ ip_arb_mux_wrapper #(
.m_ip (m_ip)
);
// dest decap
logic [15:0] tcp_dest;
logic tcp_dest_valid;
tcp_dest_decap u_tcp_dest_decap(
.i_clk (i_clk),
.i_rst (i_rst),
.s_ip (s_ip),
.m_ip (tcp_delayed_rx_ip),
.o_tcp_dest (tcp_dest),
.o_tcp_dest_valid(tcp_dest_valid)
);
// rx_stream demux (ip)
logic [$clog2(NUM_TCP)-1:0] tcp_demux_sel;
logic [15:0] tcp_dests [NUM_TCP];
always_comb begin : TCP_DEST_SEL
for (int i = 0; i < NUM_TCP; i++) begin
if (tcp_dest == tcp_dests[i]) begin
tcp_demux_sel = i;
end
end
end
ip_demux_wrapper #(
.M_COUNT(NUM_TCP)
) u_ip_demux (
.clk (i_clk),
.rst (i_rst),
.s_ip (tcp_delayed_rx_ip),
.m_ip (tcp_stream_rx_ip),
.enable (tcp_dest_valid),
.drop ('0),
.select (tcp_demux_sel)
);
generate
@@ -223,6 +260,8 @@ generate
.s_cpuif_wr_ack (tcp_hwif_in.tcp_streams[i].wr_ack),
.s_cpuif_wr_err (),
.o_tcp_port (tcp_dests[i]),
.s_ip_rx (tcp_stream_rx_ip[i]),
.m_ip_tx (tcp_stream_tx_ip[i]),

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@@ -0,0 +1,132 @@
module tcp_dest_decap (
input i_clk,
input i_rst,
ip_intf.SLAVE s_ip,
ip_intf.MASTER m_ip,
output wire [15:0] o_tcp_dest,
output wire o_tcp_dest_valid
);
logic [15:0] tcp_dest, tcp_dest_next;
logic [31:0] pipe, pipe_next;
logic [3:0] pipe_valid, pipe_valid_next;
logic [3:0] pipe_last, pipe_last_next;
enum logic [1:0] {PORTS, PASSTHROUGH} state, state_next;
logic [1:0] counter, counter_next;
// We don't need the mac addresses or the ethertype.
assign m_ip.eth_src_mac = '0;
assign m_ip.eth_dest_mac = '0;
assign m_ip.eth_type = '0;
assign o_tcp_dest = tcp_dest;
skidbuffer #(
.DW(160)
) u_tcp_ip_hdr_skidbuffer (
.i_clk (i_clk),
.i_reset (i_rst),
.i_valid (s_ip.ip_hdr_valid),
.o_ready (s_ip.ip_hdr_ready),
.i_data ({
s_ip.ip_version,
s_ip.ip_ihl,
s_ip.ip_dscp,
s_ip.ip_ecn,
s_ip.ip_length,
s_ip.ip_identification,
s_ip.ip_flags,
s_ip.ip_fragment_offset,
s_ip.ip_ttl,
s_ip.ip_protocol,
s_ip.ip_header_checksum,
s_ip.ip_source_ip,
s_ip.ip_dest_ip
}),
.o_valid (m_ip.ip_hdr_valid),
.i_ready (m_ip.ip_hdr_ready),
.o_data ({
m_ip.ip_version,
m_ip.ip_ihl,
m_ip.ip_dscp,
m_ip.ip_ecn,
m_ip.ip_length,
m_ip.ip_identification,
m_ip.ip_flags,
m_ip.ip_fragment_offset,
m_ip.ip_ttl,
m_ip.ip_protocol,
m_ip.ip_header_checksum,
m_ip.ip_source_ip,
m_ip.ip_dest_ip
})
);
always_ff @(posedge i_clk) begin
if (i_rst) begin
tcp_dest <= '0;
pipe <= '0;
pipe_valid <= '0;
pipe_last <= '0;
state <= PORTS;
counter <= '0;
end else begin
tcp_dest <= tcp_dest_next;
pipe <= pipe_next;
pipe_valid <= pipe_valid_next;
pipe_last <= pipe_last_next;
state <= state_next;
counter <= counter_next;
end
end
always_comb begin
tcp_dest_next = tcp_dest;
state_next = state;
pipe_next = pipe;
pipe_valid_next = pipe_valid;
pipe_last_next = pipe_last;
counter_next = pipe;
s_ip.ip_payload_axis_tready = '0;
case (state)
PORTS: begin
s_ip.ip_payload_axis_tready = 1;
o_tcp_dest_valid = '0;
if (s_ip.ip_payload_axis_tvalid) begin
counter_next = counter + 1;
pipe_valid_next = {pipe_valid[2:0], 1'b1};
pipe_next = {pipe_next[23:0], s_ip.ip_payload_axis_tdata};
if (counter == 2'h3) begin
state_next = PASSTHROUGH;
tcp_dest_next = pipe_next[15:0];
end
end
end
PASSTHROUGH: begin
// match ready except if we have seen last, then just finish it out.
pipe_valid_next = {pipe_valid[2:0], s_ip.ip_payload_axis_tvalid};
pipe_last_next = {pipe_last[2:0], s_ip.ip_payload_axis_tlast};
pipe_next = {pipe_next[23:0], s_ip.ip_payload_axis_tdata};
s_ip.ip_payload_axis_tready = m_ip.ip_payload_axis_tready;
m_ip.ip_payload_axis_tvalid = pipe_valid[3];
m_ip.ip_payload_axis_tlast = pipe_last[3];
m_ip.ip_payload_axis_tdata = pipe[31:24];
o_tcp_dest_valid = '1;
end
endcase
end
endmodule

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@@ -0,0 +1,11 @@
module tcp_parser(
input wire i_clk,
input wire i_rst,
ip_intf.SLAVE s_ip
);
assign s_ip.ip_hdr_ready = '1;
assign s_ip.ip_payload_axis_tready = '1;
endmodule

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@@ -20,6 +20,8 @@ module tcp_stream #(
output wire s_cpuif_wr_ack,
output wire s_cpuif_wr_err,
output logic [15:0] o_tcp_port,
ip_intf.SLAVE s_ip_rx,
ip_intf.MASTER m_ip_tx,
@@ -49,6 +51,7 @@ logic w_tx_packet_done;
tcp_pkg::rx_msg_t rx_msg;
assign o_tcp_port = hwif_out.source_port.d.value;
tcp_stream_regs u_tcp_stream_regs (
@@ -192,6 +195,12 @@ tcp_packet_generator u_tcp_packet_generator (
);
// parser
tcp_parser u_tcp_parser (
.i_clk (clk),
.i_rst (rst),
.s_ip (s_ip_rx)
);
// rx control