diff --git a/hw/efinix_fpga/simulation/Makefile b/hw/efinix_fpga/simulation/Makefile
index c9e6218..8fc9a76 100644
--- a/hw/efinix_fpga/simulation/Makefile
+++ b/hw/efinix_fpga/simulation/Makefile
@@ -13,7 +13,7 @@ TEST_PROGRAM=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).
 TOP_MODULE=sim_top
 TARGET=sim_top
 INIT_MEM=init_hex.mem
-FLAGS=-DSIM
+FLAGS=-DSIM -DRTL_SIM
 
 all: $(INIT_MEM)
 	iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv
index bab1306..da53126 100644
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -24,7 +24,7 @@ end
 
 // clk_50
 initial begin
-	r_clk_50 <= '0;
+	r_clk_50 <= '1;
 	forever begin
 		#10 r_clk_50 <= ~r_clk_50;
 	end
@@ -32,7 +32,7 @@ end
 
 // clk_2
 initial begin
-	r_clk_2 <= '0;
+	r_clk_2 <= '1;
 	forever begin
 		#250 r_clk_2 <= ~r_clk_2;
 	end
@@ -86,7 +86,7 @@ cpu_65c02 u_cpu(
 super6502 u_dut(
 	.i_sysclk(r_sysclk),
 	.i_sdrclk(r_sdrclk),
-	.i_tACclk(r_sdrclk),
+	.i_tACclk(~r_sdrclk),
 	.clk_50(r_clk_50),
 	.clk_2(r_clk_2),
 	.button_reset(button_reset),