Create interrupt controller

hw/efinix_fpga/simulation/Makefile

@@ -0,0 +1,17 @@
+TARGETS= timer interrupt_controller
+TB=$(patsubst %, %_tb.sv, $(TARGETS))
+
+all: $(TARGETS)
+
+timer: timer_tb.sv
+	iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
+
+interrupt_controller: interrupt_controller_tb.sv
+	iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
+
+.PHONY: clean
+
+clean:
+	rm -f $(TARGETS)
+	rm -f *.vcd
+	rm -f *.vvp