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Add tcp regs and switch to verilator

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This commit is contained in:
Byron Lathi
2024-08-17 11:56:01 -07:00
parent 52a76e3a85
commit 9b2a40df06
30 changed files with 1340 additions and 78 deletions
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13
hw/super6502_fpga/src/sim/Makefile
View File

@@ -1,7 +1,7 @@
FPGA_SRCS_LIST=../../sources.list
SIM_SRCS_LIST=sources.list
SUPER6502_FPGA_SOURCES=$(foreach file, $(shell cat $(FPGA_SRCS_LIST)), ../../$(file))
SUPER6502_FPGA_SOURCES=$(shell rtl-manifest $(FPGA_SRCS_LIST))
SIM_SOURCES=$(shell cat $(SIM_SRCS_LIST))
INCLUDE=include/sdram_controller_define.vh
@@ -13,13 +13,19 @@ SD_IMAGE=sd_image.bin
FLAGS=-DSIM -DRTL_SIM -DVERILATOR -DSDIO_AXI
# IVERILOG=$(REPO_TOP)/../iverilog/local/bin/iverilog -v
IVERILOG=iverilog
all: waves
waves: $(TB_NAME)
./$(TB_NAME) -fst
# ./$(TB_NAME) -fst
./obj_dir/Vsim_top
$(TB_NAME): $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) $(COPY_FILES) $(SD_IMAGE)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
# $(IVERILOG) -g2005-sv $(FLAGS) -s $@ -o $@ $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
verilator --binary $(FLAGS) $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) +incdir+../../ -Wno-BLKANDNBLK -Wno-fatal -j 16 --top sim_top --trace-fst -Wno-ASSIGNDLY
$(SD_IMAGE):
dd if=/dev/urandom bs=1 count=65536 of=$(SD_IMAGE)
@@ -34,3 +40,4 @@ clean:
rm -rf $(COPY_FILES)
rm -rf $(TB_NAME)
rm -rf sim_top.vcd
rm -rf obj_dir

4
hw/super6502_fpga/src/sim/hvl/sim_top.sv
View File

@@ -179,13 +179,15 @@ IOBUF dat_buf (
.IO(w_sd_dat)
);
wire [2:0] w_sd_dat_unused;
mdl_sdio #(
.LGMEMSZ(16),
.MEMFILE("sd_image.bin")
) u_sd_card_emu (
.sd_clk(o_sd_clk),
.sd_cmd(w_sd_cmd),
.sd_dat(w_sd_dat)
.sd_dat({w_sd_dat_unused, w_sd_dat})
);
initial begin

2
hw/super6502_fpga/src/sim/sources.list
View File

@@ -1,7 +1,7 @@
hvl/sim_top.sv
sub/verilog-6502/ALU.v
sub/verilog-6502/cpu_65c02.v
sub/sim_sdram/generic_sdr.v
sub/sim_sdram/generic_sdr_stub.v
../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdio.v
../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdcmd.v
../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdrx.v

26
hw/super6502_fpga/src/sim/sub/sim_sdram/generic_sdr.v
View File

@@ -1127,19 +1127,19 @@ parameter mem_sizes = 2**(ROW_BITS+COL_BITS) - 1;
tCMS = 1.5, // CS#, RAS#, CAS#, WE#, DQM# Setup Time
tDH = 0.8, // Data-in Hold Time
tDS = 1.5; // Data-in Setup Time
$width (posedge Clk, tCH);
$width (negedge Clk, tCL);
$period (negedge Clk, tCK3);
$period (posedge Clk, tCK3);
$setuphold(posedge Clk, Cke, tCKS, tCKH);
$setuphold(posedge Clk, Cs_n, tCMS, tCMH);
$setuphold(posedge Clk, Cas_n, tCMS, tCMH);
$setuphold(posedge Clk, Ras_n, tCMS, tCMH);
$setuphold(posedge Clk, We_n, tCMS, tCMH);
$setuphold(posedge Clk, Addr, tAS, tAH);
$setuphold(posedge Clk, Ba, tAS, tAH);
$setuphold(posedge Clk, Dqm, tCMS, tCMH);
$setuphold(posedge Dq_chk, Dq, tDS, tDH);
// $width (posedge Clk, tCH);
// $width (negedge Clk, tCL);
// $period (negedge Clk, tCK3);
// $period (posedge Clk, tCK3);
// $setuphold(posedge Clk, Cke, tCKS, tCKH);
// $setuphold(posedge Clk, Cs_n, tCMS, tCMH);
// $setuphold(posedge Clk, Cas_n, tCMS, tCMH);
// $setuphold(posedge Clk, Ras_n, tCMS, tCMH);
// $setuphold(posedge Clk, We_n, tCMS, tCMH);
// $setuphold(posedge Clk, Addr, tAS, tAH);
// $setuphold(posedge Clk, Ba, tAS, tAH);
// $setuphold(posedge Clk, Dqm, tCMS, tCMH);
// $setuphold(posedge Dq_chk, Dq, tDS, tDH);
endspecify
endmodule

106
hw/super6502_fpga/src/sim/sub/sim_sdram/generic_sdr_stub.v Normal file
View File

@@ -0,0 +1,106 @@
/**************************************************************************
*
* File Name: sdr.v
* Version: 2.2
* Date: October 12th, 2010
* Model: BUS Functional
* Simulator: Model Technology
*
* Dependencies: None
*
* Email: modelsupport@micron.com
* Company: Micron Technology, Inc.
*
* Description: Micron SDRAM Verilog model
*
* Limitation: - Doesn't check for refresh timing
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
* Copyright <EFBFBD> 2001 Micron Semiconductor Products, Inc.
* All rights researved
*
* Rev Author Date Changes
* --- -------------------------- ---------------------------------------
* 2.3 SH 05/12/2016 - Update tAC, tHZ timing
* Micron Technology Inc.
*
* 2.2 SH 10/12/2010 - Combine all parts into sdr_parameters.vh
* Micron Technology Inc.
*
* 2.1 SH 06/06/2002 - Typo in bank multiplex
* Micron Technology Inc.
*
* 2.0 SH 04/30/2002 - Second release
* Micron Technology Inc.
*
**************************************************************************/
`timescale 1ns / 1ps
`define x8
`define CLK_200
`define SYS_CLK_100
module generic_sdr (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
`include "include/sdram_controller_define.vh"
parameter tCK = 1000/fCK_MHz; // tCK ns Nominal Clock Cycle Time
`ifdef CLK_200
parameter real tAC3 = 4.5; // tAC3 ns Access time from CLK (pos edge) CL = 3
parameter real tAC2 = 4.5; // tAC2 ns Access time from CLK (pos edge) CL = 2
parameter real tAC1 = 4.5; // tAC1 ns Parameter definition for compilation - CL = 1 illegal for sg75
`elsif CLK_166
parameter real tAC3 = 5.4; // tAC3 ns Access time from CLK (pos edge) CL = 3
parameter real tAC2 = 5.4; // tAC2 ns Access time from CLK (pos edge) CL = 2
parameter real tAC1 = 5.4; // tAC1 ns Parameter definition for compilation - CL = 1 illegal for sg75
`elsif CLK_133
parameter real tAC3 = 6.0; // tAC3 ns Access time from CLK (pos edge) CL = 3
parameter real tAC2 = 6.0; // tAC2 ns Access time from CLK (pos edge) CL = 2
parameter real tAC1 = 6.0; // tAC1 ns Parameter definition for compilation - CL = 1 illegal for sg75
`endif
`ifdef CLK_200
parameter real tHZ3 = 4.5; // tHZ3 ns Data Out High Z time - CL = 3
parameter real tHZ2 = 4.5; // tHZ2 ns Data Out High Z time - CL = 2
parameter real tHZ1 = 4.5; // tHZ1 ns Parameter definition for compilation - CL = 1 illegal for sg75
`elsif CLK_166
parameter real tHZ3 = 5.4; // tHZ3 ns Data Out High Z time - CL = 3
parameter real tHZ2 = 5.4; // tHZ2 ns Data Out High Z time - CL = 2
parameter real tHZ1 = 5.4; // tHZ1 ns Parameter definition for compilation - CL = 1 illegal for sg75
`elsif CLK_133
parameter real tHZ3 = 6.0; // tHZ3 ns Data Out High Z time - CL = 3
parameter real tHZ2 = 6.0; // tHZ2 ns Data Out High Z time - CL = 2
parameter real tHZ1 = 6.0; // tHZ1 ns Parameter definition for compilation - CL = 1 illegal for sg75
`endif
parameter tOH = 2.7; // tOH ns Data Out Hold time
parameter tRRD = 2.0; // tRRD tCK Active bank a to Active bank b command time (2 * tCK)
parameter tWRa = tCK; // tWR ns Write recovery time (auto-precharge mode - must add 1 CLK)
parameter tWRm = 2*tCK; // tWR ns Write recovery time
parameter ADDR_BITS = ROW_WIDTH; // Set this parameter to control how many Address bits are used
parameter ROW_BITS = ROW_WIDTH; // Set this parameter to control how many Row bits are used
parameter COL_BITS = COL_WIDTH; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = DQ_WIDTH; // Set this parameter to control how many Data bits are used
parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
parameter BA_BITS = BA_WIDTH; // Bank bits
parameter mem_sizes = 2**(ROW_BITS+COL_BITS) - 1;
input Clk;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [ADDR_BITS - 1 : 0] Addr;
input [BA_BITS - 1 : 0] Ba;
inout [DQ_BITS - 1 : 0] Dq;
input [DM_BITS - 1 : 0] Dqm;
endmodule