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Add tcp regs and switch to verilator

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This commit is contained in:
Byron Lathi
2024-08-17 11:56:01 -07:00
parent 52a76e3a85
commit 9b2a40df06
30 changed files with 1340 additions and 78 deletions
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1
hw/super6502_fpga/src/sub/cpu_wrapper/sources.list Normal file
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@@ -0,0 +1 @@
cpu_wrapper.sv

7
hw/super6502_fpga/src/sub/network_processor/sources.list Normal file
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@@ -0,0 +1,7 @@
src/regs/tcp_stream_regs_pkg.sv
src/regs/tcp_stream_regs.sv
src/regs/tcp_top_regfile_pkg.sv
src/regs/tcp_top_regfile.sv
src/network_processor.sv
src/tcp_state_manager.sv
src/tcp_stream.sv

98
hw/super6502_fpga/src/sub/network_processor/src/network_processor.sv
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@@ -0,0 +1,98 @@
module network_processor #(
parameter NUM_TCP=8
)(
input i_clk,
input i_rst,
// our crossbar is all axi, so having this be apb means
// we have to convert it anyway
output logic s_axil_awready,
input wire s_axil_awvalid,
input wire [8:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
output logic s_axil_wready,
input wire s_axil_wvalid,
input wire [31:0] s_axil_wdata,
input wire [3:0]s_axil_wstrb,
input wire s_axil_bready,
output logic s_axil_bvalid,
output logic [1:0] s_axil_bresp,
output logic s_axil_arready,
input wire s_axil_arvalid,
input wire [8:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_rready,
output logic s_axil_rvalid,
output logic [31:0] s_axil_rdata,
output logic [1:0] s_axil_rresp
);
tcp_top_regfile_pkg::tcp_top_regfile__in_t tcp_hwif_in;
tcp_top_regfile_pkg::tcp_top_regfile__out_t tcp_hwif_out;
tcp_top_regfile u_tcp_top_regfile (
.clk (i_clk),
.rst (i_rst),
.s_axil_awready (s_axil_awready),
.s_axil_awvalid (s_axil_awvalid),
.s_axil_awaddr (s_axil_awaddr),
.s_axil_awprot (s_axil_awprot),
.s_axil_wready (s_axil_wready),
.s_axil_wvalid (s_axil_wvalid),
.s_axil_wdata (s_axil_wdata),
.s_axil_wstrb (s_axil_wstrb),
.s_axil_bready (s_axil_bready),
.s_axil_bvalid (s_axil_bvalid),
.s_axil_bresp (s_axil_bresp),
.s_axil_arready (s_axil_arready),
.s_axil_arvalid (s_axil_arvalid),
.s_axil_araddr (s_axil_araddr),
.s_axil_arprot (s_axil_arprot),
.s_axil_rready (s_axil_rready),
.s_axil_rvalid (s_axil_rvalid),
.s_axil_rdata (s_axil_rdata),
.s_axil_rresp (s_axil_rresp),
.hwif_in (tcp_hwif_in),
.hwif_out (tcp_hwif_out)
);
generate
for (genvar i = 0; i < NUM_TCP; i++) begin
logic req;
logic req_is_wr;
logic [5:0] addr;
logic [31:0] wr_data;
logic [31:0] wr_biten;
assign req = tcp_hwif_out.tcp_streams[i].req;
assign req_is_wr = tcp_hwif_out.tcp_streams[i].req_is_wr;
assign addr = tcp_hwif_out.tcp_streams[i].addr;
assign wr_data = tcp_hwif_out.tcp_streams[i].wr_data;
assign wr_biten = tcp_hwif_out.tcp_streams[i].wr_biten;
tcp_stream u_tcp_stream (
.clk (i_clk),
.rst (i_rst),
// This is the hacky decoder alex was telling me about
.s_cpuif_req (req),
.s_cpuif_req_is_wr (req_is_wr),
.s_cpuif_addr (addr),
.s_cpuif_wr_data (wr_data),
.s_cpuif_wr_biten (wr_biten),
.s_cpuif_req_stall_wr (),
.s_cpuif_req_stall_rd (),
.s_cpuif_rd_ack (tcp_hwif_in.tcp_streams[i].rd_ack),
.s_cpuif_rd_err (),
.s_cpuif_rd_data (tcp_hwif_in.tcp_streams[i].rd_data),
.s_cpuif_wr_ack (tcp_hwif_in.tcp_streams[i].wr_ack),
.s_cpuif_wr_err ()
);
end
endgenerate
endmodule

10
hw/super6502_fpga/src/sub/network_processor/src/regs/run_precompile.sh Normal file
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@@ -0,0 +1,10 @@
peakrdl regblock tcp_stream.rdl tcp_top_regs.rdl -o . --cpuif axi4-lite-flat
peakrdl regblock -t tcp_stream_regs tcp_stream.rdl -o . --cpuif passthrough
# sed -i -e 's/struct/struct packed/g' tcp_stream_regs.sv
# sed -i -e 's/struct/struct packed/g' tcp_stream_regs_pkg.sv
# sed -i -e 's/automatic/static/g' tcp_stream_regs.sv
# sed -i -e 's/struct/struct packed/g' tcp_top_regfile.sv
# sed -i -e 's/struct/struct packed/g' tcp_top_regfile_pkg.sv
# sed -i -e 's/automatic/static/g' tcp_top_regfile.sv

10
hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream.rdl
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@@ -1,4 +1,4 @@
addrmap tcp_stream {
regfile tcp_stream {
name = "TCP Stream Regs";
desc = "";
@@ -75,7 +75,7 @@ addrmap tcp_stream {
desc = "Closes the exisitng connection when written with 1";
hw = r;
sw = rw;
hwclr
hwclr;
} close[2:2] = 0x0;
field {
@@ -89,7 +89,7 @@ addrmap tcp_stream {
// is addrmap right for this? How do we specify the address of it though?
// Maybe we have to do this separately and include it?
addrmap stats {
regfile stats {
name = "Statistics";
desc = "";
@@ -132,4 +132,8 @@ addrmap tcp_stream {
} rx_bad_crc @ 0x8;
};
};
addrmap tcp_stream_regs {
tcp_stream tcp_streams;
};

375
hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs.sv Normal file
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@@ -0,0 +1,375 @@
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
module tcp_stream_regs (
input wire clk,
input wire rst,
input wire s_cpuif_req,
input wire s_cpuif_req_is_wr,
input wire [4:0] s_cpuif_addr,
input wire [31:0] s_cpuif_wr_data,
input wire [31:0] s_cpuif_wr_biten,
output wire s_cpuif_req_stall_wr,
output wire s_cpuif_req_stall_rd,
output wire s_cpuif_rd_ack,
output wire s_cpuif_rd_err,
output wire [31:0] s_cpuif_rd_data,
output wire s_cpuif_wr_ack,
output wire s_cpuif_wr_err,
input tcp_stream_regs_pkg::tcp_stream_regs__in_t hwif_in,
output tcp_stream_regs_pkg::tcp_stream_regs__out_t hwif_out
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_req_is_wr;
logic [4:0] cpuif_addr;
logic [31:0] cpuif_wr_data;
logic [31:0] cpuif_wr_biten;
logic cpuif_req_stall_wr;
logic cpuif_req_stall_rd;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
logic cpuif_wr_ack;
logic cpuif_wr_err;
assign cpuif_req = s_cpuif_req;
assign cpuif_req_is_wr = s_cpuif_req_is_wr;
assign cpuif_addr = s_cpuif_addr;
assign cpuif_wr_data = s_cpuif_wr_data;
assign cpuif_wr_biten = s_cpuif_wr_biten;
assign s_cpuif_req_stall_wr = cpuif_req_stall_wr;
assign s_cpuif_req_stall_rd = cpuif_req_stall_rd;
assign s_cpuif_rd_ack = cpuif_rd_ack;
assign s_cpuif_rd_err = cpuif_rd_err;
assign s_cpuif_rd_data = cpuif_rd_data;
assign s_cpuif_wr_ack = cpuif_wr_ack;
assign s_cpuif_wr_err = cpuif_wr_err;
logic cpuif_req_masked;
// Read & write latencies are balanced. Stalls not required
assign cpuif_req_stall_rd = '0;
assign cpuif_req_stall_wr = '0;
assign cpuif_req_masked = cpuif_req
& !(!cpuif_req_is_wr & cpuif_req_stall_rd)
& !(cpuif_req_is_wr & cpuif_req_stall_wr);
//--------------------------------------------------------------------------
// Address Decode
//--------------------------------------------------------------------------
typedef struct {
struct {
logic source_port;
logic source_ip;
logic dest_port;
logic dest_ip;
logic control;
} tcp_streams;
} decoded_reg_strb_t;
decoded_reg_strb_t decoded_reg_strb;
logic decoded_req;
logic decoded_req_is_wr;
logic [31:0] decoded_wr_data;
logic [31:0] decoded_wr_biten;
always_comb begin
decoded_reg_strb.tcp_streams.source_port = cpuif_req_masked & (cpuif_addr == 5'h0);
decoded_reg_strb.tcp_streams.source_ip = cpuif_req_masked & (cpuif_addr == 5'h4);
decoded_reg_strb.tcp_streams.dest_port = cpuif_req_masked & (cpuif_addr == 5'h8);
decoded_reg_strb.tcp_streams.dest_ip = cpuif_req_masked & (cpuif_addr == 5'hc);
decoded_reg_strb.tcp_streams.control = cpuif_req_masked & (cpuif_addr == 5'h10);
end
// Pass down signals to next stage
assign decoded_req = cpuif_req_masked;
assign decoded_req_is_wr = cpuif_req_is_wr;
assign decoded_wr_data = cpuif_wr_data;
assign decoded_wr_biten = cpuif_wr_biten;
//--------------------------------------------------------------------------
// Field logic
//--------------------------------------------------------------------------
typedef struct {
struct {
struct {
struct {
logic [31:0] next;
logic load_next;
} d;
} source_port;
struct {
struct {
logic [31:0] next;
logic load_next;
} d;
} source_ip;
struct {
struct {
logic [31:0] next;
logic load_next;
} d;
} dest_port;
struct {
struct {
logic [31:0] next;
logic load_next;
} d;
} dest_ip;
struct {
struct {
logic next;
logic load_next;
} enable;
struct {
logic next;
logic load_next;
} open;
struct {
logic next;
logic load_next;
} close;
} control;
} tcp_streams;
} field_combo_t;
field_combo_t field_combo;
typedef struct {
struct {
struct {
struct {
logic [31:0] value;
} d;
} source_port;
struct {
struct {
logic [31:0] value;
} d;
} source_ip;
struct {
struct {
logic [31:0] value;
} d;
} dest_port;
struct {
struct {
logic [31:0] value;
} d;
} dest_ip;
struct {
struct {
logic value;
} enable;
struct {
logic value;
} open;
struct {
logic value;
} close;
} control;
} tcp_streams;
} field_storage_t;
field_storage_t field_storage;
// Field: tcp_stream_regs.tcp_streams.source_port.d
always_comb begin
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.tcp_streams.source_port.d.value;
load_next_c = '0;
if(decoded_reg_strb.tcp_streams.source_port && decoded_req_is_wr) begin // SW write
next_c = (field_storage.tcp_streams.source_port.d.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
end
field_combo.tcp_streams.source_port.d.next = next_c;
field_combo.tcp_streams.source_port.d.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.tcp_streams.source_port.d.value <= 32'h0;
end else if(field_combo.tcp_streams.source_port.d.load_next) begin
field_storage.tcp_streams.source_port.d.value <= field_combo.tcp_streams.source_port.d.next;
end
end
assign hwif_out.tcp_streams.source_port.d.value = field_storage.tcp_streams.source_port.d.value;
// Field: tcp_stream_regs.tcp_streams.source_ip.d
always_comb begin
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.tcp_streams.source_ip.d.value;
load_next_c = '0;
if(decoded_reg_strb.tcp_streams.source_ip && decoded_req_is_wr) begin // SW write
next_c = (field_storage.tcp_streams.source_ip.d.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
end
field_combo.tcp_streams.source_ip.d.next = next_c;
field_combo.tcp_streams.source_ip.d.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.tcp_streams.source_ip.d.value <= 32'h0;
end else if(field_combo.tcp_streams.source_ip.d.load_next) begin
field_storage.tcp_streams.source_ip.d.value <= field_combo.tcp_streams.source_ip.d.next;
end
end
assign hwif_out.tcp_streams.source_ip.d.value = field_storage.tcp_streams.source_ip.d.value;
// Field: tcp_stream_regs.tcp_streams.dest_port.d
always_comb begin
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.tcp_streams.dest_port.d.value;
load_next_c = '0;
if(decoded_reg_strb.tcp_streams.dest_port && decoded_req_is_wr) begin // SW write
next_c = (field_storage.tcp_streams.dest_port.d.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
end
field_combo.tcp_streams.dest_port.d.next = next_c;
field_combo.tcp_streams.dest_port.d.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.tcp_streams.dest_port.d.value <= 32'h0;
end else if(field_combo.tcp_streams.dest_port.d.load_next) begin
field_storage.tcp_streams.dest_port.d.value <= field_combo.tcp_streams.dest_port.d.next;
end
end
assign hwif_out.tcp_streams.dest_port.d.value = field_storage.tcp_streams.dest_port.d.value;
// Field: tcp_stream_regs.tcp_streams.dest_ip.d
always_comb begin
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.tcp_streams.dest_ip.d.value;
load_next_c = '0;
if(decoded_reg_strb.tcp_streams.dest_ip && decoded_req_is_wr) begin // SW write
next_c = (field_storage.tcp_streams.dest_ip.d.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
end
field_combo.tcp_streams.dest_ip.d.next = next_c;
field_combo.tcp_streams.dest_ip.d.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.tcp_streams.dest_ip.d.value <= 32'h0;
end else if(field_combo.tcp_streams.dest_ip.d.load_next) begin
field_storage.tcp_streams.dest_ip.d.value <= field_combo.tcp_streams.dest_ip.d.next;
end
end
assign hwif_out.tcp_streams.dest_ip.d.value = field_storage.tcp_streams.dest_ip.d.value;
// Field: tcp_stream_regs.tcp_streams.control.enable
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.tcp_streams.control.enable.value;
load_next_c = '0;
if(decoded_reg_strb.tcp_streams.control && decoded_req_is_wr) begin // SW write
next_c = (field_storage.tcp_streams.control.enable.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
load_next_c = '1;
end
field_combo.tcp_streams.control.enable.next = next_c;
field_combo.tcp_streams.control.enable.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.tcp_streams.control.enable.value <= 1'h0;
end else if(field_combo.tcp_streams.control.enable.load_next) begin
field_storage.tcp_streams.control.enable.value <= field_combo.tcp_streams.control.enable.next;
end
end
assign hwif_out.tcp_streams.control.enable.value = field_storage.tcp_streams.control.enable.value;
// Field: tcp_stream_regs.tcp_streams.control.open
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.tcp_streams.control.open.value;
load_next_c = '0;
if(decoded_reg_strb.tcp_streams.control && decoded_req_is_wr) begin // SW write
next_c = (field_storage.tcp_streams.control.open.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
load_next_c = '1;
end else if(hwif_in.tcp_streams.control.open.hwclr) begin // HW Clear
next_c = '0;
load_next_c = '1;
end
field_combo.tcp_streams.control.open.next = next_c;
field_combo.tcp_streams.control.open.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.tcp_streams.control.open.value <= 1'h0;
end else if(field_combo.tcp_streams.control.open.load_next) begin
field_storage.tcp_streams.control.open.value <= field_combo.tcp_streams.control.open.next;
end
end
assign hwif_out.tcp_streams.control.open.value = field_storage.tcp_streams.control.open.value;
// Field: tcp_stream_regs.tcp_streams.control.close
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.tcp_streams.control.close.value;
load_next_c = '0;
if(decoded_reg_strb.tcp_streams.control && decoded_req_is_wr) begin // SW write
next_c = (field_storage.tcp_streams.control.close.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]);
load_next_c = '1;
end else if(hwif_in.tcp_streams.control.close.hwclr) begin // HW Clear
next_c = '0;
load_next_c = '1;
end
field_combo.tcp_streams.control.close.next = next_c;
field_combo.tcp_streams.control.close.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.tcp_streams.control.close.value <= 1'h0;
end else if(field_combo.tcp_streams.control.close.load_next) begin
field_storage.tcp_streams.control.close.value <= field_combo.tcp_streams.control.close.next;
end
end
assign hwif_out.tcp_streams.control.close.value = field_storage.tcp_streams.control.close.value;
//--------------------------------------------------------------------------
// Write response
//--------------------------------------------------------------------------
assign cpuif_wr_ack = decoded_req & decoded_req_is_wr;
// Writes are always granted with no error response
assign cpuif_wr_err = '0;
//--------------------------------------------------------------------------
// Readback
//--------------------------------------------------------------------------
logic readback_err;
logic readback_done;
logic [31:0] readback_data;
// Assign readback values to a flattened array
logic [31:0] readback_array[5];
assign readback_array[0][31:0] = (decoded_reg_strb.tcp_streams.source_port && !decoded_req_is_wr) ? field_storage.tcp_streams.source_port.d.value : '0;
assign readback_array[1][31:0] = (decoded_reg_strb.tcp_streams.source_ip && !decoded_req_is_wr) ? field_storage.tcp_streams.source_ip.d.value : '0;
assign readback_array[2][31:0] = (decoded_reg_strb.tcp_streams.dest_port && !decoded_req_is_wr) ? field_storage.tcp_streams.dest_port.d.value : '0;
assign readback_array[3][31:0] = (decoded_reg_strb.tcp_streams.dest_ip && !decoded_req_is_wr) ? field_storage.tcp_streams.dest_ip.d.value : '0;
assign readback_array[4][0:0] = (decoded_reg_strb.tcp_streams.control && !decoded_req_is_wr) ? field_storage.tcp_streams.control.enable.value : '0;
assign readback_array[4][1:1] = (decoded_reg_strb.tcp_streams.control && !decoded_req_is_wr) ? field_storage.tcp_streams.control.open.value : '0;
assign readback_array[4][2:2] = (decoded_reg_strb.tcp_streams.control && !decoded_req_is_wr) ? field_storage.tcp_streams.control.close.value : '0;
assign readback_array[4][5:3] = (decoded_reg_strb.tcp_streams.control && !decoded_req_is_wr) ? hwif_in.tcp_streams.control.state.next : '0;
assign readback_array[4][31:6] = '0;
// Reduce the array
always_comb begin
automatic logic [31:0] readback_data_var;
readback_done = decoded_req & ~decoded_req_is_wr;
readback_err = '0;
readback_data_var = '0;
for(int i=0; i<5; i++) readback_data_var |= readback_array[i];
readback_data = readback_data_var;
end
assign cpuif_rd_ack = readback_done;
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;
endmodule

96
hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs_pkg.sv Normal file
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@@ -0,0 +1,96 @@
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
package tcp_stream_regs_pkg;
localparam TCP_STREAM_REGS_DATA_WIDTH = 32;
localparam TCP_STREAM_REGS_MIN_ADDR_WIDTH = 5;
typedef struct {
logic hwclr;
} tcp_stream__control__open__in_t;
typedef struct {
logic hwclr;
} tcp_stream__control__close__in_t;
typedef struct {
logic [2:0] next;
} tcp_stream__control__state__in_t;
typedef struct {
tcp_stream__control__open__in_t open;
tcp_stream__control__close__in_t close;
tcp_stream__control__state__in_t state;
} tcp_stream__control__in_t;
typedef struct {
tcp_stream__control__in_t control;
} tcp_stream__in_t;
typedef struct {
tcp_stream__in_t tcp_streams;
} tcp_stream_regs__in_t;
typedef struct {
logic [31:0] value;
} tcp_stream__source_port__d__out_t;
typedef struct {
tcp_stream__source_port__d__out_t d;
} tcp_stream__source_port__out_t;
typedef struct {
logic [31:0] value;
} tcp_stream__source_ip__d__out_t;
typedef struct {
tcp_stream__source_ip__d__out_t d;
} tcp_stream__source_ip__out_t;
typedef struct {
logic [31:0] value;
} tcp_stream__dest_port__d__out_t;
typedef struct {
tcp_stream__dest_port__d__out_t d;
} tcp_stream__dest_port__out_t;
typedef struct {
logic [31:0] value;
} tcp_stream__dest_ip__d__out_t;
typedef struct {
tcp_stream__dest_ip__d__out_t d;
} tcp_stream__dest_ip__out_t;
typedef struct {
logic value;
} tcp_stream__control__enable__out_t;
typedef struct {
logic value;
} tcp_stream__control__open__out_t;
typedef struct {
logic value;
} tcp_stream__control__close__out_t;
typedef struct {
tcp_stream__control__enable__out_t enable;
tcp_stream__control__open__out_t open;
tcp_stream__control__close__out_t close;
} tcp_stream__control__out_t;
typedef struct {
tcp_stream__source_port__out_t source_port;
tcp_stream__source_ip__out_t source_ip;
tcp_stream__dest_port__out_t dest_port;
tcp_stream__dest_ip__out_t dest_ip;
tcp_stream__control__out_t control;
} tcp_stream__out_t;
typedef struct {
tcp_stream__out_t tcp_streams;
} tcp_stream_regs__out_t;
endpackage

349
hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regfile.sv Normal file
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@@ -0,0 +1,349 @@
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
module tcp_top_regfile (
input wire clk,
input wire rst,
output logic s_axil_awready,
input wire s_axil_awvalid,
input wire [8:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
output logic s_axil_wready,
input wire s_axil_wvalid,
input wire [31:0] s_axil_wdata,
input wire [3:0]s_axil_wstrb,
input wire s_axil_bready,
output logic s_axil_bvalid,
output logic [1:0] s_axil_bresp,
output logic s_axil_arready,
input wire s_axil_arvalid,
input wire [8:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_rready,
output logic s_axil_rvalid,
output logic [31:0] s_axil_rdata,
output logic [1:0] s_axil_rresp,
input tcp_top_regfile_pkg::tcp_top_regfile__in_t hwif_in,
output tcp_top_regfile_pkg::tcp_top_regfile__out_t hwif_out
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_req_is_wr;
logic [8:0] cpuif_addr;
logic [31:0] cpuif_wr_data;
logic [31:0] cpuif_wr_biten;
logic cpuif_req_stall_wr;
logic cpuif_req_stall_rd;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
logic cpuif_wr_ack;
logic cpuif_wr_err;
// Max Outstanding Transactions: 2
logic [1:0] axil_n_in_flight;
logic axil_prev_was_rd;
logic axil_arvalid;
logic [8:0] axil_araddr;
logic axil_ar_accept;
logic axil_awvalid;
logic [8:0] axil_awaddr;
logic axil_wvalid;
logic [31:0] axil_wdata;
logic [3:0] axil_wstrb;
logic axil_aw_accept;
logic axil_resp_acked;
// Transaction request acceptance
always_ff @(posedge clk) begin
if(rst) begin
axil_prev_was_rd <= '0;
axil_arvalid <= '0;
axil_araddr <= '0;
axil_awvalid <= '0;
axil_awaddr <= '0;
axil_wvalid <= '0;
axil_wdata <= '0;
axil_wstrb <= '0;
axil_n_in_flight <= '0;
end else begin
// AR* acceptance register
if(axil_ar_accept) begin
axil_prev_was_rd <= '1;
axil_arvalid <= '0;
end
if(s_axil_arvalid && s_axil_arready) begin
axil_arvalid <= '1;
axil_araddr <= s_axil_araddr;
end
// AW* & W* acceptance registers
if(axil_aw_accept) begin
axil_prev_was_rd <= '0;
axil_awvalid <= '0;
axil_wvalid <= '0;
end
if(s_axil_awvalid && s_axil_awready) begin
axil_awvalid <= '1;
axil_awaddr <= s_axil_awaddr;
end
if(s_axil_wvalid && s_axil_wready) begin
axil_wvalid <= '1;
axil_wdata <= s_axil_wdata;
axil_wstrb <= s_axil_wstrb;
end
// Keep track of in-flight transactions
if((axil_ar_accept || axil_aw_accept) && !axil_resp_acked) begin
axil_n_in_flight <= axil_n_in_flight + 1'b1;
end else if(!(axil_ar_accept || axil_aw_accept) && axil_resp_acked) begin
axil_n_in_flight <= axil_n_in_flight - 1'b1;
end
end
end
always_comb begin
s_axil_arready = (!axil_arvalid || axil_ar_accept);
s_axil_awready = (!axil_awvalid || axil_aw_accept);
s_axil_wready = (!axil_wvalid || axil_aw_accept);
end
// Request dispatch
always_comb begin
cpuif_wr_data = axil_wdata;
for(int i=0; i<4; i++) begin
cpuif_wr_biten[i*8 +: 8] = {8{axil_wstrb[i]}};
end
cpuif_req = '0;
cpuif_req_is_wr = '0;
cpuif_addr = '0;
axil_ar_accept = '0;
axil_aw_accept = '0;
if(axil_n_in_flight < 2'd2) begin
// Can safely issue more transactions without overwhelming response buffer
if(axil_arvalid && !axil_prev_was_rd) begin
cpuif_req = '1;
cpuif_req_is_wr = '0;
cpuif_addr = {axil_araddr[8:2], 2'b0};
if(!cpuif_req_stall_rd) axil_ar_accept = '1;
end else if(axil_awvalid && axil_wvalid) begin
cpuif_req = '1;
cpuif_req_is_wr = '1;
cpuif_addr = {axil_awaddr[8:2], 2'b0};
if(!cpuif_req_stall_wr) axil_aw_accept = '1;
end else if(axil_arvalid) begin
cpuif_req = '1;
cpuif_req_is_wr = '0;
cpuif_addr = {axil_araddr[8:2], 2'b0};
if(!cpuif_req_stall_rd) axil_ar_accept = '1;
end
end
end
// AXI4-Lite Response Logic
struct {
logic is_wr;
logic err;
logic [31:0] rdata;
} axil_resp_buffer[2];
logic [1:0] axil_resp_wptr;
logic [1:0] axil_resp_rptr;
always_ff @(posedge clk) begin
if(rst) begin
for(int i=0; i<2; i++) begin
axil_resp_buffer[i].is_wr <= '0;
axil_resp_buffer[i].err <= '0;
axil_resp_buffer[i].rdata <= '0;
end
axil_resp_wptr <= '0;
axil_resp_rptr <= '0;
end else begin
// Store responses in buffer until AXI response channel accepts them
if(cpuif_rd_ack || cpuif_wr_ack) begin
if(cpuif_rd_ack) begin
axil_resp_buffer[axil_resp_wptr[0:0]].is_wr <= '0;
axil_resp_buffer[axil_resp_wptr[0:0]].err <= cpuif_rd_err;
axil_resp_buffer[axil_resp_wptr[0:0]].rdata <= cpuif_rd_data;
end else if(cpuif_wr_ack) begin
axil_resp_buffer[axil_resp_wptr[0:0]].is_wr <= '1;
axil_resp_buffer[axil_resp_wptr[0:0]].err <= cpuif_wr_err;
end
axil_resp_wptr <= axil_resp_wptr + 1'b1;
end
// Advance read pointer when acknowledged
if(axil_resp_acked) begin
axil_resp_rptr <= axil_resp_rptr + 1'b1;
end
end
end
always_comb begin
axil_resp_acked = '0;
s_axil_bvalid = '0;
s_axil_rvalid = '0;
if(axil_resp_rptr != axil_resp_wptr) begin
if(axil_resp_buffer[axil_resp_rptr[0:0]].is_wr) begin
s_axil_bvalid = '1;
if(s_axil_bready) axil_resp_acked = '1;
end else begin
s_axil_rvalid = '1;
if(s_axil_rready) axil_resp_acked = '1;
end
end
s_axil_rdata = axil_resp_buffer[axil_resp_rptr[0:0]].rdata;
if(axil_resp_buffer[axil_resp_rptr[0:0]].err) begin
s_axil_bresp = 2'b10;
s_axil_rresp = 2'b10;
end else begin
s_axil_bresp = 2'b00;
s_axil_rresp = 2'b00;
end
end
logic cpuif_req_masked;
logic external_req;
logic external_pending;
logic external_wr_ack;
logic external_rd_ack;
always_ff @(posedge clk) begin
if(rst) begin
external_pending <= '0;
end else begin
if(external_req & ~external_wr_ack & ~external_rd_ack) external_pending <= '1;
else if(external_wr_ack | external_rd_ack) external_pending <= '0;
assert(!external_wr_ack || (external_pending | external_req))
else $error("An external wr_ack strobe was asserted when no external request was active");
assert(!external_rd_ack || (external_pending | external_req))
else $error("An external rd_ack strobe was asserted when no external request was active");
end
end
// Read & write latencies are balanced. Stalls not required
// except if external
assign cpuif_req_stall_rd = external_pending;
assign cpuif_req_stall_wr = external_pending;
assign cpuif_req_masked = cpuif_req
& !(!cpuif_req_is_wr & cpuif_req_stall_rd)
& !(cpuif_req_is_wr & cpuif_req_stall_wr);
//--------------------------------------------------------------------------
// Address Decode
//--------------------------------------------------------------------------
typedef struct {
logic tcp_streams[8];
} decoded_reg_strb_t;
decoded_reg_strb_t decoded_reg_strb;
logic decoded_strb_is_external;
logic [8:0] decoded_addr;
logic decoded_req;
logic decoded_req_is_wr;
logic [31:0] decoded_wr_data;
logic [31:0] decoded_wr_biten;
always_comb begin
automatic logic is_external;
is_external = '0;
for(int i0=0; i0<8; i0++) begin
decoded_reg_strb.tcp_streams[i0] = cpuif_req_masked & (cpuif_addr >= 9'h0 + i0*9'h40) & (cpuif_addr <= 9'h0 + i0*9'h40 + 9'h13);
is_external |= cpuif_req_masked & (cpuif_addr >= 9'h0 + i0*9'h40) & (cpuif_addr <= 9'h0 + i0*9'h40 + 9'h13);
end
decoded_strb_is_external = is_external;
external_req = is_external;
end
// Pass down signals to next stage
assign decoded_addr = cpuif_addr;
assign decoded_req = cpuif_req_masked;
assign decoded_req_is_wr = cpuif_req_is_wr;
assign decoded_wr_data = cpuif_wr_data;
assign decoded_wr_biten = cpuif_wr_biten;
//--------------------------------------------------------------------------
// Field logic
//--------------------------------------------------------------------------
for(genvar i0=0; i0<8; i0++) begin
assign hwif_out.tcp_streams[i0].req = decoded_reg_strb.tcp_streams[i0];
assign hwif_out.tcp_streams[i0].addr = decoded_addr[4:0];
assign hwif_out.tcp_streams[i0].req_is_wr = decoded_req_is_wr;
assign hwif_out.tcp_streams[i0].wr_data = decoded_wr_data;
assign hwif_out.tcp_streams[i0].wr_biten = decoded_wr_biten;
end
//--------------------------------------------------------------------------
// Write response
//--------------------------------------------------------------------------
always_comb begin
automatic logic wr_ack;
wr_ack = '0;
for(int i0=0; i0<8; i0++) begin
wr_ack |= hwif_in.tcp_streams[i0].wr_ack;
end
external_wr_ack = wr_ack;
end
assign cpuif_wr_ack = external_wr_ack | (decoded_req & decoded_req_is_wr & ~decoded_strb_is_external);
// Writes are always granted with no error response
assign cpuif_wr_err = '0;
//--------------------------------------------------------------------------
// Readback
//--------------------------------------------------------------------------
logic readback_external_rd_ack_c;
always_comb begin
automatic logic rd_ack;
rd_ack = '0;
for(int i0=0; i0<8; i0++) begin
rd_ack |= hwif_in.tcp_streams[i0].rd_ack;
end
readback_external_rd_ack_c = rd_ack;
end
logic readback_external_rd_ack;
assign readback_external_rd_ack = readback_external_rd_ack_c;
logic readback_err;
logic readback_done;
logic [31:0] readback_data;
// Assign readback values to a flattened array
logic [31:0] readback_array[8];
for(genvar i0=0; i0<8; i0++) begin
assign readback_array[i0*1 + 0] = hwif_in.tcp_streams[i0].rd_ack ? hwif_in.tcp_streams[i0].rd_data : '0;
end
// Reduce the array
always_comb begin
automatic logic [31:0] readback_data_var;
readback_done = decoded_req & ~decoded_req_is_wr & ~decoded_strb_is_external;
readback_err = '0;
readback_data_var = '0;
for(int i=0; i<8; i++) readback_data_var |= readback_array[i];
readback_data = readback_data_var;
end
assign external_rd_ack = readback_external_rd_ack;
assign cpuif_rd_ack = readback_done | readback_external_rd_ack;
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;
endmodule

30
hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regfile_pkg.sv Normal file
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@@ -0,0 +1,30 @@
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
package tcp_top_regfile_pkg;
localparam TCP_TOP_REGFILE_DATA_WIDTH = 32;
localparam TCP_TOP_REGFILE_MIN_ADDR_WIDTH = 9;
typedef struct {
logic rd_ack;
logic [31:0] rd_data;
logic wr_ack;
} tcp_stream__external__in_t;
typedef struct {
tcp_stream__external__in_t tcp_streams[8];
} tcp_top_regfile__in_t;
typedef struct {
logic req;
logic [4:0] addr;
logic req_is_wr;
logic [31:0] wr_data;
logic [31:0] wr_biten;
} tcp_stream__external__out_t;
typedef struct {
tcp_stream__external__out_t tcp_streams[8];
} tcp_top_regfile__out_t;
endpackage

3
hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regs.rdl Normal file
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@@ -0,0 +1,3 @@
addrmap tcp_top_regfile{
external tcp_stream tcp_streams[8] += 0x40;
};

39
hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv
View File

@@ -1,8 +1,47 @@
module tcp_stream(
input wire clk,
input wire rst,
input wire s_cpuif_req,
input wire s_cpuif_req_is_wr,
input wire [4:0] s_cpuif_addr,
input wire [31:0] s_cpuif_wr_data,
input wire [31:0] s_cpuif_wr_biten,
output wire s_cpuif_req_stall_wr,
output wire s_cpuif_req_stall_rd,
output wire s_cpuif_rd_ack,
output wire s_cpuif_rd_err,
output wire [31:0] s_cpuif_rd_data,
output wire s_cpuif_wr_ack,
output wire s_cpuif_wr_err
);
// regs
tcp_stream_regs_pkg::tcp_stream_regs__in_t hwif_in;
tcp_stream_regs_pkg::tcp_stream_regs__out_t hwif_out;
tcp_stream_regs u_tcp_stream_regs (
.clk (clk),
.rst (rst),
.s_cpuif_req (s_cpuif_req),
.s_cpuif_req_is_wr (s_cpuif_req_is_wr),
.s_cpuif_addr (s_cpuif_addr),
.s_cpuif_wr_data (s_cpuif_wr_data),
.s_cpuif_wr_biten (s_cpuif_wr_biten),
.s_cpuif_req_stall_wr (s_cpuif_req_stall_wr),
.s_cpuif_req_stall_rd (s_cpuif_req_stall_rd),
.s_cpuif_rd_ack (s_cpuif_rd_ack),
.s_cpuif_rd_err (s_cpuif_rd_err),
.s_cpuif_rd_data (s_cpuif_rd_data),
.s_cpuif_wr_ack (s_cpuif_wr_ack),
.s_cpuif_wr_err (s_cpuif_wr_err),
.hwif_in (hwif_in),
.hwif_out (hwif_out)
);
// tcp state manager

2
hw/super6502_fpga/src/sub/rtl-common

Submodule hw/super6502_fpga/src/sub/rtl-common updated: 6bb56be03a...1f071c11d9

2
hw/super6502_fpga/src/sub/sd_controller_wrapper/sdspi

Submodule hw/super6502_fpga/src/sub/sd_controller_wrapper/sdspi updated: 4738e699ca...eb8e8ba552

22
hw/super6502_fpga/src/sub/sd_controller_wrapper/sources.list Normal file
View File

@@ -0,0 +1,22 @@
sd_controller_wrapper.sv
shadow_regs.sv
sdspi/rtl/sdckgen.v
sdspi/rtl/sddma_rxgears.v
sdspi/rtl/sddma.v
sdspi/rtl/sdrxframe.v
sdspi/rtl/sdtxframe.v
sdspi/rtl/sddma_s2mm.v
sdspi/rtl/sddma_s2mm_axi.v
# sdspi/rtl/afifo.v
sdspi/rtl/sddma_txgears.v
sdspi/rtl/sdskid.v
sdspi/rtl/sdfrontend.v
sdspi/rtl/spicmd.v
sdspi/rtl/sdaxil.v
sdspi/rtl/sddma_mm2s.v
sdspi/rtl/sddma_mm2s_axi.v
sdspi/rtl/sdio_top.v
sdspi/rtl/sdwb.v
sdspi/rtl/sdio.v
sdspi/rtl/sdcmd.v
sdspi/rtl/sdfifo.v

2
hw/super6502_fpga/src/sub/wb2axip

Submodule hw/super6502_fpga/src/sub/wb2axip updated: bf09db69cb...29e1e3755f