Disable sdr debug, initialize uart status

hw/efinix_fpga/simulation/src/generic_sdr.v

@@ -164,7 +164,7 @@ parameter mem_sizes        = 2**(ROW_BITS+COL_BITS) - 1;
     // Write Burst Mode
     wire      Write_burst_mode = Mode_reg[9];
 
-    wire      Debug            = 1'b1;                          // Debug messages : 1 = On
+    wire      Debug            = 1'b0;                          // Debug messages : 1 = On
     wire      Dq_chk           = Sys_clk & Data_in_enable;      // Check setup/hold time for DQ
     
     assign    Dq               = Dq_reg;                        // DQ buffer

hw/efinix_fpga/simulation/src/sim_top.sv

@@ -49,7 +49,7 @@ initial begin
 	button_reset <= '0;
 	repeat(10) @(r_clk_2);
 	button_reset <= '1;
-	repeat(8000) @(r_clk_2);
+	repeat(20000) @(r_clk_2);
 	$finish();
 end
 

hw/efinix_fpga/src/uart_wrapper.sv

@@ -46,8 +46,9 @@ enum bit [1:0] {READY, WAIT, TRANSMIT} state, next_state;
 
 always_ff @(posedge clk_50) begin
     if (reset) begin
-        state = READY;
+        state <= READY;
         irqb <= '1;
+        status <= '0;
     end else begin
         state <= next_state;
     end