Disable sdr debug, initialize uart status

2023-09-27 21:14:09 -07:00
parent ec4c3bab86
commit 9e19a1eb72
3 changed files with 4 additions and 3 deletions
--- a/hw/efinix_fpga/simulation/src/generic_sdr.v
+++ b/hw/efinix_fpga/simulation/src/generic_sdr.v
@@ -164,7 +164,7 @@ parameter mem_sizes        = 2**(ROW_BITS+COL_BITS) - 1;
    // Write Burst Mode
    wire      Write_burst_mode = Mode_reg[9];

-    wire      Debug            = 1'b1;                          // Debug messages : 1 = On
+    wire      Debug            = 1'b0;                          // Debug messages : 1 = On
    wire      Dq_chk           = Sys_clk & Data_in_enable;      // Check setup/hold time for DQ
    
    assign    Dq               = Dq_reg;                        // DQ buffer