Disable sdr debug, initialize uart status

2023-09-27 21:14:09 -07:00
parent ec4c3bab86
commit 9e19a1eb72
3 changed files with 4 additions and 3 deletions
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -49,7 +49,7 @@ initial begin
 	button_reset <= '0;
 	repeat(10) @(r_clk_2);
 	button_reset <= '1;
-	repeat(8000) @(r_clk_2);
+	repeat(20000) @(r_clk_2);
 	$finish();
 end