Disable sdr debug, initialize uart status

2023-09-27 21:14:09 -07:00
parent ec4c3bab86
commit 9e19a1eb72
3 changed files with 4 additions and 3 deletions
--- a/hw/efinix_fpga/src/uart_wrapper.sv
+++ b/hw/efinix_fpga/src/uart_wrapper.sv
@@ -46,8 +46,9 @@ enum bit [1:0] {READY, WAIT, TRANSMIT} state, next_state;

 always_ff @(posedge clk_50) begin
    if (reset) begin
-        state = READY;
+        state <= READY;
        irqb <= '1;
+        status <= '0;
    end else begin
        state <= next_state;
    end