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Disable sdr debug, initialize uart status

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This commit is contained in:
Byron Lathi
2023-09-27 21:14:09 -07:00
parent ec4c3bab86
commit 9e19a1eb72
3 changed files with 4 additions and 3 deletions
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2
hw/efinix_fpga/simulation/src/generic_sdr.v
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@@ -164,7 +164,7 @@ parameter mem_sizes = 2**(ROW_BITS+COL_BITS) - 1;
// Write Burst Mode // Write Burst Mode
wire Write_burst_mode = Mode_reg[9]; wire Write_burst_mode = Mode_reg[9];
wire Debug = 1'b1; // Debug messages : 1 = On wire Debug = 1'b0; // Debug messages : 1 = On
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
assign Dq = Dq_reg; // DQ buffer assign Dq = Dq_reg; // DQ buffer

2
hw/efinix_fpga/simulation/src/sim_top.sv
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@@ -49,7 +49,7 @@ initial begin
button_reset <= '0; button_reset <= '0;
repeat(10) @(r_clk_2); repeat(10) @(r_clk_2);
button_reset <= '1; button_reset <= '1;
repeat(8000) @(r_clk_2); repeat(20000) @(r_clk_2);
$finish(); $finish();
end end

3
hw/efinix_fpga/src/uart_wrapper.sv
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@@ -46,8 +46,9 @@ enum bit [1:0] {READY, WAIT, TRANSMIT} state, next_state;
always_ff @(posedge clk_50) begin always_ff @(posedge clk_50) begin
if (reset) begin if (reset) begin
state = READY; state <= READY;
irqb <= '1; irqb <= '1;
status <= '0;
end else begin end else begin
state <= next_state; state <= next_state;
end end