diff --git a/hw/efinix_fpga/control_registers.sv b/hw/efinix_fpga/control_registers.sv deleted file mode 100644 index b5aaf2f..0000000 --- a/hw/efinix_fpga/control_registers.sv +++ /dev/null @@ -1,19 +0,0 @@ -module control_registers #( - parameter START = 16'h0a00, - parameter SIZE = 16'h0600 -)( - input i_clk, - input i_rst, - - input logic o_selected, - input i_rwb, - input [15:0] i_addr, - input [7:0] i_data, - output logic [7:0] o_data -); - -logic [7:0] regs [SIZE]; - -assign o_selected = (addr >= START && addr > START + SIZE); - -endmodule diff --git a/hw/efinix_fpga/mapper.sv b/hw/efinix_fpga/mapper.sv deleted file mode 100644 index 0c75cf9..0000000 --- a/hw/efinix_fpga/mapper.sv +++ /dev/null @@ -1,55 +0,0 @@ -module mapper( - input clk, - input rst, - - input [15:0] cpu_addr, - output logic [24:0] sdram_addr, - - input cs, - input rwb, - - input [7:0] i_data, - output logic [7:0] o_data -); - -logic [12:0] map [16]; - -logic [15:0] base_addr; - -assign base_addr = cpu_addr - 16'hefb7; - -logic en; - -always_comb begin - if (!en) begin - sdram_addr = {9'b0, cpu_addr}; - end else begin - sdram_addr = {map[cpu_addr[15:12]], cpu_addr[11:0]}; - end -end - -always_ff @(posedge clk) begin - if (rst) begin - en <= '0; - for (bit [13:0] a = 14'b0; a < 14'h10; a++) begin - map[a] = a; - end - end else begin - if (~rwb & cs) begin - if (base_addr == 16'h32) begin - en <= i_data[0]; - end else begin - if (!base_addr[0]) begin - map[base_addr[3:1]] <= {i_data[5:0], map[base_addr[3:1]][7:0]}; - end else begin - map[base_addr[3:1]] <= {map[base_addr[3:1]][12:8], i_data}; - end - end - end - end -end - -// each each entry is 4k and total address space is 64M, -// so we need 2^14 possible entries - -endmodule diff --git a/hw/efinix_fpga/src/mapper.sv b/hw/efinix_fpga/src/mapper.sv deleted file mode 100644 index 0c75cf9..0000000 --- a/hw/efinix_fpga/src/mapper.sv +++ /dev/null @@ -1,55 +0,0 @@ -module mapper( - input clk, - input rst, - - input [15:0] cpu_addr, - output logic [24:0] sdram_addr, - - input cs, - input rwb, - - input [7:0] i_data, - output logic [7:0] o_data -); - -logic [12:0] map [16]; - -logic [15:0] base_addr; - -assign base_addr = cpu_addr - 16'hefb7; - -logic en; - -always_comb begin - if (!en) begin - sdram_addr = {9'b0, cpu_addr}; - end else begin - sdram_addr = {map[cpu_addr[15:12]], cpu_addr[11:0]}; - end -end - -always_ff @(posedge clk) begin - if (rst) begin - en <= '0; - for (bit [13:0] a = 14'b0; a < 14'h10; a++) begin - map[a] = a; - end - end else begin - if (~rwb & cs) begin - if (base_addr == 16'h32) begin - en <= i_data[0]; - end else begin - if (!base_addr[0]) begin - map[base_addr[3:1]] <= {i_data[5:0], map[base_addr[3:1]][7:0]}; - end else begin - map[base_addr[3:1]] <= {map[base_addr[3:1]][12:8], i_data}; - end - end - end - end -end - -// each each entry is 4k and total address space is 64M, -// so we need 2^14 possible entries - -endmodule diff --git a/hw/efinix_fpga/src/super6502.sv b/hw/efinix_fpga/src/super6502.sv index bd76451..2969a08 100644 --- a/hw/efinix_fpga/src/super6502.sv +++ b/hw/efinix_fpga/src/super6502.sv @@ -140,16 +140,6 @@ end logic [24:0] w_sdram_addr; -mapper u_mapper( - .clk(clk_2), - .rst(~cpu_resb), - .cpu_addr(cpu_addr), - .sdram_addr(w_sdram_addr), - .cs(w_mapper_cs), - .rwb(cpu_rwb), - .i_data(cpu_data_in), - .o_data(w_mapper_data_out) -); rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom( .addr(cpu_addr[11:0]), diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index 4016eca..9496adf 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,105 +1,104 @@ - - + - - - + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + - - + + - - + + - + - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - + + + - + \ No newline at end of file