First throw at UART.

hw/efinix_fpga/addr_decode.sv

@@ -14,8 +14,8 @@ module addr_decode
 assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff;
 assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffb;
 assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7;
-assign o_divider_cs = i_addr >= 16'hefe7 && i_addr <= 16'hefef;
-assign o_uart_cs = i_addr >= 16'hefe5 && i_addr <= 16'hefe6;
+assign o_divider_cs = i_addr >= 16'hefe8 && i_addr <= 16'hefef;
+assign o_uart_cs = i_addr >= 16'hefe6 && i_addr <= 16'hefe7;
 assign o_leds_cs = i_addr == 16'hefff;
 assign o_sdram_cs = i_addr < 16'h8000;
 

hw/efinix_fpga/ip/bram/bram_ini.vh

@@ -4,9 +4,9 @@ input integer index;//Mode type
 input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved 
 case (index)
    0: bram_ini_table=
-(val_== 0)?256'h008d0000d000a9000ef000e90008d00001000a9000ef000e80008d000c8000a9:
-(val_== 1)?256'h0ef000ff0008d000ef000ec000ad000ef000eb0008d00000000a9000ef000ea0:
-(val_== 2)?256'h00000000000000000000000000000000000000000000000000e300080000cb00:
+(val_== 0)?256'h006500048000fd00080000cb000ef000e60008d000ff0000b000bd00000000a2:
+(val_== 1)?256'h0000000000021000640006c000720006f00077000200002c0006f0006c0006c0:
+(val_== 2)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_== 5)?256'h0000000000000000000000000000000000000000000000000000000000000000:

hw/efinix_fpga/ip/bram/init_hex.mem

@@ -1,32 +1,32 @@
-a9
-c8
-8d
-e8
-ef
-a9
-01
-8d
-e9
-ef
-a9
-0d
-8d
-ea
-ef
-a9
+a2
 00
-8d
-eb
-ef
-ad
-ec
-ef
-8d
+bd
+0b
 ff
+8d
+e6
 ef
 cb
 80
-e3
+fd
+48
+65
+6c
+6c
+6f
+2c
+20
+77
+6f
+72
+6c
+64
+21
+00
+00
+00
+00
+00
 00
 00
 00

hw/efinix_fpga/super6502.xml

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="super6502" description="" last_change_date="Wed January 11 2023 21:04:23" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="super6502" description="" last_change_date="Thu January 12 2023 12:02:15" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion"/>
         <efx:device name="T20F256"/>

hw/efinix_fpga/test_programs/Makefile

@@ -1,11 +1,11 @@
-TARGETS=stacktest runram timer timer_irq multiplier divider
+TARGETS=stacktest runram timer timer_irq multiplier divider uart
 SRC=$(wildcard *.s)
 DIR=../ip/bram
 
 all: $(TARGETS)
 
 $(TARGETS): $(SRC)
-	cl65 --cpu 65c02 -C link.ld -l $@.list $@.s
+	cl65 --cpu 65c02 -t none -C link.ld -l $@.list $@.s
 	xxd -ps $@ | fold -w 2 > $@.hex
 
 install:

hw/efinix_fpga/test_programs/uart.s

@@ -0,0 +1,28 @@
+.code
+
+UART_TX = $efe6
+UART_RX = UART_TX
+UART_STATUS = $efe7
+UART_CONTROL = UART_STATUS
+
+main:
+    ldx #$00
+loop:
+    lda string,x
+    sta UART_TX
+
+end:
+    wai
+    bra end
+
+
+
+string:
+    .asciiz "Hello, world!"
+
+
+.segment "VECTORS"
+
+.addr main
+.addr main
+.addr main

hw/efinix_fpga/uart_wrapper.sv

@@ -14,7 +14,7 @@ module uart_wrapper(
     output logic irqb
 );
 
-logic status, control;
+logic [7:0] status, control;
 
 logic tx_busy, rx_busy;
 
@@ -44,23 +44,29 @@ uart u_uart(
 
 enum bit [1:0] {READY, WAIT, TRANSMIT} state, next_state;
 
-always_ff @(negedge clk) begin
+always_ff @(posedge clk_50) begin
     if (reset) begin
         state = READY;
         irqb <= '1;
     end else begin
         state <= next_state;
     end
+end
 
-    case (addr)
-        1'b0: begin
-            tx_data <= i_data;
-        end 
+always_ff @(negedge clk) begin
+    status[0] <= status[0] | rx_data_valid;
 
-        1'b1: begin
-            control <= i_data;
-        end
-    endcase
+    if (cs & ~rwb) begin
+        case (addr)
+            1'b0: begin
+                tx_data <= i_data;
+            end 
+
+            1'b1: begin
+                control <= i_data;
+            end
+        endcase
+    end
 
 end
 
@@ -83,13 +89,14 @@ always_comb begin
 
     case (state)
         READY: begin
-            if (~rwb && addr == 1'b0) begin //write to transmit
+            if (cs & ~rwb && addr == 1'b0) begin //write to transmit
                 tx_en = 1'b1;
                 next_state = WAIT;
             end
         end
 
         WAIT: begin
+            tx_en = 1'b1;
             if (tx_busy) begin
                 next_state = TRANSMIT;
             end