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Create quartus project

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This commit is contained in:
Byron Lathi
2022-03-05 17:52:42 -06:00
parent b996d93c99
commit aca17a9cf8
10 changed files with 3761 additions and 1 deletions
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hw/fpga/ram.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram.v"]