diff --git a/Makefile b/Makefile
index 4a96722..f13bfba 100644
--- a/Makefile
+++ b/Makefile
@@ -14,6 +14,9 @@ fpga_image: $(INIT_HEX)
 sim: $(INIT_HEX)
 	$(MAKE) -C hw/super6502_fpga/src/sim
 
+waves: sim
+	gtkwave hw/super6502_fpga/src/sim/sim_top.vcd
+
 # SW
 .PHONY: toolchain
 toolchain:
diff --git a/hw/super6502_fpga/ip/sdram_controller/sdram_controller.v b/hw/super6502_fpga/ip/sdram_controller/sdram_controller.v
index ad24e9d..926328a 100644
--- a/hw/super6502_fpga/ip/sdram_controller/sdram_controller.v
+++ b/hw/super6502_fpga/ip/sdram_controller/sdram_controller.v
@@ -736,13 +736,13 @@ begin
 					if (SDR_BWIDTH > AXI_WDATA_WIDTH)
 					begin
 						r_addr_1P[0+:BA_WIDTH+ROW_WIDTH+COL_WIDTH-(0-SDR_BWIDTH/AXI_WDATA_WIDTH+1)]	<= i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0-SDR_BWIDTH/AXI_WDATA_WIDTH+1];
-						$display("foo_gt\n");
+						// $display("foo_gt\n");
 					end
 					else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
 					begin
 						r_addr_1P	<= {i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:COL_WIDTH], {(DATA_RATE-1){1'b0}}, i_AXI4_AWADDR[COL_WIDTH-1:DATA_RATE-1]};
 						//r_addr_1P	<= {{(DATA_RATE-1){1'b0}},i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:DATA_RATE-1]};
-						$display("foo_eq\n");
+						// $display("foo_eq\n");
 					end
 					
 					if (SDR_BWIDTH > AXI_WDATA_WIDTH)
@@ -750,7 +750,7 @@ begin
 						//r_AXI4_WREADY_c				<= 1'b1;
 						r_size_1P						<= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1;
 						r_shift_cnt_1P					<= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1;
-						$display("SDR_BWIDTH %d > AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
+						// $display("SDR_BWIDTH %d > AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
 					end
 					else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
 					begin
@@ -762,14 +762,14 @@ begin
 						end
 						r_size_1P			<= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1;
 						r_shift_cnt_1P		<= {7{1'b0}};
-						$display("SDR_BWIDTH %d = AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
+						// $display("SDR_BWIDTH %d = AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
 					end
 					else
 					begin
 						//r_AXI4_WREADY_c	<= 1'b1;
 						r_size_1P			<= AXI_WDATA_WIDTH/SDR_BWIDTH-1'b1;
 						r_shift_cnt_1P		<= AXI_WDATA_WIDTH/SDR_BWIDTH-1'b1;
-						$display("SDR_BWIDTH %d < AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
+						// $display("SDR_BWIDTH %d < AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
 					end
 				end
 			end
diff --git a/hw/super6502_fpga/src/sim/Makefile b/hw/super6502_fpga/src/sim/Makefile
index caf1014..5c25611 100644
--- a/hw/super6502_fpga/src/sim/Makefile
+++ b/hw/super6502_fpga/src/sim/Makefile
@@ -10,6 +10,8 @@ TB_NAME=sim_top
 
 COPY_FILES=addr_map.mem init_hex.mem
 
+FLAGS=-DSIM -DRTL_SIM
+
 all: waves
 
 waves: $(TB_NAME)
@@ -25,4 +27,4 @@ $(COPY_FILES): ../../$@
 clean:
 	rm -rf $(COPY_FILES)
 	rm -rf $(TB_NAME)
-	rm -rf sim_top.vcd
\ No newline at end of file
+	rm -rf sim_top.vcd