Fix sdram wrapper state machine

hw/efinix_fpga/simulation/src/sim_top.sv

@@ -34,10 +34,14 @@ end
 initial begin
     r_clk_cpu <= '1;
     forever begin
-        #250 r_clk_cpu <= ~r_clk_cpu;
+        #125 r_clk_cpu <= ~r_clk_cpu;
     end
 end
 
+initial begin
+    #275000 $finish();
+end
+
 initial begin
     $dumpfile("sim_top.vcd");
     $dumpvars(0,sim_top);