From f276c5469e0da450ee52768617b9b6e0fe02772e Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Fri, 8 Apr 2022 00:49:59 -0500
Subject: [PATCH 01/20] Fix indentation

---
 hw/fpga/hvl/mm_testbench.sv | 80 ++++++++++++++++++-------------------
 1 file changed, 40 insertions(+), 40 deletions(-)

diff --git a/hw/fpga/hvl/mm_testbench.sv b/hw/fpga/hvl/mm_testbench.sv
index b498337..1b18ee3 100644
--- a/hw/fpga/hvl/mm_testbench.sv
+++ b/hw/fpga/hvl/mm_testbench.sv
@@ -25,61 +25,61 @@ assign MA = cpu_addr[15:12];
 assign mm_address = {MO, cpu_addr[11:0]};
 
 memory_mapper dut(
-	.data_in(_data_in),
-	.data_out(_data_out),
-	.*
+    .data_in(_data_in),
+    .data_out(_data_out),
+    .*
 );
 
 always #1 clk_50 = clk_50 === 1'b0;
 always #100 clk = clk === 1'b0;
 
 task write_reg(logic [3:0] addr, logic [7:0] data);
-	@(negedge clk);
-	cs <= '1;
-	RS <= addr;
-	data_in <= data;
-	rw <= '0;
-	@(posedge clk);
-	cs <= '0;
-	rw <= '1;
-	@(negedge clk);
+    @(negedge clk);
+    cs <= '1;
+    RS <= addr;
+    data_in <= data;
+    rw <= '0;
+    @(posedge clk);
+    cs <= '0;
+    rw <= '1;
+    @(negedge clk);
 endtask
 
 task enable(logic [7:0] data);
-	@(negedge clk);
-	MM_cs <= '1;
-	rw <= '0;
-	data_in <= data;
-	@(posedge clk);
-	rw <= '1;
-	MM_cs <= '0;
-	@(negedge clk);
+    @(negedge clk);
+    MM_cs <= '1;
+    rw <= '0;
+    data_in <= data;
+    @(posedge clk);
+    rw <= '1;
+    MM_cs <= '0;
+    @(negedge clk);
 endtask
 
 initial begin
-	rst <= '1;
-	repeat(5) @(posedge clk);
-	rst <= '0;
+    rst <= '1;
+    repeat(5) @(posedge clk);
+    rst <= '0;
 
-	cpu_addr <= 16'h0abc;
-	write_reg(4'h0, 8'hcc);
-	$display("Address: %x", mm_address);
-	assert(mm_address == 24'h000abc) else begin
-		$error("Bad address before enable!");
-	end
+    cpu_addr <= 16'h0abc;
+    write_reg(4'h0, 8'hcc);
+    $display("Address: %x", mm_address);
+    assert(mm_address == 24'h000abc) else begin
+        $error("Bad address before enable!");
+    end
 
-	enable(1);
-	$display("Address: %x", mm_address);
-	assert(mm_address == 24'h0ccabc) else begin
-		$error("Bad address after enable!");
-	end
+    enable(1);
+    $display("Address: %x", mm_address);
+    assert(mm_address == 24'h0ccabc) else begin
+        $error("Bad address after enable!");
+    end
 
-	enable(0);
-	$display("Address: %x", mm_address);
-	assert(mm_address == 24'h000abc) else begin
-		$error("Bad address after enable!");
-	end
-	$finish();
+    enable(0);
+    $display("Address: %x", mm_address);
+    assert(mm_address == 24'h000abc) else begin
+        $error("Bad address after enable!");
+    end
+    $finish();
 end
 
 endmodule

From e828df0807477a4837b0c6258b0ebcda7bc77536 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Fri, 8 Apr 2022 00:50:28 -0500
Subject: [PATCH 02/20] Add crc7 module

This module takes in a 40 bit word and generates the 7 bit crc7
appropriate for an SD card.

It does not use any fancy parallel algorithm, it does it 1 bit at a
time.
---
 hw/fpga/crc7.sv       | 105 ++++++++++++++++++++++++++++++++++++++++++
 hw/fpga/super6502.qsf |   1 +
 2 files changed, 106 insertions(+)
 create mode 100644 hw/fpga/crc7.sv

diff --git a/hw/fpga/crc7.sv b/hw/fpga/crc7.sv
new file mode 100644
index 0000000..960f22c
--- /dev/null
+++ b/hw/fpga/crc7.sv
@@ -0,0 +1,105 @@
+module crc7 #(parameter POLYNOMIAL = 8'h89)
+(
+    input clk,
+    input rst,
+
+    input load,
+    input [39:0] data_in,
+
+    output logic [6:0] crc_out,
+    output logic valid
+);
+
+logic [46:0] data;
+logic [46:0] next_data;
+logic [46:0] polyshift;
+
+typedef enum bit [1:0] {IDLE, WORKING, VALID} macro_t;
+struct packed {
+    macro_t macro;
+    logic [5:0] count;
+} state, next_state;
+
+always_ff @(posedge clk) begin
+    if (rst) begin
+        polyshift <= {POLYNOMIAL, 39'b0};    //start all the way at the left
+        data <= '0;
+        state.macro <= IDLE;
+        state.count <= '0;
+    end else begin
+        if (load) begin
+            data <= {data_in, 7'b0};
+        end else begin
+            data <= next_data;
+        end
+        state <= next_state;
+
+        if (state.macro == WORKING) begin
+            polyshift <= polyshift >> 1;
+        end
+
+        if (state.macro == VALID) begin
+            polyshift <= {POLYNOMIAL, 39'b0};
+        end
+    end
+end
+
+always_comb begin
+    next_state = state;
+
+    case (state.macro)
+        IDLE: begin
+            if (load) begin
+                next_state.macro = WORKING;
+                next_state.count = '0;
+            end
+        end
+
+        WORKING: begin
+            if (state.count < 39) begin
+                next_state.count = state.count + 6'b1;
+            end else begin
+                next_state.macro = VALID;
+                next_state.count = '0;
+            end
+        end
+
+        VALID: begin            // Same as IDLE, but IDLE is just for reset.
+            if (load) begin
+                next_state.macro = WORKING;
+                next_state.count = '0;
+            end
+        end
+
+        default:;
+    endcase
+end
+
+always_comb begin
+    valid = 0;
+    next_data = '0;
+    crc_out = '0;
+
+    case (state.macro)
+        IDLE: begin
+            valid = 0;
+        end
+
+        WORKING: begin
+            if (data[6'd46 - state.count]) begin
+                next_data = data ^ polyshift;
+            end else begin
+                next_data = data;
+            end
+        end
+
+        VALID: begin
+            valid =  ~load;
+            crc_out = data[6:0];
+        end
+
+        default:;
+    endcase
+end
+
+endmodule
diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf
index fdb7289..053e5d2 100644
--- a/hw/fpga/super6502.qsf
+++ b/hw/fpga/super6502.qsf
@@ -350,6 +350,7 @@ set_location_assignment PIN_V22 -to DRAM_LDQM
 set_location_assignment PIN_U22 -to DRAM_RAS_N
 set_location_assignment PIN_J21 -to DRAM_UDQM
 set_location_assignment PIN_V20 -to DRAM_WE_N
+set_global_assignment -name SYSTEMVERILOG_FILE crc7.sv
 set_global_assignment -name SYSTEMVERILOG_FILE memory_mapper.sv
 set_global_assignment -name SYSTEMVERILOG_FILE board_io.sv
 set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv

From 3e69109474e8d852ff3a84752992b542062af4a6 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Fri, 8 Apr 2022 00:51:20 -0500
Subject: [PATCH 03/20] Add tests for crc7

These are just some values that I found from an example program. This
does not test every possible value.
---
 .gitlab-ci.yml                                |  7 ++
 hw/fpga/hvl/crc7_testbench.sv                 | 65 +++++++++++++++++++
 hw/fpga/simulation/modelsim/crc7_testbench.do | 23 +++++++
 3 files changed, 95 insertions(+)
 create mode 100644 hw/fpga/hvl/crc7_testbench.sv
 create mode 100644 hw/fpga/simulation/modelsim/crc7_testbench.do

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 25079d4..5e55618 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -45,3 +45,10 @@ test_mm:
     script:
       - cd hw/fpga/simulation/modelsim/
       - vsim -do "do mm_testbench.do"
+
+test_crc7:
+    stage: test
+    image: bslathi19/modelsim_18.1:lite
+    script:
+      - cd hw/fpga/simulation/modelsim/
+      - vsim -do "do crc7_testbench.do"
diff --git a/hw/fpga/hvl/crc7_testbench.sv b/hw/fpga/hvl/crc7_testbench.sv
new file mode 100644
index 0000000..935dd85
--- /dev/null
+++ b/hw/fpga/hvl/crc7_testbench.sv
@@ -0,0 +1,65 @@
+module testbench();
+
+timeunit 10ns;
+
+timeprecision 1ns;
+
+logic clk;
+logic rst;
+
+logic load;
+logic [39:0] data_in;
+
+logic [6:0] crc_out;
+logic valid;
+
+crc7 dut(.*);
+
+always #1 clk = clk === 1'b0;
+
+task create_sd_packet(logic [5:0] cmd, logic [31:0] data, output logic [47:0] _packet);
+    @(posedge clk);
+    data_in <= {1'b0, 1'b1, cmd, data};
+    load <= '1;
+    @(posedge clk);
+    load <= '0;
+
+    while (~valid) begin
+        //$display("Working %b", dut.data);
+        @(posedge clk);
+    end
+
+    _packet = {1'b0, 1'b1, cmd, data, crc_out, 1'b1};
+endtask
+
+logic [47:0] packet;
+
+initial begin
+    rst <= '1;
+    repeat(5) @(posedge clk);
+    rst <= '0;
+
+    create_sd_packet(6'h0, 32'h0, packet);
+    $display("Result: %x", packet);
+    assert(packet == 48'h400000000095) else
+        $error("Bad crc7. Got %x expected %x", packet, 48'h400000000095);
+
+    create_sd_packet(6'd8, 32'h1aa, packet);
+    $display("Result: %x", packet);
+    assert(packet == 48'h48000001aa87) else
+        $error("Bad crc7. Got %x expected %x", packet, 48'h48000001aa87);
+
+    create_sd_packet(6'd55, 32'h0, packet);
+    $display("Result: %x", packet);
+    assert(packet == 48'h770000000065) else
+        $error("Bad crc7. Got %x expected %x", packet, 48'h770000000065);
+        
+    create_sd_packet(6'd41, 32'h40180000, packet);
+    $display("Result: %x", packet);
+    assert(packet == 48'h694018000019) else
+        $error("Bad crc7. Got %x expected %x", packet, 48'h694018000019);
+
+    $finish();
+end
+
+endmodule
diff --git a/hw/fpga/simulation/modelsim/crc7_testbench.do b/hw/fpga/simulation/modelsim/crc7_testbench.do
new file mode 100644
index 0000000..a79c2f4
--- /dev/null
+++ b/hw/fpga/simulation/modelsim/crc7_testbench.do
@@ -0,0 +1,23 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -sv -work work  {../../crc7.sv}
+vlog -sv -work work  {../../hvl/crc7_testbench.sv}
+
+vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixv_ver -L stratixv_hssi_ver -L stratixv_pcie_hip_ver -L rtl_work -L work -voptargs="+acc"  testbench
+
+add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*
+
+onfinish stop
+run -all
+
+if { [coverage attribute -name TESTSTATUS -concise] == "1"} {
+    echo Warning
+    quit -f -code 0
+}
+
+quit -code [coverage attribute -name TESTSTATUS -concise]

From 552fe8b6f86a8e1956e34a269d68fa7ef4006ad7 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Fri, 8 Apr 2022 12:25:17 -0500
Subject: [PATCH 04/20] Have valid crc when valid signal is present

Previously the crc would be reset after 1 clock cycle while the valid
signal was still high. Now the data is preserved in the valid state
until the load signal is asserted.
---
 hw/fpga/crc7.sv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/fpga/crc7.sv b/hw/fpga/crc7.sv
index 960f22c..e009826 100644
--- a/hw/fpga/crc7.sv
+++ b/hw/fpga/crc7.sv
@@ -95,6 +95,7 @@ always_comb begin
 
         VALID: begin
             valid =  ~load;
+            next_data = data;
             crc_out = data[6:0];
         end
 

From f89ecfa038309666b4a1458212b4007f13eb5133 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Fri, 8 Apr 2022 12:28:17 -0500
Subject: [PATCH 05/20] Add SD Card controller for sending commands

Adds the start of the SD card controller which is capable of sending
commands using the SD protocol.

It is accessed by writing the arguments first and triggered by writing
the command number.
---
 hw/fpga/sd_controller.sv | 124 +++++++++++++++++++++++++++++++++++++++
 hw/fpga/super6502.qsf    |   1 +
 2 files changed, 125 insertions(+)
 create mode 100644 hw/fpga/sd_controller.sv

diff --git a/hw/fpga/sd_controller.sv b/hw/fpga/sd_controller.sv
new file mode 100644
index 0000000..b898803
--- /dev/null
+++ b/hw/fpga/sd_controller.sv
@@ -0,0 +1,124 @@
+module sd_controller(
+    input clk,
+    input rst,
+
+    input [3:0] addr,
+    input [7:0] data,
+    input cs,
+
+    input i_sd_cmd,
+    output logic o_sd_cmd,
+
+    input i_sd_data,
+    output logic o_sd_dat
+);
+
+logic [31:0] arg;
+logic [5:0] cmd;
+
+logic [47:0] rxcmd_buf;
+
+typedef enum bit [1:0] {IDLE, CRC, TXCMD, RXCMD} macro_t;
+struct packed {
+    macro_t macro;
+    logic [5:0] count;
+} state, next_state;
+
+always_ff @(posedge clk) begin
+    if (rst) begin
+        state.macro <= IDLE;
+        state.count <= '0;
+    end else begin
+        state <= next_state;
+    end
+
+    if (state.macro == IDLE) begin
+        if (cs) begin
+            if (addr < 4'h4) begin
+                arg[8 * addr +: 8] <= data;
+            end else if (addr == 4'h4) begin
+                cmd <= data;
+            end
+        end
+    end else if (state.macro == RXCMD) begin
+        rxcmd_buf[6'd46-state.count] <= i_sd_cmd;   //we probabily missed bit 47
+    end
+end
+
+logic [6:0] crc;
+logic load_crc;
+logic crc_valid;
+logic [39:0] _packet;
+assign _packet = {1'b0, 1'b1, cmd, arg};
+logic [47:0] packet_crc;
+assign packet_crc = {_packet, crc, 1'b1};
+
+crc7 u_crc7(
+    .clk(clk),
+    .rst(rst),
+    .load(load_crc),
+    .data_in(_packet),
+    .crc_out(crc),
+    .valid(crc_valid)
+);
+
+always_comb begin
+    next_state = state;
+
+    case (state.macro)
+        IDLE: begin
+            if (~i_sd_cmd) begin        // receive data if sd pulls cmd low
+                next_state.macro = RXCMD;
+            end
+
+            if (addr == 4'h4 & cs) begin     // transmit if cpu writes to cmd
+                next_state.macro = CRC;
+            end
+        end
+
+        CRC: begin
+            next_state.macro = TXCMD;
+        end
+
+        TXCMD: begin
+            if (state.count < 47) begin
+                next_state.count = state.count + 6'b1;
+            end else begin
+                next_state.macro = IDLE;
+                next_state.count = '0;
+            end
+        end
+
+        RXCMD: begin
+            if (state.count < 47) begin
+                next_state.count = state.count + 6'b1;
+            end else begin
+                next_state.macro = IDLE;
+                next_state.count = '0;
+            end
+        end
+    endcase
+end
+
+always_comb begin
+    o_sd_cmd = '1;  //default to 1
+    o_sd_dat = '1;
+
+    load_crc = '0;
+
+    case (state.macro)
+        IDLE:;
+
+        CRC: begin
+            load_crc = '1;
+        end
+
+        TXCMD: begin
+            o_sd_cmd = packet_crc[6'd47 - state.count];
+        end
+
+        RXCMD:;
+    endcase
+end
+
+endmodule
diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf
index 053e5d2..bd10e36 100644
--- a/hw/fpga/super6502.qsf
+++ b/hw/fpga/super6502.qsf
@@ -350,6 +350,7 @@ set_location_assignment PIN_V22 -to DRAM_LDQM
 set_location_assignment PIN_U22 -to DRAM_RAS_N
 set_location_assignment PIN_J21 -to DRAM_UDQM
 set_location_assignment PIN_V20 -to DRAM_WE_N
+set_global_assignment -name SYSTEMVERILOG_FILE sd_controller.sv
 set_global_assignment -name SYSTEMVERILOG_FILE crc7.sv
 set_global_assignment -name SYSTEMVERILOG_FILE memory_mapper.sv
 set_global_assignment -name SYSTEMVERILOG_FILE board_io.sv

From 38566f7b4aee405e6f826de01b9e4b6c11d888cf Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Fri, 8 Apr 2022 12:29:15 -0500
Subject: [PATCH 06/20] add testbench for SD command tx

Sends a few commands which we know the proper checksum for and makes
sure that the bits on the output are correct.
---
 .gitlab-ci.yml                                |  7 ++
 hw/fpga/hvl/sd_cmd_testbench.sv               | 74 +++++++++++++++++++
 .../simulation/modelsim/sd_cmd_testbench.do   | 24 ++++++
 3 files changed, 105 insertions(+)
 create mode 100644 hw/fpga/hvl/sd_cmd_testbench.sv
 create mode 100644 hw/fpga/simulation/modelsim/sd_cmd_testbench.do

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 5e55618..04a587b 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -52,3 +52,10 @@ test_crc7:
     script:
       - cd hw/fpga/simulation/modelsim/
       - vsim -do "do crc7_testbench.do"
+
+test_sd_cmd:
+    stage: test
+    image: bslathi19/modelsim_18.1:lite
+    script:
+      - cd hw/fpga/simulation/modelsim/
+      - vsim -do "sd_cmd_testbench.do"
diff --git a/hw/fpga/hvl/sd_cmd_testbench.sv b/hw/fpga/hvl/sd_cmd_testbench.sv
new file mode 100644
index 0000000..f123ce2
--- /dev/null
+++ b/hw/fpga/hvl/sd_cmd_testbench.sv
@@ -0,0 +1,74 @@
+module testbench();
+
+timeunit 10ns;
+
+timeprecision 1ns;
+
+logic clk;
+logic clk_50;
+logic rst;
+
+logic [3:0] addr;
+logic [7:0] data;
+logic cs;
+
+logic i_sd_cmd;
+logic o_sd_cmd;
+
+logic i_sd_data;
+logic o_sd_dat;
+
+sd_controller dut(.*);
+
+always #1 clk_50 = clk_50 === 1'b0;
+always #100 clk = clk === 1'b0;
+
+task write_reg(logic [3:0] _addr, logic [7:0] _data);
+    @(negedge clk);
+    cs <= '1;
+    addr <= _addr;
+    data <= _data;
+    @(posedge clk);
+    cs <= '0;
+    @(negedge clk);
+endtask
+
+task verify_cmd(logic [5:0] cmd, logic [31:0] arg, logic [47:0] verify);
+    write_reg(0, arg[7:0]);
+    write_reg(1, arg[15:8]);
+    write_reg(2, arg[23:16]);
+    write_reg(3, arg[31:24]);
+    write_reg(4, cmd);
+
+    @(posedge clk);
+    @(posedge clk);
+
+    while (dut.state.macro == dut.TXCMD) begin
+        assert(o_sd_cmd == verify[47-dut.state.count]) else begin
+            $error("cmd output error: Expected %h:%b, got %h:%b", 
+                47-dut.state.count, verify[47-dut.state.count],
+                47-dut.state.count, o_sd_cmd);
+        end
+        @(negedge clk);
+    end
+endtask
+
+localparam cmd0 = 48'h400000000095;
+localparam cmd8 = 48'h48000001aa87;
+localparam cmd55 = 48'h770000000065;
+localparam cmd41 = 48'h694018000019;
+
+initial begin
+    rst <= '1;
+    repeat(5) @(posedge clk);
+    rst <= '0;
+
+    verify_cmd(0, 0, cmd0);
+    verify_cmd(8, 'h1aa, cmd8);
+    verify_cmd('d55, 0, cmd55);
+    verify_cmd('d41, 'h40180000, cmd41);
+
+    $finish();
+end
+
+endmodule
\ No newline at end of file
diff --git a/hw/fpga/simulation/modelsim/sd_cmd_testbench.do b/hw/fpga/simulation/modelsim/sd_cmd_testbench.do
new file mode 100644
index 0000000..ee0bc8f
--- /dev/null
+++ b/hw/fpga/simulation/modelsim/sd_cmd_testbench.do
@@ -0,0 +1,24 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -sv -work work  {../../sd_controller.sv}
+vlog -sv -work work  {../../crc7.sv}
+vlog -sv -work work  {../../hvl/sd_cmd_testbench.sv}
+
+vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixv_ver -L stratixv_hssi_ver -L stratixv_pcie_hip_ver -L rtl_work -L work -voptargs="+acc"  testbench
+
+add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*
+
+onfinish stop
+run -all
+
+if { [coverage attribute -name TESTSTATUS -concise] == "1"} {
+    echo Warning
+    quit -f -code 0
+}
+
+quit -code [coverage attribute -name TESTSTATUS -concise]

From 31a4656cac6467c406d4013afbc06a2a831c5adc Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sat, 9 Apr 2022 17:31:25 -0500
Subject: [PATCH 07/20] Reduce sd_controller addr width from 4 to 3

---
 hw/fpga/hvl/sd_cmd_testbench.sv | 2 +-
 hw/fpga/sd_controller.sv        | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/fpga/hvl/sd_cmd_testbench.sv b/hw/fpga/hvl/sd_cmd_testbench.sv
index f123ce2..374041d 100644
--- a/hw/fpga/hvl/sd_cmd_testbench.sv
+++ b/hw/fpga/hvl/sd_cmd_testbench.sv
@@ -8,7 +8,7 @@ logic clk;
 logic clk_50;
 logic rst;
 
-logic [3:0] addr;
+logic [2:0] addr;
 logic [7:0] data;
 logic cs;
 
diff --git a/hw/fpga/sd_controller.sv b/hw/fpga/sd_controller.sv
index b898803..6202a2f 100644
--- a/hw/fpga/sd_controller.sv
+++ b/hw/fpga/sd_controller.sv
@@ -2,7 +2,7 @@ module sd_controller(
     input clk,
     input rst,
 
-    input [3:0] addr,
+    input [2:0] addr,
     input [7:0] data,
     input cs,
 

From 09428c887516349a391383222254547816cac7f2 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sun, 10 Apr 2022 16:15:55 -0500
Subject: [PATCH 08/20] Add sd card cs

---
 hw/fpga/addr_decode.sv      | 6 ++++--
 hw/fpga/hvl/cs_testbench.sv | 8 +++++++-
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/hw/fpga/addr_decode.sv b/hw/fpga/addr_decode.sv
index a145fcc..c127697 100644
--- a/hw/fpga/addr_decode.sv
+++ b/hw/fpga/addr_decode.sv
@@ -6,8 +6,9 @@ module addr_decode(
     output logic uart_cs,
     output logic irq_cs,
     output logic board_io_cs,
-	output logic mm_cs1,
-	output logic mm_cs2
+    output logic mm_cs1,
+    output logic mm_cs2,
+    output logic sd_cs
 );
 
 assign rom_cs = addr >= 24'h008000 && addr < 24'h010000;
@@ -17,6 +18,7 @@ assign hex_cs = addr >= 24'h007ff0 && addr < 24'h007ff4;
 assign uart_cs = addr >= 24'h007ff4 && addr < 24'h007ff6;
 assign board_io_cs = addr == 24'h007ff6;
 assign mm_cs2 = addr == 24'h007ff7;
+assign sd_cs = addr >= 24'h007ff8 && addr < 24'h007ffd;
 assign irq_cs  = addr == 24'h007fff;
 
 endmodule
diff --git a/hw/fpga/hvl/cs_testbench.sv b/hw/fpga/hvl/cs_testbench.sv
index a6e1072..64dbe7f 100644
--- a/hw/fpga/hvl/cs_testbench.sv
+++ b/hw/fpga/hvl/cs_testbench.sv
@@ -13,8 +13,9 @@ logic uart_cs;
 logic irq_cs;
 logic mm_cs2;
 logic mm_cs1;
+logic sd_cs;
 
-int cs_count = sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs + mm_cs2 + mm_cs1;
+int cs_count = sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs + mm_cs2 + mm_cs1 + sd_cs;
 
 addr_decode dut(.*);
 
@@ -56,6 +57,11 @@ initial begin : TEST_VECTORS
             else
                 $error("Bad CS! addr=%4x should have mm_cs1!", addr);
         end
+        if (i >= 24'h007ff8 && i < 24'h007ffd) begin
+            assert(sd_cs == '1)
+            else
+            $error("Bad CS! addr=%4x should have sd_cs!", addr);
+        end
         if (i == 16'h7fff) begin
             assert(irq_cs == '1)
             else

From 50b0860137799c266b4881a0cc364354fb07811b Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sun, 10 Apr 2022 17:50:49 -0500
Subject: [PATCH 09/20] Update testbench with more realistic timings

Updates the testbench to simulate writes with more correct timings.
Writes take two clock cycles since the cpu runs at half speed.
---
 hw/fpga/hvl/sd_cmd_testbench.sv | 31 +++++++++++++++++++++++--------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/hw/fpga/hvl/sd_cmd_testbench.sv b/hw/fpga/hvl/sd_cmd_testbench.sv
index 374041d..b90b7bc 100644
--- a/hw/fpga/hvl/sd_cmd_testbench.sv
+++ b/hw/fpga/hvl/sd_cmd_testbench.sv
@@ -5,6 +5,7 @@ timeunit 10ns;
 timeprecision 1ns;
 
 logic clk;
+logic rw;
 logic clk_50;
 logic rst;
 
@@ -16,21 +17,32 @@ logic i_sd_cmd;
 logic o_sd_cmd;
 
 logic i_sd_data;
-logic o_sd_dat;
+logic o_sd_data;
 
-sd_controller dut(.*);
+logic cpu_phi2;
+
+always @(posedge clk) begin
+    cpu_phi2 <= cpu_phi2 === '0;
+end
+
+sd_controller dut(
+    .sd_clk(cpu_phi2),
+    .*);
 
 always #1 clk_50 = clk_50 === 1'b0;
 always #100 clk = clk === 1'b0;
 
 task write_reg(logic [3:0] _addr, logic [7:0] _data);
-    @(negedge clk);
-    cs <= '1;
-    addr <= _addr;
-    data <= _data;
     @(posedge clk);
-    cs <= '0;
-    @(negedge clk);
+    cs = '1;
+    addr = _addr;
+    rw = '0;
+    data = '1;
+    @(posedge clk);
+    data = _data;
+    @(posedge clk);
+    cs = '0;
+    rw = '1;
 endtask
 
 task verify_cmd(logic [5:0] cmd, logic [31:0] arg, logic [47:0] verify);
@@ -40,6 +52,9 @@ task verify_cmd(logic [5:0] cmd, logic [31:0] arg, logic [47:0] verify);
     write_reg(3, arg[31:24]);
     write_reg(4, cmd);
 
+    $display("arg: %x", dut.arg);
+    $display("dut.cmd: %x", dut.cmd);
+
     @(posedge clk);
     @(posedge clk);
 

From 1128b986eb1349c0cea29914570c63926f4ee144 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sun, 10 Apr 2022 17:52:07 -0500
Subject: [PATCH 10/20] Fix state transitions with regard to clock

The SD card expects data to transition on falling edges and be stable on
rising edges.

Additionally, writes from the CPU were not handled with correct timing.

Now, there is an extra state when writing to the command register so
that the command is properly latched before the CRC is calculated.
---
 hw/fpga/sd_controller.sv | 39 +++++++++++++++++++++++++--------------
 1 file changed, 25 insertions(+), 14 deletions(-)

diff --git a/hw/fpga/sd_controller.sv b/hw/fpga/sd_controller.sv
index 6202a2f..4dacc9b 100644
--- a/hw/fpga/sd_controller.sv
+++ b/hw/fpga/sd_controller.sv
@@ -1,16 +1,18 @@
 module sd_controller(
     input clk,
+    input sd_clk,
     input rst,
 
     input [2:0] addr,
     input [7:0] data,
     input cs,
+    input rw,
 
     input i_sd_cmd,
     output logic o_sd_cmd,
 
     input i_sd_data,
-    output logic o_sd_dat
+    output logic o_sd_data
 );
 
 logic [31:0] arg;
@@ -18,7 +20,7 @@ logic [5:0] cmd;
 
 logic [47:0] rxcmd_buf;
 
-typedef enum bit [1:0] {IDLE, CRC, TXCMD, RXCMD} macro_t;
+typedef enum bit [2:0] {IDLE, LOAD, CRC, TXCMD, RXCMD} macro_t;
 struct packed {
     macro_t macro;
     logic [5:0] count;
@@ -29,18 +31,23 @@ always_ff @(posedge clk) begin
         state.macro <= IDLE;
         state.count <= '0;
     end else begin
-        state <= next_state;
+        if (state.macro == TXCMD || state.macro == CRC) begin
+            if (sd_clk) begin
+                state <= next_state;
+            end
+        end else begin
+            state <= next_state;
+        end
     end
 
-    if (state.macro == IDLE) begin
-        if (cs) begin
-            if (addr < 4'h4) begin
-                arg[8 * addr +: 8] <= data;
-            end else if (addr == 4'h4) begin
-                cmd <= data;
-            end
+    if (cs & ~rw) begin
+        if (addr < 4'h4) begin
+            arg[8 * addr +: 8] <= data;
+        end else if (addr == 4'h4) begin
+            cmd <= data;
         end
-    end else if (state.macro == RXCMD) begin
+    end
+    if (state.macro == RXCMD) begin
         rxcmd_buf[6'd46-state.count] <= i_sd_cmd;   //we probabily missed bit 47
     end
 end
@@ -71,11 +78,15 @@ always_comb begin
                 next_state.macro = RXCMD;
             end
 
-            if (addr == 4'h4 & cs) begin     // transmit if cpu writes to cmd
-                next_state.macro = CRC;
+            if (addr == 4'h4 & cs & ~rw) begin     // transmit if cpu writes to cmd
+                next_state.macro = LOAD;
             end
         end
 
+        LOAD: begin
+            next_state.macro = CRC;
+        end
+
         CRC: begin
             next_state.macro = TXCMD;
         end
@@ -102,7 +113,7 @@ end
 
 always_comb begin
     o_sd_cmd = '1;  //default to 1
-    o_sd_dat = '1;
+    o_sd_data = '1;
 
     load_crc = '0;
 

From cd11670fb17ef20f7038bb09bdc0be60e2e6ac5a Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sun, 10 Apr 2022 17:54:08 -0500
Subject: [PATCH 11/20] Add sd controller to top level

Also adds the logic required for the bidirectional sd lines and attaches
the controller to the cpu.
---
 hw/fpga/super6502.qsf | 35 ++++++++++++++++++++++++++++++++++-
 hw/fpga/super6502.sv  | 36 +++++++++++++++++++++++++++++++++---
 2 files changed, 67 insertions(+), 4 deletions(-)

diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf
index bd10e36..191ee02 100644
--- a/hw/fpga/super6502.qsf
+++ b/hw/fpga/super6502.qsf
@@ -188,7 +188,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_sob
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_sync
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_50
 set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp2.stp
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/sd.stp
 set_location_assignment PIN_F20 -to HEX4[6]
 set_location_assignment PIN_F19 -to HEX4[5]
 set_location_assignment PIN_H19 -to HEX4[4]
@@ -205,6 +205,20 @@ set_location_assignment PIN_F18 -to HEX4[0]
 set_location_assignment PIN_E20 -to HEX4[1]
 set_location_assignment PIN_AB5 -to UART_RXD
 set_location_assignment PIN_AB6 -to UART_TXD
+set_location_assignment PIN_AB7 -to ARDUINO_IO[2]
+set_location_assignment PIN_AB8 -to ARDUINO_IO[3]
+set_location_assignment PIN_AB9 -to ARDUINO_IO[4]
+set_location_assignment PIN_Y10 -to ARDUINO_IO[5]
+set_location_assignment PIN_AA11 -to ARDUINO_IO[6]
+set_location_assignment PIN_AA12 -to ARDUINO_IO[7]
+set_location_assignment PIN_AB17 -to ARDUINO_IO[8]
+set_location_assignment PIN_AA17 -to ARDUINO_IO[9]
+set_location_assignment PIN_AB19 -to ARDUINO_IO[10]
+set_location_assignment PIN_AA19 -to ARDUINO_IO[11]
+set_location_assignment PIN_Y19 -to ARDUINO_IO[12]
+set_location_assignment PIN_AB20 -to ARDUINO_IO[13]
+set_location_assignment PIN_AB21 -to ARDUINO_IO[14]
+set_location_assignment PIN_AA20 -to ARDUINO_IO[15]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
@@ -367,4 +381,23 @@ set_global_assignment -name SYSTEMVERILOG_FILE SevenSeg.sv
 set_global_assignment -name QIP_FILE cpu_clk.qip
 set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
 set_global_assignment -name SIGNALTAP_FILE output_files/stp2.stp
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[11]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[12]
+set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv
index fdfdafa..1e2009f 100644
--- a/hw/fpga/super6502.sv
+++ b/hw/fpga/super6502.sv
@@ -26,8 +26,10 @@ module super6502(
     input   logic           UART_RXD,
     output  logic           UART_TXD,
 
-    input [7:0] SW,
-    output [7:0] LED,
+    input                   [7:0] SW,
+    output  logic           [7:0] LED,
+
+    inout   logic [15: 0]   ARDUINO_IO,
 
     ///////// SDRAM /////////
     output             DRAM_CLK,
@@ -54,6 +56,16 @@ assign cpu_data_in = cpu_data;
 logic [7:0] cpu_data_out;
 assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
 
+logic o_sd_cmd, i_sd_cmd;
+logic o_sd_data, i_sd_data;
+
+assign ARDUINO_IO[11] = o_sd_cmd ? 1'bz : 1'b0;
+assign ARDUINO_IO[12] = o_sd_data ? 1'bz : 1'b0;
+assign ARDUINO_IO[13] = cpu_phi2;
+assign ARDUINO_IO[6] = 1'b1;
+
+assign i_sd_cmd = ARDUINO_IO[11];
+assign i_sd_data = ARDUINO_IO[12];
 
 logic [7:0] rom_data_out;
 logic [7:0] sdram_data_out;
@@ -70,6 +82,7 @@ logic irq_cs;
 logic board_io_cs;
 logic mm_cs1;
 logic mm_cs2;
+logic sd_cs;
 
 cpu_clk cpu_clk(
 	.inclk0(clk_50),
@@ -114,7 +127,8 @@ addr_decode decode(
     .irq_cs(irq_cs),
     .board_io_cs(board_io_cs),
 	.mm_cs1(mm_cs1),
-	.mm_cs2(mm_cs2)
+	.mm_cs2(mm_cs2),
+    .sd_cs(sd_cs)
 );
 
 
@@ -204,6 +218,22 @@ uart uart(
     .data_out(uart_data_out)
 );
 
+sd_controller sd_controller(
+    .clk(clk),
+    .sd_clk(cpu_phi2),
+    .rst(rst),
+    .addr(cpu_addr[2:0]),
+    .data(cpu_data_in),
+    .cs(sd_cs),
+    .rw(cpu_rwb),
+
+    .i_sd_cmd(i_sd_cmd),
+    .o_sd_cmd(o_sd_cmd),
+
+    .i_sd_data(i_sd_data),
+    .o_sd_data(o_sd_data)
+);
+
 always_ff @(posedge clk_50) begin
     if (rst)
         irq_data_out <= '0;

From 7092cc8f77947159976133e17a85e60fdefc9a02 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sun, 10 Apr 2022 17:55:51 -0500
Subject: [PATCH 12/20] Add SD card software interface

Adds a function to send a command to the sd card.
---
 sw/io.inc65  |  3 +++
 sw/main.c    |  4 ++++
 sw/sd_card.h |  8 ++++++++
 sw/sd_card.s | 27 +++++++++++++++++++++++++++
 4 files changed, 42 insertions(+)
 create mode 100644 sw/sd_card.h
 create mode 100644 sw/sd_card.s

diff --git a/sw/io.inc65 b/sw/io.inc65
index 5e87bc2..3586e7c 100644
--- a/sw/io.inc65
+++ b/sw/io.inc65
@@ -11,4 +11,7 @@ SW          = LED
 MM_CTRL		= $7ff7
 MM_DATA		= $7fe0
 
+SD_ARG      = $7ff8
+SD_CMD      = $7ffc
+
 IRQ_STATUS  = $7fff
diff --git a/sw/main.c b/sw/main.c
index 4f894d8..aea99c8 100644
--- a/sw/main.c
+++ b/sw/main.c
@@ -4,6 +4,7 @@
 #include "board_io.h"
 #include "uart.h"
 #include "mapper.h"
+#include "sd_card.h"
 
 int main() {
     int i;
@@ -46,6 +47,9 @@ int main() {
 	cprintf("Reading from 0x4000: %x\n", *(unsigned int*)(0x4000));
 	cprintf("Reading from 0x5000: %x\n", *(unsigned int*)(0x5000));
 
+	sd_card_command(0, 0);
+	sd_card_command(0x000001aa, 8);
+
     while (1) {
 
         sw = sw_read();
diff --git a/sw/sd_card.h b/sw/sd_card.h
new file mode 100644
index 0000000..1cd59af
--- /dev/null
+++ b/sw/sd_card.h
@@ -0,0 +1,8 @@
+#ifndef _SD_CARD_H
+#define _SD_CARD_H
+
+#include <stdint.h>
+
+void sd_card_command(uint32_t arg, uint8_t cmd);
+
+#endif
\ No newline at end of file
diff --git a/sw/sd_card.s b/sw/sd_card.s
new file mode 100644
index 0000000..f6c6ed6
--- /dev/null
+++ b/sw/sd_card.s
@@ -0,0 +1,27 @@
+.include "io.inc65"
+
+.importzp sp, sreg
+
+.export _sd_card_command
+
+.autoimport on
+
+.code
+
+; Send sd card command.
+; command is in A register, the args are on the stack
+; I think the order is high byte first?
+_sd_card_command:
+    pha
+
+    jsr popeax
+    sta SD_ARG
+    stx SD_ARG+1
+    lda sreg
+    sta SD_ARG+2
+    lda sreg+1
+    sta SD_ARG+3
+
+    pla
+    sta SD_CMD
+    rts

From 385efb25114ab3e7b1027ccfb6508952d98e18a9 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sun, 10 Apr 2022 19:34:38 -0500
Subject: [PATCH 13/20] Read some data off of the sd card

These series of commands are enough to read the first 512b block off of
the sd card. The RCA is hard coded to the sd card that I have on hand,
since response codes are not supported
---
 sw/main.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/sw/main.c b/sw/main.c
index aea99c8..81e6cd6 100644
--- a/sw/main.c
+++ b/sw/main.c
@@ -47,8 +47,20 @@ int main() {
 	cprintf("Reading from 0x4000: %x\n", *(unsigned int*)(0x4000));
 	cprintf("Reading from 0x5000: %x\n", *(unsigned int*)(0x5000));
 
+	// This will read a 512 block from the sd card.
+	// The RCA is hard coded for the one that I have on hand as responses
+	// are not implemented yet.
 	sd_card_command(0, 0);
 	sd_card_command(0x000001aa, 8);
+	sd_card_command(0, 55);
+	sd_card_command(0x40180000, 41);
+	sd_card_command(0, 55);
+	sd_card_command(0x40180000, 41);
+	sd_card_command(0, 2);
+	sd_card_command(0, 3);
+	sd_card_command(0x59b40000, 7);
+	sd_card_command(0x59b41000, 13);
+	sd_card_command(0, 17);
 
     while (1) {
 

From f5f1d7ccc6721851b2b996b5747224ff036a0c94 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sun, 10 Apr 2022 23:16:10 -0500
Subject: [PATCH 14/20] Add read flag to sd controller

Read flag is set when the sd controller reads response data in from the
sd card. When the cpu reads from the controller, the flag is reset.

This flag does not trigger an interrupt, it mmust be polled.
---
 hw/fpga/sd_controller.sv | 34 +++++++++++++++++++++++++++++++++-
 hw/fpga/super6502.sv     | 37 +++++++++++++++++++++----------------
 2 files changed, 54 insertions(+), 17 deletions(-)

diff --git a/hw/fpga/sd_controller.sv b/hw/fpga/sd_controller.sv
index 4dacc9b..d96c5de 100644
--- a/hw/fpga/sd_controller.sv
+++ b/hw/fpga/sd_controller.sv
@@ -12,13 +12,30 @@ module sd_controller(
     output logic o_sd_cmd,
 
     input i_sd_data,
-    output logic o_sd_data
+    output logic o_sd_data,
+
+    output logic [7:0] data_out
 );
 
 logic [31:0] arg;
 logic [5:0] cmd;
 
 logic [47:0] rxcmd_buf;
+logic [31:0] rx_val;
+
+assign rx_val = rxcmd_buf[39:8];
+
+always_comb begin
+    data_out = 'x;
+
+    if (addr < 4'h4) begin
+        data_out = rx_val[8 * addr +: 8];
+    end else if (addr == 4'h4) begin
+        data_out = read_flag;
+    end
+end
+
+logic read_flag, next_read_flag;
 
 typedef enum bit [2:0] {IDLE, LOAD, CRC, TXCMD, RXCMD} macro_t;
 struct packed {
@@ -30,16 +47,25 @@ always_ff @(posedge clk) begin
     if (rst) begin
         state.macro <= IDLE;
         state.count <= '0;
+        read_flag <= '0;
     end else begin
         if (state.macro == TXCMD || state.macro == CRC) begin
             if (sd_clk) begin
                 state <= next_state;
             end
+        end else if (state.macro == RXCMD) begin
+            if (~sd_clk) begin
+                state <= next_state;
+            end
         end else begin
             state <= next_state;
         end
     end
 
+    if (sd_clk) begin
+        read_flag <= next_read_flag;
+    end
+
     if (cs & ~rw) begin
         if (addr < 4'h4) begin
             arg[8 * addr +: 8] <= data;
@@ -71,6 +97,7 @@ crc7 u_crc7(
 
 always_comb begin
     next_state = state;
+    next_read_flag = read_flag;
 
     case (state.macro)
         IDLE: begin
@@ -81,6 +108,10 @@ always_comb begin
             if (addr == 4'h4 & cs & ~rw) begin     // transmit if cpu writes to cmd
                 next_state.macro = LOAD;
             end
+
+            if (addr == 4'h4 & cs & rw) begin
+                next_read_flag = '0;
+            end
         end
 
         LOAD: begin
@@ -104,6 +135,7 @@ always_comb begin
             if (state.count < 47) begin
                 next_state.count = state.count + 6'b1;
             end else begin
+                next_read_flag = '1;
                 next_state.macro = IDLE;
                 next_state.count = '0;
             end
diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv
index 1e2009f..54bbdfe 100644
--- a/hw/fpga/super6502.sv
+++ b/hw/fpga/super6502.sv
@@ -73,6 +73,7 @@ logic [7:0] uart_data_out;
 logic [7:0] irq_data_out;
 logic [7:0] board_io_data_out;
 logic [7:0] mm_data_out;
+logic [7:0] sd_data_out;
 
 logic sdram_cs;
 logic rom_cs;
@@ -85,8 +86,8 @@ logic mm_cs2;
 logic sd_cs;
 
 cpu_clk cpu_clk(
-	.inclk0(clk_50),
-	.c0(clk)
+    .inclk0(clk_50),
+    .c0(clk)
 );
 
 always @(posedge clk) begin
@@ -106,16 +107,16 @@ logic [23:0] mm_addr;
 assign mm_addr = {mm_MO, cpu_addr[11:0]};
 
 memory_mapper memory_mapper(
-	.clk(clk),
+    .clk(clk),
     .rst(rst),
-	.rw(cpu_rwb),
-	.cs(mm_cs1),
-	.MM_cs(mm_cs2),
-	.RS(cpu_addr[3:0]),
-	.MA(cpu_addr[15:12]),
-	.data_in(cpu_data_in),
-	.data_out(mm_data_out),
-	.MO(mm_MO)
+    .rw(cpu_rwb),
+    .cs(mm_cs1),
+    .MM_cs(mm_cs2),
+    .RS(cpu_addr[3:0]),
+    .MA(cpu_addr[15:12]),
+    .data_in(cpu_data_in),
+    .data_out(mm_data_out),
+    .MO(mm_MO)
 );
 
 addr_decode decode(
@@ -126,8 +127,8 @@ addr_decode decode(
     .uart_cs(uart_cs),
     .irq_cs(irq_cs),
     .board_io_cs(board_io_cs),
-	.mm_cs1(mm_cs1),
-	.mm_cs2(mm_cs2),
+    .mm_cs1(mm_cs1),
+    .mm_cs2(mm_cs2),
     .sd_cs(sd_cs)
 );
 
@@ -143,8 +144,10 @@ always_comb begin
         cpu_data_out = irq_data_out;
     else if (board_io_cs)
         cpu_data_out = board_io_data_out;
-	else if (mm_cs1)
-		cpu_data_out = mm_data_out;
+    else if (mm_cs1)
+        cpu_data_out = mm_data_out;
+    else if (sd_cs)
+        cpu_data_out = sd_data_out;
     else
         cpu_data_out = 'x;
 end
@@ -231,7 +234,9 @@ sd_controller sd_controller(
     .o_sd_cmd(o_sd_cmd),
 
     .i_sd_data(i_sd_data),
-    .o_sd_data(o_sd_data)
+    .o_sd_data(o_sd_data),
+
+    .data_out(sd_data_out)
 );
 
 always_ff @(posedge clk_50) begin

From 9eaa6c49f9300e98674ec004c2aac81dc354a898 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sun, 10 Apr 2022 23:18:26 -0500
Subject: [PATCH 15/20] Add software support for sd response codes

Polls the sd controller until the read flag is set, at which point it
reads 32 bits of data from the controller.

long response codes (such as CID) are not supported in hw or sw.
---
 sw/main.c    | 59 +++++++++++++++++++++++++++++++++++++---------------
 sw/sd_card.h |  2 ++
 sw/sd_card.s | 25 +++++++++++++++++++++-
 3 files changed, 68 insertions(+), 18 deletions(-)

diff --git a/sw/main.c b/sw/main.c
index 81e6cd6..c20b850 100644
--- a/sw/main.c
+++ b/sw/main.c
@@ -7,13 +7,14 @@
 #include "sd_card.h"
 
 int main() {
-    int i;
-    uint8_t sw;
-    char s[16];
-    s[15] = 0;
+	int i;
+	uint8_t sw;
+	uint32_t resp;
+	char s[16];
+	s[15] = 0;
 
-    clrscr();
-    cprintf("Hello, world!\n");
+	clrscr();
+	cprintf("Hello, world!\n");
 
 	for (i = 0; i < 16; i++){
 		cprintf("Mapping %1xxxx to %2xxxx\n", i, i);
@@ -51,29 +52,53 @@ int main() {
 	// The RCA is hard coded for the one that I have on hand as responses
 	// are not implemented yet.
 	sd_card_command(0, 0);
+
 	sd_card_command(0x000001aa, 8);
+	sd_card_resp(&resp);
+	cprintf("CMD8: %lx\n", resp);
+
 	sd_card_command(0, 55);
 	sd_card_command(0x40180000, 41);
+	sd_card_resp(&resp);
+	cprintf("CMD41: %lx\n", resp);
+
 	sd_card_command(0, 55);
 	sd_card_command(0x40180000, 41);
+	sd_card_resp(&resp);
+	cprintf("CMD41: %lx\n", resp);
+
 	sd_card_command(0, 2);
+	sd_card_resp(&resp);
+	cprintf("CMD2: %lx\n", resp);
+
 	sd_card_command(0, 3);
+	sd_card_resp(&resp);
+	cprintf("CMD3: %lx\n", resp);
+
 	sd_card_command(0x59b40000, 7);
+	sd_card_resp(&resp);
+	cprintf("CMD7: %lx\n", resp);
+
 	sd_card_command(0x59b41000, 13);
+	sd_card_resp(&resp);
+	cprintf("CMD13: %lx\n", resp);
+
 	sd_card_command(0, 17);
+	sd_card_resp(&resp);
+	cprintf("CMD17: %lx\n", resp);
 
-    while (1) {
+	while (1) {
 
-        sw = sw_read();
-        led_set(sw);
+		sw = sw_read();
+		led_set(sw);
 
-        cscanf("%15s", s);
-        cprintf("\n");
-        for (i = 0; i < 16; i++)
-            cprintf("s[%d]=%c ", i, s[i]);
-        cprintf("\n");
-        cprintf("Read string: %s\n", s);
-    }
+		cscanf("%15s", s);
+		cprintf("\n");
+		for (i = 0; i < 16; i++)
+			cprintf("s[%d]=%c ", i, s[i]);
+		cprintf("\n");
+		cprintf("Read string: %s\n", s);
+	}
 
-    return 0;
+	return 0;
 }
diff --git a/sw/sd_card.h b/sw/sd_card.h
index 1cd59af..df44704 100644
--- a/sw/sd_card.h
+++ b/sw/sd_card.h
@@ -5,4 +5,6 @@
 
 void sd_card_command(uint32_t arg, uint8_t cmd);
 
+void sd_card_resp(uint32_t* resp);
+
 #endif
\ No newline at end of file
diff --git a/sw/sd_card.s b/sw/sd_card.s
index f6c6ed6..13a5e0c 100644
--- a/sw/sd_card.s
+++ b/sw/sd_card.s
@@ -1,8 +1,9 @@
 .include "io.inc65"
 
-.importzp sp, sreg
+.importzp sp, sreg, ptr1
 
 .export _sd_card_command
+.export _sd_card_resp
 
 .autoimport on
 
@@ -25,3 +26,25 @@ _sd_card_command:
     pla
     sta SD_CMD
     rts
+
+; void sd_card_resp(uint32_t* resp);
+_sd_card_resp:
+        phy
+        sta ptr1        ; store pointer
+        stx ptr1+1
+@1:     lda SD_CMD      ; wait for status flag
+        beq @1
+        lda SD_ARG
+        ldy #$0
+        sta (ptr1),y
+        lda SD_ARG+1
+        iny
+        sta (ptr1),y
+        lda SD_ARG+2
+        iny
+        sta (ptr1),y
+        lda SD_ARG+3
+        iny
+        sta (ptr1),y
+        ply
+        rts

From 51c348bc7cab8497010e047b9e38677ca68cd38b Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Mon, 11 Apr 2022 13:57:07 -0500
Subject: [PATCH 16/20] Increase sd card addr width by 1

Adds a new memory location for data accesses.
---
 hw/fpga/addr_decode.sv      | 2 +-
 hw/fpga/hvl/cs_testbench.sv | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/fpga/addr_decode.sv b/hw/fpga/addr_decode.sv
index c127697..bcfde85 100644
--- a/hw/fpga/addr_decode.sv
+++ b/hw/fpga/addr_decode.sv
@@ -18,7 +18,7 @@ assign hex_cs = addr >= 24'h007ff0 && addr < 24'h007ff4;
 assign uart_cs = addr >= 24'h007ff4 && addr < 24'h007ff6;
 assign board_io_cs = addr == 24'h007ff6;
 assign mm_cs2 = addr == 24'h007ff7;
-assign sd_cs = addr >= 24'h007ff8 && addr < 24'h007ffd;
+assign sd_cs = addr >= 24'h007ff8 && addr < 24'h007ffe;
 assign irq_cs  = addr == 24'h007fff;
 
 endmodule
diff --git a/hw/fpga/hvl/cs_testbench.sv b/hw/fpga/hvl/cs_testbench.sv
index 64dbe7f..3e69518 100644
--- a/hw/fpga/hvl/cs_testbench.sv
+++ b/hw/fpga/hvl/cs_testbench.sv
@@ -57,7 +57,7 @@ initial begin : TEST_VECTORS
             else
                 $error("Bad CS! addr=%4x should have mm_cs1!", addr);
         end
-        if (i >= 24'h007ff8 && i < 24'h007ffd) begin
+        if (i >= 24'h007ff8 && i < 24'h007ffe) begin
             assert(sd_cs == '1)
             else
             $error("Bad CS! addr=%4x should have sd_cs!", addr);

From 87d1457d9424a37f407125a5aba9f4270b7085ae Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Mon, 11 Apr 2022 13:57:56 -0500
Subject: [PATCH 17/20] Add logic to store and readback data from SD card

After a data read (e.g. CMD17) the data received from the SD card is
stored into a buffer which can be read back one byte at a time by the
CPU through address 5.

There is also a flag which is set when data is received. This can be
checked by reading the CMD register, which doubles as the status
register.
---
 hw/fpga/sd_controller.sv |  67 +++++++++++-
 hw/fpga/super6502.qsf    | 215 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 277 insertions(+), 5 deletions(-)

diff --git a/hw/fpga/sd_controller.sv b/hw/fpga/sd_controller.sv
index d96c5de..b166f18 100644
--- a/hw/fpga/sd_controller.sv
+++ b/hw/fpga/sd_controller.sv
@@ -23,6 +23,12 @@ logic [5:0] cmd;
 logic [47:0] rxcmd_buf;
 logic [31:0] rx_val;
 
+logic [7:0] rxdata_buf [512];
+logic [9:0] data_count;
+
+logic [15:0] data_crc;
+
+
 assign rx_val = rxcmd_buf[39:8];
 
 always_comb begin
@@ -31,29 +37,36 @@ always_comb begin
     if (addr < 4'h4) begin
         data_out = rx_val[8 * addr +: 8];
     end else if (addr == 4'h4) begin
-        data_out = read_flag;
+        data_out = {data_flag, read_flag};
+    end else if (addr == 4'h5) begin
+        data_out = rxdata_buf[data_count];
     end
 end
 
 logic read_flag, next_read_flag;
+logic data_flag, next_data_flag;
 
-typedef enum bit [2:0] {IDLE, LOAD, CRC, TXCMD, RXCMD} macro_t;
+typedef enum bit [2:0] {IDLE, LOAD, CRC, TXCMD, RXCMD, TXDATA, RXDATA, RXDCRC} macro_t;
 struct packed {
     macro_t macro;
-    logic [5:0] count;
+    logic [8:0] count;
+    logic [2:0] d_bit_count;
 } state, next_state;
 
 always_ff @(posedge clk) begin
     if (rst) begin
         state.macro <= IDLE;
         state.count <= '0;
+        state.d_bit_count <= '1;
         read_flag <= '0;
+        data_flag <= '0;
+        data_count <= '0;
     end else begin
         if (state.macro == TXCMD || state.macro == CRC) begin
             if (sd_clk) begin
                 state <= next_state;
             end
-        end else if (state.macro == RXCMD) begin
+        end else if (state.macro == RXCMD || state.macro == RXDATA || state.macro == RXDCRC) begin
             if (~sd_clk) begin
                 state <= next_state;
             end
@@ -64,6 +77,7 @@ always_ff @(posedge clk) begin
 
     if (sd_clk) begin
         read_flag <= next_read_flag;
+        data_flag <= next_data_flag;
     end
 
     if (cs & ~rw) begin
@@ -73,9 +87,23 @@ always_ff @(posedge clk) begin
             cmd <= data;
         end
     end
+
+    if (cs & addr == 4'h5 && sd_clk) begin
+        data_count <= data_count + 1;
+    end
+
     if (state.macro == RXCMD) begin
         rxcmd_buf[6'd46-state.count] <= i_sd_cmd;   //we probabily missed bit 47
     end
+
+    if (state.macro == RXDATA && ~sd_clk) begin
+        rxdata_buf[state.count][state.d_bit_count] <= i_sd_data;
+    end
+
+    if (state.macro == RXDCRC && ~sd_clk) begin
+        data_crc[4'd15-state.count] <= i_sd_data;
+    end
+
 end
 
 logic [6:0] crc;
@@ -98,6 +126,7 @@ crc7 u_crc7(
 always_comb begin
     next_state = state;
     next_read_flag = read_flag;
+    next_data_flag = data_flag;
 
     case (state.macro)
         IDLE: begin
@@ -105,6 +134,10 @@ always_comb begin
                 next_state.macro = RXCMD;
             end
 
+            if (~i_sd_data) begin
+                next_state.macro = RXDATA;
+            end
+
             if (addr == 4'h4 & cs & ~rw) begin     // transmit if cpu writes to cmd
                 next_state.macro = LOAD;
             end
@@ -112,6 +145,10 @@ always_comb begin
             if (addr == 4'h4 & cs & rw) begin
                 next_read_flag = '0;
             end
+
+            if (addr == 4'h5 & cs) begin
+                next_data_flag = '0;
+            end
         end
 
         LOAD: begin
@@ -140,6 +177,28 @@ always_comb begin
                 next_state.count = '0;
             end
         end
+
+        RXDATA: begin
+            if (state.count < 511 || (state.count == 511 && state.d_bit_count > 0)) begin
+                if (state.d_bit_count == 8'h0) begin
+                    next_state.count = state.count + 9'b1;
+                end
+                next_state.d_bit_count = state.d_bit_count - 8'h1;
+            end else begin
+                next_data_flag = '1;
+                next_state.macro = RXDCRC;
+                next_state.count = '0;
+            end
+        end
+
+        RXDCRC: begin
+            if (state.count < 16) begin
+                next_state.count = state.count + 9'b1;
+            end else begin
+                next_state.macro = IDLE;
+                next_state.count = '0;
+            end
+        end
     endcase
 end
 
diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf
index 191ee02..0267ca5 100644
--- a/hw/fpga/super6502.qsf
+++ b/hw/fpga/super6502.qsf
@@ -187,7 +187,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_rwb
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_sob
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_sync
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_50
-set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name ENABLE_SIGNALTAP ON
 set_global_assignment -name USE_SIGNALTAP_FILE output_files/sd.stp
 set_location_assignment PIN_F20 -to HEX4[6]
 set_location_assignment PIN_F19 -to HEX4[5]
@@ -400,4 +400,217 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[11]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[12]
 set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "cpu_clk:cpu_clk|c0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "sd_controller:sd_controller|addr[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "sd_controller:sd_controller|addr[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "sd_controller:sd_controller|addr[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "sd_controller:sd_controller|cs" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "sd_controller:sd_controller|addr[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "sd_controller:sd_controller|addr[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "sd_controller:sd_controller|addr[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "sd_controller:sd_controller|cs" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=8192" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=8192" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "sd_controller:sd_controller|data_count[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "sd_controller:sd_controller|data_count[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "sd_controller:sd_controller|data_count[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "sd_controller:sd_controller|data_count[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "sd_controller:sd_controller|data_count[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "sd_controller:sd_controller|data_count[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "sd_controller:sd_controller|data_count[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "sd_controller:sd_controller|data_count[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "sd_controller:sd_controller|data_count[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "sd_controller:sd_controller|data_count[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "sd_controller:sd_controller|data_flag" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "sd_controller:sd_controller|data_out[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "sd_controller:sd_controller|data_out[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "sd_controller:sd_controller|data_out[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "sd_controller:sd_controller|data_out[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "sd_controller:sd_controller|data_out[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "sd_controller:sd_controller|data_out[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "sd_controller:sd_controller|data_out[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "sd_controller:sd_controller|data_out[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "sd_controller:sd_controller|i_sd_cmd" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "sd_controller:sd_controller|i_sd_data" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "sd_controller:sd_controller|o_sd_cmd" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "sd_controller:sd_controller|o_sd_data" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "sd_controller:sd_controller|read_flag" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "sd_controller:sd_controller|rw" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "sd_controller:sd_controller|rxcmd_buf[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "sd_controller:sd_controller|rxcmd_buf[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "sd_controller:sd_controller|rxcmd_buf[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "sd_controller:sd_controller|rxcmd_buf[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "sd_controller:sd_controller|rxcmd_buf[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "sd_controller:sd_controller|rxcmd_buf[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "sd_controller:sd_controller|rxcmd_buf[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "sd_controller:sd_controller|rxcmd_buf[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "sd_controller:sd_controller|rxcmd_buf[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "sd_controller:sd_controller|rxcmd_buf[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "sd_controller:sd_controller|rxcmd_buf[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "sd_controller:sd_controller|rxcmd_buf[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "sd_controller:sd_controller|rxcmd_buf[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "sd_controller:sd_controller|rxcmd_buf[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "sd_controller:sd_controller|rxcmd_buf[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "sd_controller:sd_controller|rxcmd_buf[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "sd_controller:sd_controller|rxcmd_buf[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "sd_controller:sd_controller|rxcmd_buf[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "sd_controller:sd_controller|rxcmd_buf[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "sd_controller:sd_controller|rxcmd_buf[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "sd_controller:sd_controller|rxcmd_buf[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "sd_controller:sd_controller|rxcmd_buf[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "sd_controller:sd_controller|rxcmd_buf[32]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "sd_controller:sd_controller|rxcmd_buf[33]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "sd_controller:sd_controller|rxcmd_buf[34]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "sd_controller:sd_controller|rxcmd_buf[35]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "sd_controller:sd_controller|rxcmd_buf[36]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "sd_controller:sd_controller|rxcmd_buf[37]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "sd_controller:sd_controller|rxcmd_buf[38]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "sd_controller:sd_controller|rxcmd_buf[39]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "sd_controller:sd_controller|rxcmd_buf[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "sd_controller:sd_controller|rxcmd_buf[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "sd_controller:sd_controller|state.count[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "sd_controller:sd_controller|state.count[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "sd_controller:sd_controller|state.count[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "sd_controller:sd_controller|state.count[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "sd_controller:sd_controller|state.count[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "sd_controller:sd_controller|state.count[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "sd_controller:sd_controller|state.count[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "sd_controller:sd_controller|state.count[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "sd_controller:sd_controller|state.count[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "sd_controller:sd_controller|state.d_bit_count[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "sd_controller:sd_controller|state.d_bit_count[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "sd_controller:sd_controller|state.d_bit_count[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "sd_controller:sd_controller|state.macro[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "sd_controller:sd_controller|state.macro[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "sd_controller:sd_controller|state.macro[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "sd_controller:sd_controller|data_count[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "sd_controller:sd_controller|data_count[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "sd_controller:sd_controller|data_count[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "sd_controller:sd_controller|data_count[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "sd_controller:sd_controller|data_count[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "sd_controller:sd_controller|data_count[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "sd_controller:sd_controller|data_count[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "sd_controller:sd_controller|data_count[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "sd_controller:sd_controller|data_count[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "sd_controller:sd_controller|data_count[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "sd_controller:sd_controller|data_flag" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "sd_controller:sd_controller|data_out[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "sd_controller:sd_controller|data_out[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "sd_controller:sd_controller|data_out[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "sd_controller:sd_controller|data_out[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "sd_controller:sd_controller|data_out[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "sd_controller:sd_controller|data_out[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "sd_controller:sd_controller|data_out[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "sd_controller:sd_controller|data_out[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "sd_controller:sd_controller|i_sd_cmd" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "sd_controller:sd_controller|i_sd_data" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "sd_controller:sd_controller|o_sd_cmd" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "sd_controller:sd_controller|o_sd_data" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "sd_controller:sd_controller|read_flag" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "sd_controller:sd_controller|rw" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "sd_controller:sd_controller|rxcmd_buf[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "sd_controller:sd_controller|rxcmd_buf[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "sd_controller:sd_controller|rxcmd_buf[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "sd_controller:sd_controller|rxcmd_buf[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "sd_controller:sd_controller|rxcmd_buf[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "sd_controller:sd_controller|rxcmd_buf[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "sd_controller:sd_controller|rxcmd_buf[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "sd_controller:sd_controller|rxcmd_buf[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "sd_controller:sd_controller|rxcmd_buf[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "sd_controller:sd_controller|rxcmd_buf[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "sd_controller:sd_controller|rxcmd_buf[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "sd_controller:sd_controller|rxcmd_buf[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "sd_controller:sd_controller|rxcmd_buf[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "sd_controller:sd_controller|rxcmd_buf[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "sd_controller:sd_controller|rxcmd_buf[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "sd_controller:sd_controller|rxcmd_buf[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "sd_controller:sd_controller|rxcmd_buf[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "sd_controller:sd_controller|rxcmd_buf[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "sd_controller:sd_controller|rxcmd_buf[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "sd_controller:sd_controller|rxcmd_buf[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "sd_controller:sd_controller|rxcmd_buf[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "sd_controller:sd_controller|rxcmd_buf[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "sd_controller:sd_controller|rxcmd_buf[32]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "sd_controller:sd_controller|rxcmd_buf[33]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "sd_controller:sd_controller|rxcmd_buf[34]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "sd_controller:sd_controller|rxcmd_buf[35]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "sd_controller:sd_controller|rxcmd_buf[36]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "sd_controller:sd_controller|rxcmd_buf[37]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "sd_controller:sd_controller|rxcmd_buf[38]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "sd_controller:sd_controller|rxcmd_buf[39]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "sd_controller:sd_controller|rxcmd_buf[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "sd_controller:sd_controller|rxcmd_buf[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "sd_controller:sd_controller|state.count[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "sd_controller:sd_controller|state.count[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "sd_controller:sd_controller|state.count[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "sd_controller:sd_controller|state.count[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "sd_controller:sd_controller|state.count[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "sd_controller:sd_controller|state.count[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "sd_controller:sd_controller|state.count[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "sd_controller:sd_controller|state.count[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "sd_controller:sd_controller|state.count[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "sd_controller:sd_controller|state.d_bit_count[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "sd_controller:sd_controller|state.d_bit_count[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "sd_controller:sd_controller|state.d_bit_count[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "sd_controller:sd_controller|state.macro[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "sd_controller:sd_controller|state.macro[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "sd_controller:sd_controller|state.macro[2]" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=76" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=76" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=76" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=255" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_global_assignment -name SLD_FILE db/sd_auto_stripped.stp
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file

From f4e16c0c12fb65bbe4160bb2558260547eafd987 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Mon, 11 Apr 2022 14:03:42 -0500
Subject: [PATCH 18/20] Add software interface for reading SD card data

Adds functions to wait for data to be read, and to read data form the sd
card controller.
---
 sw/io.inc65  |  1 +
 sw/main.c    | 10 ++++++++++
 sw/sd_card.h |  2 ++
 sw/sd_card.s | 16 ++++++++++++++++
 4 files changed, 29 insertions(+)

diff --git a/sw/io.inc65 b/sw/io.inc65
index 3586e7c..bad732c 100644
--- a/sw/io.inc65
+++ b/sw/io.inc65
@@ -13,5 +13,6 @@ MM_DATA		= $7fe0
 
 SD_ARG      = $7ff8
 SD_CMD      = $7ffc
+SD_DATA     = $7ffd
 
 IRQ_STATUS  = $7fff
diff --git a/sw/main.c b/sw/main.c
index c20b850..dc7182b 100644
--- a/sw/main.c
+++ b/sw/main.c
@@ -87,6 +87,16 @@ int main() {
 	sd_card_resp(&resp);
 	cprintf("CMD17: %lx\n", resp);
 
+
+	while(sw_read());
+
+	sd_card_wait_for_data();
+
+	cprintf("Read data: \n");
+	for (i = 0; i < 512; i++){
+		cprintf("%c", sd_card_read_byte());
+	}
+
 	while (1) {
 
 		sw = sw_read();
diff --git a/sw/sd_card.h b/sw/sd_card.h
index df44704..8dbe972 100644
--- a/sw/sd_card.h
+++ b/sw/sd_card.h
@@ -6,5 +6,7 @@
 void sd_card_command(uint32_t arg, uint8_t cmd);
 
 void sd_card_resp(uint32_t* resp);
+uint8_t sd_card_read_byte();
+void sd_card_wait_for_data();
 
 #endif
\ No newline at end of file
diff --git a/sw/sd_card.s b/sw/sd_card.s
index 13a5e0c..fe4f4e2 100644
--- a/sw/sd_card.s
+++ b/sw/sd_card.s
@@ -4,6 +4,8 @@
 
 .export _sd_card_command
 .export _sd_card_resp
+.export _sd_card_read_byte
+.export _sd_card_wait_for_data
 
 .autoimport on
 
@@ -33,6 +35,7 @@ _sd_card_resp:
         sta ptr1        ; store pointer
         stx ptr1+1
 @1:     lda SD_CMD      ; wait for status flag
+        and #$01
         beq @1
         lda SD_ARG
         ldy #$0
@@ -48,3 +51,16 @@ _sd_card_resp:
         sta (ptr1),y
         ply
         rts
+
+_sd_card_read_byte:
+        lda SD_DATA
+        ldx #$00
+        rts
+
+_sd_card_wait_for_data:
+        pha
+@1:     lda SD_CMD      ; wait for status flag
+        and #$02
+        beq @1
+        pla
+        rts
\ No newline at end of file

From 68a422d5e32d03695c9603c6aa8b179457bc6284 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Mon, 11 Apr 2022 16:03:50 -0500
Subject: [PATCH 19/20] Disable signal tap

---
 hw/fpga/super6502.qsf | 215 +-----------------------------------------
 1 file changed, 1 insertion(+), 214 deletions(-)

diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf
index 0267ca5..191ee02 100644
--- a/hw/fpga/super6502.qsf
+++ b/hw/fpga/super6502.qsf
@@ -187,7 +187,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_rwb
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_sob
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_sync
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_50
-set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name ENABLE_SIGNALTAP OFF
 set_global_assignment -name USE_SIGNALTAP_FILE output_files/sd.stp
 set_location_assignment PIN_F20 -to HEX4[6]
 set_location_assignment PIN_F19 -to HEX4[5]
@@ -400,217 +400,4 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[11]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[12]
 set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp
-set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "cpu_clk:cpu_clk|c0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "sd_controller:sd_controller|addr[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "sd_controller:sd_controller|addr[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "sd_controller:sd_controller|addr[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "sd_controller:sd_controller|cs" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "sd_controller:sd_controller|addr[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "sd_controller:sd_controller|addr[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "sd_controller:sd_controller|addr[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "sd_controller:sd_controller|cs" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=8192" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=8192" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "sd_controller:sd_controller|data_count[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "sd_controller:sd_controller|data_count[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "sd_controller:sd_controller|data_count[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "sd_controller:sd_controller|data_count[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "sd_controller:sd_controller|data_count[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "sd_controller:sd_controller|data_count[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "sd_controller:sd_controller|data_count[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "sd_controller:sd_controller|data_count[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "sd_controller:sd_controller|data_count[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "sd_controller:sd_controller|data_count[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "sd_controller:sd_controller|data_flag" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "sd_controller:sd_controller|data_out[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "sd_controller:sd_controller|data_out[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "sd_controller:sd_controller|data_out[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "sd_controller:sd_controller|data_out[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "sd_controller:sd_controller|data_out[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "sd_controller:sd_controller|data_out[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "sd_controller:sd_controller|data_out[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "sd_controller:sd_controller|data_out[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "sd_controller:sd_controller|i_sd_cmd" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "sd_controller:sd_controller|i_sd_data" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "sd_controller:sd_controller|o_sd_cmd" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "sd_controller:sd_controller|o_sd_data" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "sd_controller:sd_controller|read_flag" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "sd_controller:sd_controller|rw" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "sd_controller:sd_controller|rxcmd_buf[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "sd_controller:sd_controller|rxcmd_buf[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "sd_controller:sd_controller|rxcmd_buf[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "sd_controller:sd_controller|rxcmd_buf[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "sd_controller:sd_controller|rxcmd_buf[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "sd_controller:sd_controller|rxcmd_buf[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "sd_controller:sd_controller|rxcmd_buf[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "sd_controller:sd_controller|rxcmd_buf[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "sd_controller:sd_controller|rxcmd_buf[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "sd_controller:sd_controller|rxcmd_buf[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "sd_controller:sd_controller|rxcmd_buf[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "sd_controller:sd_controller|rxcmd_buf[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "sd_controller:sd_controller|rxcmd_buf[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "sd_controller:sd_controller|rxcmd_buf[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "sd_controller:sd_controller|rxcmd_buf[24]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "sd_controller:sd_controller|rxcmd_buf[25]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "sd_controller:sd_controller|rxcmd_buf[26]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "sd_controller:sd_controller|rxcmd_buf[27]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "sd_controller:sd_controller|rxcmd_buf[28]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "sd_controller:sd_controller|rxcmd_buf[29]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "sd_controller:sd_controller|rxcmd_buf[30]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "sd_controller:sd_controller|rxcmd_buf[31]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "sd_controller:sd_controller|rxcmd_buf[32]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "sd_controller:sd_controller|rxcmd_buf[33]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "sd_controller:sd_controller|rxcmd_buf[34]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "sd_controller:sd_controller|rxcmd_buf[35]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "sd_controller:sd_controller|rxcmd_buf[36]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "sd_controller:sd_controller|rxcmd_buf[37]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "sd_controller:sd_controller|rxcmd_buf[38]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "sd_controller:sd_controller|rxcmd_buf[39]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "sd_controller:sd_controller|rxcmd_buf[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "sd_controller:sd_controller|rxcmd_buf[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "sd_controller:sd_controller|state.count[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "sd_controller:sd_controller|state.count[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "sd_controller:sd_controller|state.count[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "sd_controller:sd_controller|state.count[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "sd_controller:sd_controller|state.count[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "sd_controller:sd_controller|state.count[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "sd_controller:sd_controller|state.count[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "sd_controller:sd_controller|state.count[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "sd_controller:sd_controller|state.count[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "sd_controller:sd_controller|state.d_bit_count[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "sd_controller:sd_controller|state.d_bit_count[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "sd_controller:sd_controller|state.d_bit_count[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "sd_controller:sd_controller|state.macro[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "sd_controller:sd_controller|state.macro[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "sd_controller:sd_controller|state.macro[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "sd_controller:sd_controller|data_count[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "sd_controller:sd_controller|data_count[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "sd_controller:sd_controller|data_count[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "sd_controller:sd_controller|data_count[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "sd_controller:sd_controller|data_count[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "sd_controller:sd_controller|data_count[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "sd_controller:sd_controller|data_count[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "sd_controller:sd_controller|data_count[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "sd_controller:sd_controller|data_count[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "sd_controller:sd_controller|data_count[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "sd_controller:sd_controller|data_flag" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "sd_controller:sd_controller|data_out[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "sd_controller:sd_controller|data_out[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "sd_controller:sd_controller|data_out[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "sd_controller:sd_controller|data_out[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "sd_controller:sd_controller|data_out[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "sd_controller:sd_controller|data_out[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "sd_controller:sd_controller|data_out[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "sd_controller:sd_controller|data_out[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "sd_controller:sd_controller|i_sd_cmd" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "sd_controller:sd_controller|i_sd_data" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "sd_controller:sd_controller|o_sd_cmd" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "sd_controller:sd_controller|o_sd_data" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "sd_controller:sd_controller|read_flag" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "sd_controller:sd_controller|rw" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "sd_controller:sd_controller|rxcmd_buf[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "sd_controller:sd_controller|rxcmd_buf[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "sd_controller:sd_controller|rxcmd_buf[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "sd_controller:sd_controller|rxcmd_buf[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "sd_controller:sd_controller|rxcmd_buf[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "sd_controller:sd_controller|rxcmd_buf[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "sd_controller:sd_controller|rxcmd_buf[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "sd_controller:sd_controller|rxcmd_buf[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "sd_controller:sd_controller|rxcmd_buf[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "sd_controller:sd_controller|rxcmd_buf[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "sd_controller:sd_controller|rxcmd_buf[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "sd_controller:sd_controller|rxcmd_buf[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "sd_controller:sd_controller|rxcmd_buf[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "sd_controller:sd_controller|rxcmd_buf[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "sd_controller:sd_controller|rxcmd_buf[24]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "sd_controller:sd_controller|rxcmd_buf[25]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "sd_controller:sd_controller|rxcmd_buf[26]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "sd_controller:sd_controller|rxcmd_buf[27]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "sd_controller:sd_controller|rxcmd_buf[28]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "sd_controller:sd_controller|rxcmd_buf[29]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "sd_controller:sd_controller|rxcmd_buf[30]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "sd_controller:sd_controller|rxcmd_buf[31]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "sd_controller:sd_controller|rxcmd_buf[32]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "sd_controller:sd_controller|rxcmd_buf[33]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "sd_controller:sd_controller|rxcmd_buf[34]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "sd_controller:sd_controller|rxcmd_buf[35]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "sd_controller:sd_controller|rxcmd_buf[36]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "sd_controller:sd_controller|rxcmd_buf[37]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "sd_controller:sd_controller|rxcmd_buf[38]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "sd_controller:sd_controller|rxcmd_buf[39]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "sd_controller:sd_controller|rxcmd_buf[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "sd_controller:sd_controller|rxcmd_buf[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "sd_controller:sd_controller|state.count[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "sd_controller:sd_controller|state.count[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "sd_controller:sd_controller|state.count[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "sd_controller:sd_controller|state.count[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "sd_controller:sd_controller|state.count[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "sd_controller:sd_controller|state.count[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "sd_controller:sd_controller|state.count[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "sd_controller:sd_controller|state.count[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "sd_controller:sd_controller|state.count[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "sd_controller:sd_controller|state.d_bit_count[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "sd_controller:sd_controller|state.d_bit_count[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "sd_controller:sd_controller|state.d_bit_count[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "sd_controller:sd_controller|state.macro[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "sd_controller:sd_controller|state.macro[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "sd_controller:sd_controller|state.macro[2]" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=76" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=76" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=76" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=255" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
-set_global_assignment -name SLD_FILE db/sd_auto_stripped.stp
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file

From c9269b2fb853e4db9cbd4aa62c9817b0d7cf603d Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Mon, 11 Apr 2022 16:13:38 -0500
Subject: [PATCH 20/20] Fix some warnings

Adds some missing cases, length specifiers.
---
 hw/fpga/sd_controller.sv | 13 ++++++++++---
 hw/fpga/super6502.sv     |  2 +-
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/hw/fpga/sd_controller.sv b/hw/fpga/sd_controller.sv
index b166f18..b8f864f 100644
--- a/hw/fpga/sd_controller.sv
+++ b/hw/fpga/sd_controller.sv
@@ -84,12 +84,12 @@ always_ff @(posedge clk) begin
         if (addr < 4'h4) begin
             arg[8 * addr +: 8] <= data;
         end else if (addr == 4'h4) begin
-            cmd <= data;
+            cmd <= data[6:0];
         end
     end
 
     if (cs & addr == 4'h5 && sd_clk) begin
-        data_count <= data_count + 1;
+        data_count <= data_count + 9'b1;
     end
 
     if (state.macro == RXCMD) begin
@@ -183,7 +183,7 @@ always_comb begin
                 if (state.d_bit_count == 8'h0) begin
                     next_state.count = state.count + 9'b1;
                 end
-                next_state.d_bit_count = state.d_bit_count - 8'h1;
+                next_state.d_bit_count = state.d_bit_count - 3'h1;
             end else begin
                 next_data_flag = '1;
                 next_state.macro = RXDCRC;
@@ -199,6 +199,11 @@ always_comb begin
                 next_state.count = '0;
             end
         end
+
+        default: begin
+                next_state.macro = IDLE;
+                next_state.count = '0;
+        end
     endcase
 end
 
@@ -220,6 +225,8 @@ always_comb begin
         end
 
         RXCMD:;
+
+        default:;
     endcase
 end
 
diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv
index 54bbdfe..6cb2502 100644
--- a/hw/fpga/super6502.sv
+++ b/hw/fpga/super6502.sv
@@ -29,7 +29,7 @@ module super6502(
     input                   [7:0] SW,
     output  logic           [7:0] LED,
 
-    inout   logic [15: 0]   ARDUINO_IO,
+    inout   logic [15: 2]   ARDUINO_IO,
 
     ///////// SDRAM /////////
     output             DRAM_CLK,