From 195367e1c03cb65e72208a0b4cbf7d49fc2e9c16 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Tue, 21 Nov 2023 20:37:55 -0800
Subject: [PATCH] try needs

---
 .gitlab-ci.yml | 40 ++++++++++++++++++++++++++++++++--------
 1 file changed, 32 insertions(+), 8 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index e1194ce..2f670bf 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -43,6 +43,9 @@ build bios:
   tags:
     - linux
   stage: build_sw
+  needs:
+    - job: build toolchain
+      artifacts: true
   artifacts:
     paths:
       - hw/efinix_fpga/init_hex.mem
@@ -50,27 +53,27 @@ build bios:
     - source init_env.sh
     - cd sw/
     - make bios
-  dependencies:
-    - build toolchain
 
 build kernel:
   tags:
     - linux
   stage: build_sw
+  needs:
+    - job: build toolchain
+      artifacts: true
   script:
     - source init_env.sh
     - cd sw/
     - make kernel
-  dependencies:
-    - build toolchain
 
 build fpga:       # This job runs in the build stage, which runs first.
   tags:
     - efinity
     - linux
   stage: build_hw
-  dependencies:
-    - build bios
+  needs:
+    - job: build bios
+      artifacts: true
   script:
     - source init_env.sh
     - cd hw/efinix_fpga
@@ -92,14 +95,20 @@ full sim:
     - cd hw/efinix_fpga/simulation
     - make clean
     - TEST_PROGRAM=$REPO_TOP/sw/bios/bios.hex TEST_FOLDER=$REPO_TOP/sw/bios make full_sim
-  dependencies:
-    - build toolchain
+  needs:
+    - job: build bios
+      artifacts: true
+    - job: build kernel
+      artifacts: true
 
 mapper sim:
   tags:
     - linux
     - iverilog
   stage: simulate
+  needs:
+    - job: build toolchain
+      artifacts: true
   artifacts:
     paths:
       - hw/efinix_fpga/simulation/mapper_tb.vcd
@@ -115,6 +124,9 @@ mapper_code sim:
     - linux
     - iverilog
   stage: simulate
+  needs:
+    - job: build toolchain
+      artifacts: true
   artifacts:
     paths:
       - hw/efinix_fpga/simulation/mapper_code_tb.vcd
@@ -130,6 +142,9 @@ interrupt_controller sim:
     - linux
     - iverilog
   stage: simulate
+  needs:
+    - job: build toolchain
+      artifacts: true
   artifacts:
     paths:
       - hw/efinix_fpga/simulation/interrupt_controller.vcd
@@ -145,6 +160,9 @@ interrupt_controller_code sim:
     - linux
     - iverilog
   stage: simulate
+  needs:
+    - job: build toolchain
+      artifacts: true
   artifacts:
     paths:
       - hw/efinix_fpga/simulation/interrupt_controller_code.vcd
@@ -160,6 +178,9 @@ rtc_code sim:
     - linux
     - iverilog
   stage: simulate
+  needs:
+    - job: build toolchain
+      artifacts: true
   artifacts:
     paths:
       - hw/efinix_fpga/simulation/interrupt_controller_code.vcd
@@ -175,6 +196,9 @@ devices_setup_code sim:
     - linux
     - iverilog
   stage: simulate
+  needs:
+    - job: build toolchain
+      artifacts: true
   script:
     - source init_env.sh
     - cd hw/efinix_fpga/simulation