diff --git a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv index e91d6aa..709cd33 100644 --- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv +++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv @@ -193,23 +193,23 @@ logic sd_controller_dma_RREADY; logic [DATA_WIDTH-1:0] sd_controller_dma_RDATA; logic [1:0] sd_controller_dma_RRESP; -logic ntw_AWVALID; -logic ntw_AWREADY; -logic [ADDR_WIDTH-1:0] ntw_AWADDR; -logic ntw_WVALID; -logic ntw_WREADY; -logic [DATA_WIDTH-1:0] ntw_WDATA; -logic [DATA_WIDTH/8-1:0] ntw_WSTRB; -logic ntw_BVALID; -logic ntw_BREADY; -logic [1:0] ntw_BRESP; -logic ntw_ARVALID; -logic ntw_ARREADY; -logic [ADDR_WIDTH-1:0] ntw_ARADDR; -logic ntw_RVALID; -logic ntw_RREADY; -logic [DATA_WIDTH-1:0] ntw_RDATA; -logic [1:0] ntw_RRESP; +logic ntw_reg_AWVALID; +logic ntw_reg_AWREADY; +logic [ADDR_WIDTH-1:0] ntw_reg_AWADDR; +logic ntw_reg_WVALID; +logic ntw_reg_WREADY; +logic [DATA_WIDTH-1:0] ntw_reg_WDATA; +logic [DATA_WIDTH/8-1:0] ntw_reg_WSTRB; +logic ntw_reg_BVALID; +logic ntw_reg_BREADY; +logic [1:0] ntw_reg_BRESP; +logic ntw_reg_ARVALID; +logic ntw_reg_ARREADY; +logic [ADDR_WIDTH-1:0] ntw_reg_ARADDR; +logic ntw_reg_RVALID; +logic ntw_reg_RREADY; +logic [DATA_WIDTH-1:0] ntw_reg_RDATA; +logic [1:0] ntw_reg_RRESP; cpu_wrapper u_cpu_wrapper_0( @@ -287,23 +287,23 @@ axilxbar #( .S_AXI_BRESP ({cpu0_BRESP, sd_controller_dma_BRESP }), .S_AXI_BVALID ({cpu0_BVALID, sd_controller_dma_BVALID }), .S_AXI_BREADY ({cpu0_BREADY, sd_controller_dma_BREADY }), - .M_AXI_ARADDR ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_ctrl_ARADDR, ntw_ARADDR }), - .M_AXI_ARVALID ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_ctrl_ARVALID, ntw_ARVALID }), - .M_AXI_ARREADY ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_ctrl_ARREADY, ntw_ARREADY }), - .M_AXI_RDATA ({ram_rdata, rom_rdata, sdram_RDATA, sd_controller_ctrl_RDATA, ntw_RDATA }), - .M_AXI_RRESP ({ram_rresp, rom_rresp, sdram_RRESP, sd_controller_ctrl_RRESP, ntw_RRESP }), - .M_AXI_RVALID ({ram_rvalid, rom_rvalid, sdram_RVALID, sd_controller_ctrl_RVALID, ntw_RVALID }), - .M_AXI_RREADY ({ram_rready, rom_rready, sdram_RREADY, sd_controller_ctrl_RREADY, ntw_RREADY }), - .M_AXI_AWADDR ({ram_awaddr, rom_awaddr, sdram_AWADDR, sd_controller_ctrl_AWADDR, ntw_AWADDR }), - .M_AXI_AWVALID ({ram_awvalid, rom_awvalid, sdram_AWVALID, sd_controller_ctrl_AWVALID, ntw_AWVALID }), - .M_AXI_AWREADY ({ram_awready, rom_awready, sdram_AWREADY, sd_controller_ctrl_AWREADY, ntw_AWREADY }), - .M_AXI_WDATA ({ram_wdata, rom_wdata, sdram_WDATA, sd_controller_ctrl_WDATA, ntw_WDATA }), - .M_AXI_WVALID ({ram_wvalid, rom_wvalid, sdram_WVALID, sd_controller_ctrl_WVALID, ntw_WVALID }), - .M_AXI_WREADY ({ram_wready, rom_wready, sdram_WREADY, sd_controller_ctrl_WREADY, ntw_WREADY }), - .M_AXI_WSTRB ({ram_wstrb, rom_wstrb, sdram_WSTRB, sd_controller_ctrl_WSTRB, ntw_WSTRB }), - .M_AXI_BRESP ({ram_bresp, rom_bresp, sdram_BRESP, sd_controller_ctrl_BRESP, ntw_BRESP }), - .M_AXI_BVALID ({ram_bvalid, rom_bvalid, sdram_BVALID, sd_controller_ctrl_BVALID, ntw_BVALID }), - .M_AXI_BREADY ({ram_bready, rom_bready, sdram_BREADY, sd_controller_ctrl_BREADY, ntw_BREADY }) + .M_AXI_ARADDR ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_ctrl_ARADDR, ntw_reg_ARADDR }), + .M_AXI_ARVALID ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_ctrl_ARVALID, ntw_reg_ARVALID }), + .M_AXI_ARREADY ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_ctrl_ARREADY, ntw_reg_ARREADY }), + .M_AXI_RDATA ({ram_rdata, rom_rdata, sdram_RDATA, sd_controller_ctrl_RDATA, ntw_reg_RDATA }), + .M_AXI_RRESP ({ram_rresp, rom_rresp, sdram_RRESP, sd_controller_ctrl_RRESP, ntw_reg_RRESP }), + .M_AXI_RVALID ({ram_rvalid, rom_rvalid, sdram_RVALID, sd_controller_ctrl_RVALID, ntw_reg_RVALID }), + .M_AXI_RREADY ({ram_rready, rom_rready, sdram_RREADY, sd_controller_ctrl_RREADY, ntw_reg_RREADY }), + .M_AXI_AWADDR ({ram_awaddr, rom_awaddr, sdram_AWADDR, sd_controller_ctrl_AWADDR, ntw_reg_AWADDR }), + .M_AXI_AWVALID ({ram_awvalid, rom_awvalid, sdram_AWVALID, sd_controller_ctrl_AWVALID, ntw_reg_AWVALID }), + .M_AXI_AWREADY ({ram_awready, rom_awready, sdram_AWREADY, sd_controller_ctrl_AWREADY, ntw_reg_AWREADY }), + .M_AXI_WDATA ({ram_wdata, rom_wdata, sdram_WDATA, sd_controller_ctrl_WDATA, ntw_reg_WDATA }), + .M_AXI_WVALID ({ram_wvalid, rom_wvalid, sdram_WVALID, sd_controller_ctrl_WVALID, ntw_reg_WVALID }), + .M_AXI_WREADY ({ram_wready, rom_wready, sdram_WREADY, sd_controller_ctrl_WREADY, ntw_reg_WREADY }), + .M_AXI_WSTRB ({ram_wstrb, rom_wstrb, sdram_WSTRB, sd_controller_ctrl_WSTRB, ntw_reg_WSTRB }), + .M_AXI_BRESP ({ram_bresp, rom_bresp, sdram_BRESP, sd_controller_ctrl_BRESP, ntw_reg_BRESP }), + .M_AXI_BVALID ({ram_bvalid, rom_bvalid, sdram_BVALID, sd_controller_ctrl_BVALID, ntw_reg_BVALID }), + .M_AXI_BREADY ({ram_bready, rom_bready, sdram_BREADY, sd_controller_ctrl_BREADY, ntw_reg_BREADY }) ); @@ -504,30 +504,30 @@ sd_controller_wrapper #( ); network_processor #( - .NUM_TCP(8) + .NUM_TCP(8) ) u_network_processor ( .i_clk (i_sysclk), .i_rst (~master_resetn), - .s_axil_awready (ntw_AWREADY), - .s_axil_awvalid (ntw_AWVALID), - .s_axil_awaddr (ntw_AWADDR), - .s_axil_awprot (ntw_AWPROT), - .s_axil_wready (ntw_WREADY), - .s_axil_wvalid (ntw_WVALID), - .s_axil_wdata (ntw_WDATA), - .s_axil_wstrb (ntw_WSTRB), - .s_axil_bready (ntw_BREADY), - .s_axil_bvalid (ntw_BVALID), - .s_axil_bresp (ntw_BRESP), - .s_axil_arready (ntw_ARREADY), - .s_axil_arvalid (ntw_ARVALID), - .s_axil_araddr (ntw_ARADDR), - .s_axil_arprot (ntw_ARPROT), - .s_axil_rready (ntw_RREADY), - .s_axil_rvalid (ntw_RVALID), - .s_axil_rdata (ntw_RDATA), - .s_axil_rresp (ntw_RRESP) + .s_reg_axil_awready (ntw_reg_AWREADY), + .s_reg_axil_awvalid (ntw_reg_AWVALID), + .s_reg_axil_awaddr (ntw_reg_AWADDR), + .s_reg_axil_awprot (ntw_reg_AWPROT), + .s_reg_axil_wready (ntw_reg_WREADY), + .s_reg_axil_wvalid (ntw_reg_WVALID), + .s_reg_axil_wdata (ntw_reg_WDATA), + .s_reg_axil_wstrb (ntw_reg_WSTRB), + .s_reg_axil_bready (ntw_reg_BREADY), + .s_reg_axil_bvalid (ntw_reg_BVALID), + .s_reg_axil_bresp (ntw_reg_BRESP), + .s_reg_axil_arready (ntw_reg_ARREADY), + .s_reg_axil_arvalid (ntw_reg_ARVALID), + .s_reg_axil_araddr (ntw_reg_ARADDR), + .s_reg_axil_arprot (ntw_reg_ARPROT), + .s_reg_axil_rready (ntw_reg_RREADY), + .s_reg_axil_rvalid (ntw_reg_RVALID), + .s_reg_axil_rdata (ntw_reg_RDATA), + .s_reg_axil_rresp (ntw_reg_RRESP) ); endmodule diff --git a/hw/super6502_fpga/src/sub/network_processor/doc/tcp.drawio b/hw/super6502_fpga/src/sub/network_processor/doc/tcp.drawio index 2db5777..753846b 100644 --- a/hw/super6502_fpga/src/sub/network_processor/doc/tcp.drawio +++ b/hw/super6502_fpga/src/sub/network_processor/doc/tcp.drawio @@ -1,21 +1,21 @@ - + - + - + - + - + - + @@ -24,97 +24,97 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -123,97 +123,97 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -222,77 +222,77 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -313,7 +313,7 @@ - + @@ -372,60 +372,60 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -434,12 +434,12 @@ - + - + @@ -501,37 +501,37 @@ - + - + - + - + - + - + - + @@ -539,49 +539,49 @@ - + - + - + - + - + - + - + - + diff --git a/hw/super6502_fpga/src/sub/network_processor/sources.list b/hw/super6502_fpga/src/sub/network_processor/sources.list index 9571989..10d5670 100644 --- a/hw/super6502_fpga/src/sub/network_processor/sources.list +++ b/hw/super6502_fpga/src/sub/network_processor/sources.list @@ -4,4 +4,5 @@ src/regs/tcp_top_regfile_pkg.sv src/regs/tcp_top_regfile.sv src/network_processor.sv src/tcp_state_manager.sv -src/tcp_stream.sv \ No newline at end of file +src/tcp_stream.sv +src/tcp.sv \ No newline at end of file diff --git a/hw/super6502_fpga/src/sub/network_processor/src/network_processor.sv b/hw/super6502_fpga/src/sub/network_processor/src/network_processor.sv index cec4160..40d38d4 100644 --- a/hw/super6502_fpga/src/sub/network_processor/src/network_processor.sv +++ b/hw/super6502_fpga/src/sub/network_processor/src/network_processor.sv @@ -4,95 +4,57 @@ module network_processor #( input i_clk, input i_rst, - // our crossbar is all axi, so having this be apb means - // we have to convert it anyway - output logic s_axil_awready, - input wire s_axil_awvalid, - input wire [8:0] s_axil_awaddr, - input wire [2:0] s_axil_awprot, - output logic s_axil_wready, - input wire s_axil_wvalid, - input wire [31:0] s_axil_wdata, - input wire [3:0]s_axil_wstrb, - input wire s_axil_bready, - output logic s_axil_bvalid, - output logic [1:0] s_axil_bresp, - output logic s_axil_arready, - input wire s_axil_arvalid, - input wire [8:0] s_axil_araddr, - input wire [2:0] s_axil_arprot, - input wire s_axil_rready, - output logic s_axil_rvalid, - output logic [31:0] s_axil_rdata, - output logic [1:0] s_axil_rresp + output logic s_reg_axil_awready, + input wire s_reg_axil_awvalid, + input wire [8:0] s_reg_axil_awaddr, + input wire [2:0] s_reg_axil_awprot, + output logic s_reg_axil_wready, + input wire s_reg_axil_wvalid, + input wire [31:0] s_reg_axil_wdata, + input wire [3:0] s_reg_axil_wstrb, + input wire s_reg_axil_bready, + output logic s_reg_axil_bvalid, + output logic [1:0] s_reg_axil_bresp, + output logic s_reg_axil_arready, + input wire s_reg_axil_arvalid, + input wire [8:0] s_reg_axil_araddr, + input wire [2:0] s_reg_axil_arprot, + input wire s_reg_axil_rready, + output logic s_reg_axil_rvalid, + output logic [31:0] s_reg_axil_rdata, + output logic [1:0] s_reg_axil_rresp ); tcp_top_regfile_pkg::tcp_top_regfile__in_t tcp_hwif_in; tcp_top_regfile_pkg::tcp_top_regfile__out_t tcp_hwif_out; -tcp_top_regfile u_tcp_top_regfile ( - .clk (i_clk), - .rst (i_rst), +tcp #( + .NUM_TCP(NUM_TCP) +) tcp ( + .i_clk (i_clk), + .i_rst (i_rst), - .s_axil_awready (s_axil_awready), - .s_axil_awvalid (s_axil_awvalid), - .s_axil_awaddr (s_axil_awaddr), - .s_axil_awprot (s_axil_awprot), - .s_axil_wready (s_axil_wready), - .s_axil_wvalid (s_axil_wvalid), - .s_axil_wdata (s_axil_wdata), - .s_axil_wstrb (s_axil_wstrb), - .s_axil_bready (s_axil_bready), - .s_axil_bvalid (s_axil_bvalid), - .s_axil_bresp (s_axil_bresp), - .s_axil_arready (s_axil_arready), - .s_axil_arvalid (s_axil_arvalid), - .s_axil_araddr (s_axil_araddr), - .s_axil_arprot (s_axil_arprot), - .s_axil_rready (s_axil_rready), - .s_axil_rvalid (s_axil_rvalid), - .s_axil_rdata (s_axil_rdata), - .s_axil_rresp (s_axil_rresp), - - .hwif_in (tcp_hwif_in), - .hwif_out (tcp_hwif_out) + .s_reg_axil_awready (s_reg_axil_awready), + .s_reg_axil_awvalid (s_reg_axil_awvalid), + .s_reg_axil_awaddr (s_reg_axil_awaddr), + .s_reg_axil_awprot (s_reg_axil_awprot), + .s_reg_axil_wready (s_reg_axil_wready), + .s_reg_axil_wvalid (s_reg_axil_wvalid), + .s_reg_axil_wdata (s_reg_axil_wdata), + .s_reg_axil_wstrb (s_reg_axil_wstrb), + .s_reg_axil_bready (s_reg_axil_bready), + .s_reg_axil_bvalid (s_reg_axil_bvalid), + .s_reg_axil_bresp (s_reg_axil_bresp), + .s_reg_axil_arready (s_reg_axil_arready), + .s_reg_axil_arvalid (s_reg_axil_arvalid), + .s_reg_axil_araddr (s_reg_axil_araddr), + .s_reg_axil_arprot (s_reg_axil_arprot), + .s_reg_axil_rready (s_reg_axil_rready), + .s_reg_axil_rvalid (s_reg_axil_rvalid), + .s_reg_axil_rdata (s_reg_axil_rdata), + .s_reg_axil_rresp (s_reg_axil_rresp) ); -generate - - for (genvar i = 0; i < NUM_TCP; i++) begin - logic req; - logic req_is_wr; - logic [5:0] addr; - logic [31:0] wr_data; - logic [31:0] wr_biten; - - assign req = tcp_hwif_out.tcp_streams[i].req; - assign req_is_wr = tcp_hwif_out.tcp_streams[i].req_is_wr; - assign addr = tcp_hwif_out.tcp_streams[i].addr; - assign wr_data = tcp_hwif_out.tcp_streams[i].wr_data; - assign wr_biten = tcp_hwif_out.tcp_streams[i].wr_biten; - - tcp_stream u_tcp_stream ( - .clk (i_clk), - .rst (i_rst), - - // This is the hacky decoder alex was telling me about - .s_cpuif_req (req), - .s_cpuif_req_is_wr (req_is_wr), - .s_cpuif_addr (addr), - .s_cpuif_wr_data (wr_data), - .s_cpuif_wr_biten (wr_biten), - .s_cpuif_req_stall_wr (), - .s_cpuif_req_stall_rd (), - .s_cpuif_rd_ack (tcp_hwif_in.tcp_streams[i].rd_ack), - .s_cpuif_rd_err (), - .s_cpuif_rd_data (tcp_hwif_in.tcp_streams[i].rd_data), - .s_cpuif_wr_ack (tcp_hwif_in.tcp_streams[i].wr_ack), - .s_cpuif_wr_err () - ); - end -endgenerate endmodule \ No newline at end of file diff --git a/hw/super6502_fpga/src/sub/network_processor/src/tcp.sv b/hw/super6502_fpga/src/sub/network_processor/src/tcp.sv new file mode 100644 index 0000000..d7d8e6e --- /dev/null +++ b/hw/super6502_fpga/src/sub/network_processor/src/tcp.sv @@ -0,0 +1,96 @@ +module tcp #( + parameter NUM_TCP=8 +)( + input i_clk, + input i_rst, + +output logic s_reg_axil_awready, +input wire s_reg_axil_awvalid, +input wire [8:0] s_reg_axil_awaddr, +input wire [2:0] s_reg_axil_awprot, +output logic s_reg_axil_wready, +input wire s_reg_axil_wvalid, +input wire [31:0] s_reg_axil_wdata, +input wire [3:0] s_reg_axil_wstrb, +input wire s_reg_axil_bready, +output logic s_reg_axil_bvalid, +output logic [1:0] s_reg_axil_bresp, +output logic s_reg_axil_arready, +input wire s_reg_axil_arvalid, +input wire [8:0] s_reg_axil_araddr, +input wire [2:0] s_reg_axil_arprot, +input wire s_reg_axil_rready, +output logic s_reg_axil_rvalid, +output logic [31:0] s_reg_axil_rdata, +output logic [1:0] s_reg_axil_rresp +); + +tcp_top_regfile_pkg::tcp_top_regfile__in_t tcp_hwif_in; +tcp_top_regfile_pkg::tcp_top_regfile__out_t tcp_hwif_out; + + +tcp_top_regfile u_tcp_top_regfile ( + .clk (i_clk), + .rst (i_rst), + + .s_axil_awready (s_reg_axil_awready), + .s_axil_awvalid (s_reg_axil_awvalid), + .s_axil_awaddr (s_reg_axil_awaddr), + .s_axil_awprot (s_reg_axil_awprot), + .s_axil_wready (s_reg_axil_wready), + .s_axil_wvalid (s_reg_axil_wvalid), + .s_axil_wdata (s_reg_axil_wdata), + .s_axil_wstrb (s_reg_axil_wstrb), + .s_axil_bready (s_reg_axil_bready), + .s_axil_bvalid (s_reg_axil_bvalid), + .s_axil_bresp (s_reg_axil_bresp), + .s_axil_arready (s_reg_axil_arready), + .s_axil_arvalid (s_reg_axil_arvalid), + .s_axil_araddr (s_reg_axil_araddr), + .s_axil_arprot (s_reg_axil_arprot), + .s_axil_rready (s_reg_axil_rready), + .s_axil_rvalid (s_reg_axil_rvalid), + .s_axil_rdata (s_reg_axil_rdata), + .s_axil_rresp (s_reg_axil_rresp), + + .hwif_in (tcp_hwif_in), + .hwif_out (tcp_hwif_out) +); + +generate + + for (genvar i = 0; i < NUM_TCP; i++) begin + logic req; + logic req_is_wr; + logic [5:0] addr; + logic [31:0] wr_data; + logic [31:0] wr_biten; + + assign req = tcp_hwif_out.tcp_streams[i].req; + assign req_is_wr = tcp_hwif_out.tcp_streams[i].req_is_wr; + assign addr = tcp_hwif_out.tcp_streams[i].addr; + assign wr_data = tcp_hwif_out.tcp_streams[i].wr_data; + assign wr_biten = tcp_hwif_out.tcp_streams[i].wr_biten; + + tcp_stream u_tcp_stream ( + .clk (i_clk), + .rst (i_rst), + + // This is the hacky decoder alex was telling me about + .s_cpuif_req (req), + .s_cpuif_req_is_wr (req_is_wr), + .s_cpuif_addr (addr), + .s_cpuif_wr_data (wr_data), + .s_cpuif_wr_biten (wr_biten), + .s_cpuif_req_stall_wr (), + .s_cpuif_req_stall_rd (), + .s_cpuif_rd_ack (tcp_hwif_in.tcp_streams[i].rd_ack), + .s_cpuif_rd_err (), + .s_cpuif_rd_data (tcp_hwif_in.tcp_streams[i].rd_data), + .s_cpuif_wr_ack (tcp_hwif_in.tcp_streams[i].wr_ack), + .s_cpuif_wr_err () + ); + end +endgenerate + +endmodule \ No newline at end of file