diff --git a/hw/efinix_fpga/addr_decode.sv b/hw/efinix_fpga/addr_decode.sv new file mode 100644 index 0000000..a2d49f7 --- /dev/null +++ b/hw/efinix_fpga/addr_decode.sv @@ -0,0 +1,12 @@ +module addr_decode +( + input [15:0] i_addr, + + output o_rom_cs, + output o_leds_cs +); + +assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff; +assign o_leds_cs = i_addr == 16'hefff; + +endmodule \ No newline at end of file diff --git a/hw/efinix_fpga/debug_profile.wizard.json b/hw/efinix_fpga/debug_profile.wizard.json index e605521..7ef2626 100644 --- a/hw/efinix_fpga/debug_profile.wizard.json +++ b/hw/efinix_fpga/debug_profile.wizard.json @@ -3,7 +3,7 @@ { "name": "la0", "type": "la", - "uuid": "244dbd2d34ea40fba571b257d0a2bb75", + "uuid": "7ac38c47d15d4906b7e4dfa4b8e0f620", "trigin_en": false, "trigout_en": false, "auto_inserted": true, @@ -19,42 +19,52 @@ { "name": "cpu_addr", "width": 16, - "probe_type": 1 + "probe_type": 2 }, { "name": "button_reset", "width": 1, - "probe_type": 1 + "probe_type": 2 }, { "name": "cpu_data_in", "width": 8, - "probe_type": 1 + "probe_type": 2 }, { "name": "cpu_rwb", "width": 1, - "probe_type": 1 + "probe_type": 2 }, { "name": "cpu_sync", "width": 1, - "probe_type": 1 + "probe_type": 2 }, { "name": "cpu_data_out", "width": 8, - "probe_type": 1 + "probe_type": 2 }, { "name": "cpu_data_oe", "width": 8, - "probe_type": 1 + "probe_type": 2 }, { "name": "cpu_phi2", "width": 1, - "probe_type": 1 + "probe_type": 2 + }, + { + "name": "w_rom_cs", + "width": 1, + "probe_type": 2 + }, + { + "name": "boot_rom/re", + "width": 1, + "probe_type": 2 } ] } @@ -409,6 +419,18 @@ "name": "la0_probe8", "net": "cpu_phi2", "path": [] + }, + { + "name": "la0_probe9", + "net": "w_rom_cs", + "path": [] + }, + { + "name": "la0_probe10", + "net": "re", + "path": [ + "boot_rom" + ] } ] } @@ -437,7 +459,7 @@ "name": "cpu_addr", "width": 16, "clk_domain": "clk_2", - "selected_probe_type": "DATA AND TRIGGER", + "selected_probe_type": "DATA ONLY", "child": [], "path": [], "net_idx_left": 15, @@ -447,7 +469,7 @@ "name": "button_reset", "width": 1, "clk_domain": "clk_2", - "selected_probe_type": "DATA AND TRIGGER", + "selected_probe_type": "DATA ONLY", "child": [], "path": [] }, @@ -455,7 +477,7 @@ "name": "cpu_data_in", "width": 8, "clk_domain": "clk_2", - "selected_probe_type": "DATA AND TRIGGER", + "selected_probe_type": "DATA ONLY", "child": [], "path": [], "net_idx_left": 7, @@ -465,7 +487,7 @@ "name": "cpu_rwb", "width": 1, "clk_domain": "clk_2", - "selected_probe_type": "DATA AND TRIGGER", + "selected_probe_type": "DATA ONLY", "child": [], "path": [] }, @@ -473,7 +495,7 @@ "name": "cpu_sync", "width": 1, "clk_domain": "clk_2", - "selected_probe_type": "DATA AND TRIGGER", + "selected_probe_type": "DATA ONLY", "child": [], "path": [] }, @@ -481,7 +503,7 @@ "name": "cpu_data_out", "width": 8, "clk_domain": "clk_2", - "selected_probe_type": "DATA AND TRIGGER", + "selected_probe_type": "DATA ONLY", "child": [], "path": [], "net_idx_left": 7, @@ -491,7 +513,7 @@ "name": "cpu_data_oe", "width": 8, "clk_domain": "clk_2", - "selected_probe_type": "DATA AND TRIGGER", + "selected_probe_type": "DATA ONLY", "child": [], "path": [], "net_idx_left": 7, @@ -501,9 +523,27 @@ "name": "cpu_phi2", "width": 1, "clk_domain": "clk_2", - "selected_probe_type": "DATA AND TRIGGER", + "selected_probe_type": "DATA ONLY", "child": [], "path": [] + }, + { + "name": "w_rom_cs", + "width": 1, + "clk_domain": "clk_2", + "selected_probe_type": "DATA ONLY", + "child": [], + "path": [] + }, + { + "name": "re", + "width": 1, + "clk_domain": "clk_2", + "selected_probe_type": "DATA ONLY", + "child": [], + "path": [ + "boot_rom" + ] } ], "top_module": "super6502", diff --git a/hw/efinix_fpga/ip/bram/bram_ini.vh b/hw/efinix_fpga/ip/bram/bram_ini.vh index 01680d1..a3729fa 100644 --- a/hw/efinix_fpga/ip/bram/bram_ini.vh +++ b/hw/efinix_fpga/ip/bram/bram_ini.vh @@ -4,7 +4,7 @@ input integer index;//Mode type input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved case (index) 0: bram_ini_table= -(val_== 0)?256'h0000000000000000000000000000000000000000000000000000010004c000ea: +(val_== 0)?256'h00000000000000000fe00080000fa000d00003a000ef000ff0008d000ff000a9: (val_== 1)?256'h0000000000000000000000000000000000000000000000000000000000000000: (val_== 2)?256'h0000000000000000000000000000000000000000000000000000000000000000: (val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000: @@ -23,7 +23,7 @@ case (index) (val_==16)?256'h0000000000000000000000000000000000000000000000000000000000000000: (val_==17)?256'h0000000000000000000000000000000000000000000000000000000000000000: (val_==18)?256'h0000000000000000000000000000000000000000000000000000000000000000: -(val_==19)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==19)?256'h0000000000000ff0000000000000000000000000000000000000000000000000: (val_==20)?256'h0000000000000000000000000000000000000000000000000000000000000000: (val_==21)?256'h0000000000000000000000000000000000000000000000000000000000000000: (val_==22)?256'h0000000000000000000000000000000000000000000000000000000000000000: diff --git a/hw/efinix_fpga/ip/bram/init_hex.mem b/hw/efinix_fpga/ip/bram/init_hex.mem index 0afe336..6b920db 100644 --- a/hw/efinix_fpga/ip/bram/init_hex.mem +++ b/hw/efinix_fpga/ip/bram/init_hex.mem @@ -1,6 +1,13 @@ -ea -4c -01 +a9 +ff +8d +ff +ef +3a +d0 +fa +80 +fe 00 00 00 @@ -244,13 +251,6 @@ ea 00 00 00 +ff 00 00 -00 -00 -00 -00 -00 -00 -00 -00 \ No newline at end of file diff --git a/hw/efinix_fpga/leds.sv b/hw/efinix_fpga/leds.sv new file mode 100644 index 0000000..06fd580 --- /dev/null +++ b/hw/efinix_fpga/leds.sv @@ -0,0 +1,29 @@ +module leds +( + input clk, + input [7:0] i_data, + output logic [7:0] o_data, + input cs, + input rwb, + + output logic [7:0] o_leds +); + +logic re, we; +assign re = rwb & cs; +assign we = ~rwb & cs; + +logic [7:0] _data; + +assign o_leds = ~_data; + +always @(negedge clk) begin + if (re) begin + o_data <= _data; + end + else if (we) begin + _data <= i_data; + end +end + +endmodule \ No newline at end of file diff --git a/hw/efinix_fpga/super6502.peri.xml b/hw/efinix_fpga/super6502.peri.xml index f375343..77a52a4 100644 --- a/hw/efinix_fpga/super6502.peri.xml +++ b/hw/efinix_fpga/super6502.peri.xml @@ -1,5 +1,5 @@ - + @@ -130,12 +130,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/efinix_fpga/super6502.sv b/hw/efinix_fpga/super6502.sv index 039ec62..4c88070 100644 --- a/hw/efinix_fpga/super6502.sv +++ b/hw/efinix_fpga/super6502.sv @@ -16,7 +16,9 @@ module super6502 output logic cpu_rdy, output logic cpu_resb, output logic pll_cpu_reset, - output logic cpu_phi2 + output logic cpu_phi2, + + output logic [7:0] leds ); assign pll_cpu_reset = '1; @@ -39,15 +41,47 @@ always @(posedge clk_2) begin end end + +logic w_rom_cs; +logic w_leds_cs; + +addr_decode u_addr_decode( + .i_addr(cpu_addr), + .o_rom_cs(w_rom_cs), + .o_leds_cs(w_leds_cs) +); + +logic [7:0] w_rom_data_out; +logic [7:0] w_leds_data_out; + +always_comb begin + if (w_rom_cs) + cpu_data_out = w_rom_data_out; + else if (w_leds_cs) + cpu_data_out= w_leds_data_out; + else + cpu_data_out = 'x; +end + + efx_single_port_ram boot_rom( .clk(clk_2), // clock input for one clock mode .addr(cpu_addr[7:0]), // address input - .wclke('0), // Write clock-enable input - .byteen('0), // Byteen input - .we('0), // Write-enable input + .wclke('0), // Write clock-enable input + .byteen('0), // Byteen input + .we('0), // Write-enable input - .re(cpu_rwb), // Read-enable input - .rdata(cpu_data_out) // Read data output + .re(cpu_rwb & w_rom_cs), // Read-enable input + .rdata(w_rom_data_out) // Read data output +); + +leds u_leds( + .clk(clk_2), + .i_data(cpu_data_in), + .o_data(w_leds_data_out), + .cs(w_leds_cs), + .rwb(cpu_rwb), + .o_leds(leds) ); endmodule diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index 11a500f..135366d 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,5 +1,5 @@ - + @@ -13,6 +13,8 @@ + + @@ -77,7 +79,7 @@ - +