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Update regs

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This commit is contained in:
Byron Lathi
2024-08-19 21:11:12 -07:00
parent 47f958f5c4
commit b8b9852974
9 changed files with 301 additions and 994 deletions
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4
hw/super6502_fpga/src/sub/network_processor/sources.list
View File

@@ -2,6 +2,10 @@ src/regs/tcp_stream_regs_pkg.sv
src/regs/tcp_stream_regs.sv src/regs/tcp_stream_regs.sv
src/regs/tcp_top_regfile_pkg.sv src/regs/tcp_top_regfile_pkg.sv
src/regs/tcp_top_regfile.sv src/regs/tcp_top_regfile.sv
src/regs/mac_regs_pkg.sv
src/regs/mac_regs.sv
src/regs/ntw_top_regfile_pkg.sv
src/regs/ntw_top_regfile.sv
src/network_processor.sv src/network_processor.sv
src/tcp_state_manager.sv src/tcp_state_manager.sv
src/tcp_stream.sv src/tcp_stream.sv

2
hw/super6502_fpga/src/sub/network_processor/src/regs/mac_regs.rdl
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@@ -1,4 +1,4 @@
addrmap mac_t { addrmap mac_regs {
reg { reg {
name = "Control"; name = "Control";
desc = "Control bits for the MAC"; desc = "Control bits for the MAC";

296
hw/super6502_fpga/src/sub/network_processor/src/regs/mac_regs.sv
View File

@@ -66,10 +66,8 @@ module mac_regs (
// Address Decode // Address Decode
//-------------------------------------------------------------------------- //--------------------------------------------------------------------------
typedef struct { typedef struct {
struct {
logic ctrl; logic ctrl;
logic stats; logic stats;
} mac;
} decoded_reg_strb_t; } decoded_reg_strb_t;
decoded_reg_strb_t decoded_reg_strb; decoded_reg_strb_t decoded_reg_strb;
logic decoded_req; logic decoded_req;
@@ -78,8 +76,8 @@ module mac_regs (
logic [31:0] decoded_wr_biten; logic [31:0] decoded_wr_biten;
always_comb begin always_comb begin
decoded_reg_strb.mac.ctrl = cpuif_req_masked & (cpuif_addr == 3'h0); decoded_reg_strb.ctrl = cpuif_req_masked & (cpuif_addr == 3'h0);
decoded_reg_strb.mac.stats = cpuif_req_masked & (cpuif_addr == 3'h4); decoded_reg_strb.stats = cpuif_req_masked & (cpuif_addr == 3'h4);
end end
// Pass down signals to next stage // Pass down signals to next stage
@@ -92,7 +90,6 @@ module mac_regs (
// Field logic // Field logic
//-------------------------------------------------------------------------- //--------------------------------------------------------------------------
typedef struct { typedef struct {
struct {
struct { struct {
struct { struct {
logic next; logic next;
@@ -149,12 +146,10 @@ module mac_regs (
logic load_next; logic load_next;
} rx_fifo_good_frame; } rx_fifo_good_frame;
} stats; } stats;
} mac;
} field_combo_t; } field_combo_t;
field_combo_t field_combo; field_combo_t field_combo;
typedef struct { typedef struct {
struct {
struct { struct {
struct { struct {
logic value; logic value;
@@ -198,310 +193,309 @@ module mac_regs (
logic value; logic value;
} rx_fifo_good_frame; } rx_fifo_good_frame;
} stats; } stats;
} mac;
} field_storage_t; } field_storage_t;
field_storage_t field_storage; field_storage_t field_storage;
// Field: mac_regs.mac.ctrl.tx_en // Field: mac_regs.ctrl.tx_en
always_comb begin always_comb begin
automatic logic [0:0] next_c; automatic logic [0:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.ctrl.tx_en.value; next_c = field_storage.ctrl.tx_en.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.ctrl && decoded_req_is_wr) begin // SW write if(decoded_reg_strb.ctrl && decoded_req_is_wr) begin // SW write
next_c = (field_storage.mac.ctrl.tx_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); next_c = (field_storage.ctrl.tx_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.ctrl.tx_en.next = next_c; field_combo.ctrl.tx_en.next = next_c;
field_combo.mac.ctrl.tx_en.load_next = load_next_c; field_combo.ctrl.tx_en.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.ctrl.tx_en.value <= 1'h0; field_storage.ctrl.tx_en.value <= 1'h0;
end else if(field_combo.mac.ctrl.tx_en.load_next) begin end else if(field_combo.ctrl.tx_en.load_next) begin
field_storage.mac.ctrl.tx_en.value <= field_combo.mac.ctrl.tx_en.next; field_storage.ctrl.tx_en.value <= field_combo.ctrl.tx_en.next;
end end
end end
assign hwif_out.mac.ctrl.tx_en.value = field_storage.mac.ctrl.tx_en.value; assign hwif_out.ctrl.tx_en.value = field_storage.ctrl.tx_en.value;
// Field: mac_regs.mac.ctrl.rx_en // Field: mac_regs.ctrl.rx_en
always_comb begin always_comb begin
automatic logic [0:0] next_c; automatic logic [0:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.ctrl.rx_en.value; next_c = field_storage.ctrl.rx_en.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.ctrl && decoded_req_is_wr) begin // SW write if(decoded_reg_strb.ctrl && decoded_req_is_wr) begin // SW write
next_c = (field_storage.mac.ctrl.rx_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); next_c = (field_storage.ctrl.rx_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.ctrl.rx_en.next = next_c; field_combo.ctrl.rx_en.next = next_c;
field_combo.mac.ctrl.rx_en.load_next = load_next_c; field_combo.ctrl.rx_en.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.ctrl.rx_en.value <= 1'h0; field_storage.ctrl.rx_en.value <= 1'h0;
end else if(field_combo.mac.ctrl.rx_en.load_next) begin end else if(field_combo.ctrl.rx_en.load_next) begin
field_storage.mac.ctrl.rx_en.value <= field_combo.mac.ctrl.rx_en.next; field_storage.ctrl.rx_en.value <= field_combo.ctrl.rx_en.next;
end end
end end
assign hwif_out.mac.ctrl.rx_en.value = field_storage.mac.ctrl.rx_en.value; assign hwif_out.ctrl.rx_en.value = field_storage.ctrl.rx_en.value;
// Field: mac_regs.mac.ctrl.phy_rstn // Field: mac_regs.ctrl.phy_rstn
always_comb begin always_comb begin
automatic logic [0:0] next_c; automatic logic [0:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.ctrl.phy_rstn.value; next_c = field_storage.ctrl.phy_rstn.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.ctrl && decoded_req_is_wr) begin // SW write if(decoded_reg_strb.ctrl && decoded_req_is_wr) begin // SW write
next_c = (field_storage.mac.ctrl.phy_rstn.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); next_c = (field_storage.ctrl.phy_rstn.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]);
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.ctrl.phy_rstn.next = next_c; field_combo.ctrl.phy_rstn.next = next_c;
field_combo.mac.ctrl.phy_rstn.load_next = load_next_c; field_combo.ctrl.phy_rstn.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.ctrl.phy_rstn.value <= 1'h1; field_storage.ctrl.phy_rstn.value <= 1'h1;
end else if(field_combo.mac.ctrl.phy_rstn.load_next) begin end else if(field_combo.ctrl.phy_rstn.load_next) begin
field_storage.mac.ctrl.phy_rstn.value <= field_combo.mac.ctrl.phy_rstn.next; field_storage.ctrl.phy_rstn.value <= field_combo.ctrl.phy_rstn.next;
end end
end end
assign hwif_out.mac.ctrl.phy_rstn.value = field_storage.mac.ctrl.phy_rstn.value; assign hwif_out.ctrl.phy_rstn.value = field_storage.ctrl.phy_rstn.value;
// Field: mac_regs.mac.ctrl.ifg // Field: mac_regs.ctrl.ifg
always_comb begin always_comb begin
automatic logic [7:0] next_c; automatic logic [7:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.ctrl.ifg.value; next_c = field_storage.ctrl.ifg.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.ctrl && decoded_req_is_wr) begin // SW write if(decoded_reg_strb.ctrl && decoded_req_is_wr) begin // SW write
next_c = (field_storage.mac.ctrl.ifg.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]); next_c = (field_storage.ctrl.ifg.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.ctrl.ifg.next = next_c; field_combo.ctrl.ifg.next = next_c;
field_combo.mac.ctrl.ifg.load_next = load_next_c; field_combo.ctrl.ifg.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.ctrl.ifg.value <= 8'h0; field_storage.ctrl.ifg.value <= 8'h0;
end else if(field_combo.mac.ctrl.ifg.load_next) begin end else if(field_combo.ctrl.ifg.load_next) begin
field_storage.mac.ctrl.ifg.value <= field_combo.mac.ctrl.ifg.next; field_storage.ctrl.ifg.value <= field_combo.ctrl.ifg.next;
end end
end end
assign hwif_out.mac.ctrl.ifg.value = field_storage.mac.ctrl.ifg.value; assign hwif_out.ctrl.ifg.value = field_storage.ctrl.ifg.value;
// Field: mac_regs.mac.stats.tx_error_underflow // Field: mac_regs.stats.tx_error_underflow
always_comb begin always_comb begin
automatic logic [0:0] next_c; automatic logic [0:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.stats.tx_error_underflow.value; next_c = field_storage.stats.tx_error_underflow.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.stats && !decoded_req_is_wr) begin // SW clear on read if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0; next_c = '0;
load_next_c = '1; load_next_c = '1;
end else if(hwif_in.mac.stats.tx_error_underflow.hwset) begin // HW Set end else if(hwif_in.stats.tx_error_underflow.hwset) begin // HW Set
next_c = '1; next_c = '1;
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.stats.tx_error_underflow.next = next_c; field_combo.stats.tx_error_underflow.next = next_c;
field_combo.mac.stats.tx_error_underflow.load_next = load_next_c; field_combo.stats.tx_error_underflow.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.stats.tx_error_underflow.value <= 1'h0; field_storage.stats.tx_error_underflow.value <= 1'h0;
end else if(field_combo.mac.stats.tx_error_underflow.load_next) begin end else if(field_combo.stats.tx_error_underflow.load_next) begin
field_storage.mac.stats.tx_error_underflow.value <= field_combo.mac.stats.tx_error_underflow.next; field_storage.stats.tx_error_underflow.value <= field_combo.stats.tx_error_underflow.next;
end end
end end
assign hwif_out.mac.stats.tx_error_underflow.value = field_storage.mac.stats.tx_error_underflow.value; assign hwif_out.stats.tx_error_underflow.value = field_storage.stats.tx_error_underflow.value;
// Field: mac_regs.mac.stats.tx_fifo_overflow // Field: mac_regs.stats.tx_fifo_overflow
always_comb begin always_comb begin
automatic logic [0:0] next_c; automatic logic [0:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.stats.tx_fifo_overflow.value; next_c = field_storage.stats.tx_fifo_overflow.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.stats && !decoded_req_is_wr) begin // SW clear on read if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0; next_c = '0;
load_next_c = '1; load_next_c = '1;
end else if(hwif_in.mac.stats.tx_fifo_overflow.hwset) begin // HW Set end else if(hwif_in.stats.tx_fifo_overflow.hwset) begin // HW Set
next_c = '1; next_c = '1;
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.stats.tx_fifo_overflow.next = next_c; field_combo.stats.tx_fifo_overflow.next = next_c;
field_combo.mac.stats.tx_fifo_overflow.load_next = load_next_c; field_combo.stats.tx_fifo_overflow.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.stats.tx_fifo_overflow.value <= 1'h0; field_storage.stats.tx_fifo_overflow.value <= 1'h0;
end else if(field_combo.mac.stats.tx_fifo_overflow.load_next) begin end else if(field_combo.stats.tx_fifo_overflow.load_next) begin
field_storage.mac.stats.tx_fifo_overflow.value <= field_combo.mac.stats.tx_fifo_overflow.next; field_storage.stats.tx_fifo_overflow.value <= field_combo.stats.tx_fifo_overflow.next;
end end
end end
assign hwif_out.mac.stats.tx_fifo_overflow.value = field_storage.mac.stats.tx_fifo_overflow.value; assign hwif_out.stats.tx_fifo_overflow.value = field_storage.stats.tx_fifo_overflow.value;
// Field: mac_regs.mac.stats.tx_fifo_bad_frame // Field: mac_regs.stats.tx_fifo_bad_frame
always_comb begin always_comb begin
automatic logic [0:0] next_c; automatic logic [0:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.stats.tx_fifo_bad_frame.value; next_c = field_storage.stats.tx_fifo_bad_frame.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.stats && !decoded_req_is_wr) begin // SW clear on read if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0; next_c = '0;
load_next_c = '1; load_next_c = '1;
end else if(hwif_in.mac.stats.tx_fifo_bad_frame.hwset) begin // HW Set end else if(hwif_in.stats.tx_fifo_bad_frame.hwset) begin // HW Set
next_c = '1; next_c = '1;
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.stats.tx_fifo_bad_frame.next = next_c; field_combo.stats.tx_fifo_bad_frame.next = next_c;
field_combo.mac.stats.tx_fifo_bad_frame.load_next = load_next_c; field_combo.stats.tx_fifo_bad_frame.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.stats.tx_fifo_bad_frame.value <= 1'h0; field_storage.stats.tx_fifo_bad_frame.value <= 1'h0;
end else if(field_combo.mac.stats.tx_fifo_bad_frame.load_next) begin end else if(field_combo.stats.tx_fifo_bad_frame.load_next) begin
field_storage.mac.stats.tx_fifo_bad_frame.value <= field_combo.mac.stats.tx_fifo_bad_frame.next; field_storage.stats.tx_fifo_bad_frame.value <= field_combo.stats.tx_fifo_bad_frame.next;
end end
end end
assign hwif_out.mac.stats.tx_fifo_bad_frame.value = field_storage.mac.stats.tx_fifo_bad_frame.value; assign hwif_out.stats.tx_fifo_bad_frame.value = field_storage.stats.tx_fifo_bad_frame.value;
// Field: mac_regs.mac.stats.tx_fifo_good_frame // Field: mac_regs.stats.tx_fifo_good_frame
always_comb begin always_comb begin
automatic logic [0:0] next_c; automatic logic [0:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.stats.tx_fifo_good_frame.value; next_c = field_storage.stats.tx_fifo_good_frame.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.stats && !decoded_req_is_wr) begin // SW clear on read if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0; next_c = '0;
load_next_c = '1; load_next_c = '1;
end else if(hwif_in.mac.stats.tx_fifo_good_frame.hwset) begin // HW Set end else if(hwif_in.stats.tx_fifo_good_frame.hwset) begin // HW Set
next_c = '1; next_c = '1;
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.stats.tx_fifo_good_frame.next = next_c; field_combo.stats.tx_fifo_good_frame.next = next_c;
field_combo.mac.stats.tx_fifo_good_frame.load_next = load_next_c; field_combo.stats.tx_fifo_good_frame.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.stats.tx_fifo_good_frame.value <= 1'h0; field_storage.stats.tx_fifo_good_frame.value <= 1'h0;
end else if(field_combo.mac.stats.tx_fifo_good_frame.load_next) begin end else if(field_combo.stats.tx_fifo_good_frame.load_next) begin
field_storage.mac.stats.tx_fifo_good_frame.value <= field_combo.mac.stats.tx_fifo_good_frame.next; field_storage.stats.tx_fifo_good_frame.value <= field_combo.stats.tx_fifo_good_frame.next;
end end
end end
assign hwif_out.mac.stats.tx_fifo_good_frame.value = field_storage.mac.stats.tx_fifo_good_frame.value; assign hwif_out.stats.tx_fifo_good_frame.value = field_storage.stats.tx_fifo_good_frame.value;
// Field: mac_regs.mac.stats.rx_error_bad_frame // Field: mac_regs.stats.rx_error_bad_frame
always_comb begin always_comb begin
automatic logic [0:0] next_c; automatic logic [0:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.stats.rx_error_bad_frame.value; next_c = field_storage.stats.rx_error_bad_frame.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.stats && !decoded_req_is_wr) begin // SW clear on read if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0; next_c = '0;
load_next_c = '1; load_next_c = '1;
end else if(hwif_in.mac.stats.rx_error_bad_frame.hwset) begin // HW Set end else if(hwif_in.stats.rx_error_bad_frame.hwset) begin // HW Set
next_c = '1; next_c = '1;
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.stats.rx_error_bad_frame.next = next_c; field_combo.stats.rx_error_bad_frame.next = next_c;
field_combo.mac.stats.rx_error_bad_frame.load_next = load_next_c; field_combo.stats.rx_error_bad_frame.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.stats.rx_error_bad_frame.value <= 1'h0; field_storage.stats.rx_error_bad_frame.value <= 1'h0;
end else if(field_combo.mac.stats.rx_error_bad_frame.load_next) begin end else if(field_combo.stats.rx_error_bad_frame.load_next) begin
field_storage.mac.stats.rx_error_bad_frame.value <= field_combo.mac.stats.rx_error_bad_frame.next; field_storage.stats.rx_error_bad_frame.value <= field_combo.stats.rx_error_bad_frame.next;
end end
end end
assign hwif_out.mac.stats.rx_error_bad_frame.value = field_storage.mac.stats.rx_error_bad_frame.value; assign hwif_out.stats.rx_error_bad_frame.value = field_storage.stats.rx_error_bad_frame.value;
// Field: mac_regs.mac.stats.rx_error_bad_fcs // Field: mac_regs.stats.rx_error_bad_fcs
always_comb begin always_comb begin
automatic logic [0:0] next_c; automatic logic [0:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.stats.rx_error_bad_fcs.value; next_c = field_storage.stats.rx_error_bad_fcs.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.stats && !decoded_req_is_wr) begin // SW clear on read if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0; next_c = '0;
load_next_c = '1; load_next_c = '1;
end else if(hwif_in.mac.stats.rx_error_bad_fcs.hwset) begin // HW Set end else if(hwif_in.stats.rx_error_bad_fcs.hwset) begin // HW Set
next_c = '1; next_c = '1;
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.stats.rx_error_bad_fcs.next = next_c; field_combo.stats.rx_error_bad_fcs.next = next_c;
field_combo.mac.stats.rx_error_bad_fcs.load_next = load_next_c; field_combo.stats.rx_error_bad_fcs.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.stats.rx_error_bad_fcs.value <= 1'h0; field_storage.stats.rx_error_bad_fcs.value <= 1'h0;
end else if(field_combo.mac.stats.rx_error_bad_fcs.load_next) begin end else if(field_combo.stats.rx_error_bad_fcs.load_next) begin
field_storage.mac.stats.rx_error_bad_fcs.value <= field_combo.mac.stats.rx_error_bad_fcs.next; field_storage.stats.rx_error_bad_fcs.value <= field_combo.stats.rx_error_bad_fcs.next;
end end
end end
assign hwif_out.mac.stats.rx_error_bad_fcs.value = field_storage.mac.stats.rx_error_bad_fcs.value; assign hwif_out.stats.rx_error_bad_fcs.value = field_storage.stats.rx_error_bad_fcs.value;
// Field: mac_regs.mac.stats.rx_fifo_overflow // Field: mac_regs.stats.rx_fifo_overflow
always_comb begin always_comb begin
automatic logic [0:0] next_c; automatic logic [0:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.stats.rx_fifo_overflow.value; next_c = field_storage.stats.rx_fifo_overflow.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.stats && !decoded_req_is_wr) begin // SW clear on read if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0; next_c = '0;
load_next_c = '1; load_next_c = '1;
end else if(hwif_in.mac.stats.rx_fifo_overflow.hwset) begin // HW Set end else if(hwif_in.stats.rx_fifo_overflow.hwset) begin // HW Set
next_c = '1; next_c = '1;
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.stats.rx_fifo_overflow.next = next_c; field_combo.stats.rx_fifo_overflow.next = next_c;
field_combo.mac.stats.rx_fifo_overflow.load_next = load_next_c; field_combo.stats.rx_fifo_overflow.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.stats.rx_fifo_overflow.value <= 1'h0; field_storage.stats.rx_fifo_overflow.value <= 1'h0;
end else if(field_combo.mac.stats.rx_fifo_overflow.load_next) begin end else if(field_combo.stats.rx_fifo_overflow.load_next) begin
field_storage.mac.stats.rx_fifo_overflow.value <= field_combo.mac.stats.rx_fifo_overflow.next; field_storage.stats.rx_fifo_overflow.value <= field_combo.stats.rx_fifo_overflow.next;
end end
end end
assign hwif_out.mac.stats.rx_fifo_overflow.value = field_storage.mac.stats.rx_fifo_overflow.value; assign hwif_out.stats.rx_fifo_overflow.value = field_storage.stats.rx_fifo_overflow.value;
// Field: mac_regs.mac.stats.rx_fifo_bad_frame // Field: mac_regs.stats.rx_fifo_bad_frame
always_comb begin always_comb begin
automatic logic [0:0] next_c; automatic logic [0:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.stats.rx_fifo_bad_frame.value; next_c = field_storage.stats.rx_fifo_bad_frame.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.stats && !decoded_req_is_wr) begin // SW clear on read if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0; next_c = '0;
load_next_c = '1; load_next_c = '1;
end else if(hwif_in.mac.stats.rx_fifo_bad_frame.hwset) begin // HW Set end else if(hwif_in.stats.rx_fifo_bad_frame.hwset) begin // HW Set
next_c = '1; next_c = '1;
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.stats.rx_fifo_bad_frame.next = next_c; field_combo.stats.rx_fifo_bad_frame.next = next_c;
field_combo.mac.stats.rx_fifo_bad_frame.load_next = load_next_c; field_combo.stats.rx_fifo_bad_frame.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.stats.rx_fifo_bad_frame.value <= 1'h0; field_storage.stats.rx_fifo_bad_frame.value <= 1'h0;
end else if(field_combo.mac.stats.rx_fifo_bad_frame.load_next) begin end else if(field_combo.stats.rx_fifo_bad_frame.load_next) begin
field_storage.mac.stats.rx_fifo_bad_frame.value <= field_combo.mac.stats.rx_fifo_bad_frame.next; field_storage.stats.rx_fifo_bad_frame.value <= field_combo.stats.rx_fifo_bad_frame.next;
end end
end end
assign hwif_out.mac.stats.rx_fifo_bad_frame.value = field_storage.mac.stats.rx_fifo_bad_frame.value; assign hwif_out.stats.rx_fifo_bad_frame.value = field_storage.stats.rx_fifo_bad_frame.value;
// Field: mac_regs.mac.stats.rx_fifo_good_frame // Field: mac_regs.stats.rx_fifo_good_frame
always_comb begin always_comb begin
automatic logic [0:0] next_c; automatic logic [0:0] next_c;
automatic logic load_next_c; automatic logic load_next_c;
next_c = field_storage.mac.stats.rx_fifo_good_frame.value; next_c = field_storage.stats.rx_fifo_good_frame.value;
load_next_c = '0; load_next_c = '0;
if(decoded_reg_strb.mac.stats && !decoded_req_is_wr) begin // SW clear on read if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0; next_c = '0;
load_next_c = '1; load_next_c = '1;
end else if(hwif_in.mac.stats.rx_fifo_good_frame.hwset) begin // HW Set end else if(hwif_in.stats.rx_fifo_good_frame.hwset) begin // HW Set
next_c = '1; next_c = '1;
load_next_c = '1; load_next_c = '1;
end end
field_combo.mac.stats.rx_fifo_good_frame.next = next_c; field_combo.stats.rx_fifo_good_frame.next = next_c;
field_combo.mac.stats.rx_fifo_good_frame.load_next = load_next_c; field_combo.stats.rx_fifo_good_frame.load_next = load_next_c;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
field_storage.mac.stats.rx_fifo_good_frame.value <= 1'h0; field_storage.stats.rx_fifo_good_frame.value <= 1'h0;
end else if(field_combo.mac.stats.rx_fifo_good_frame.load_next) begin end else if(field_combo.stats.rx_fifo_good_frame.load_next) begin
field_storage.mac.stats.rx_fifo_good_frame.value <= field_combo.mac.stats.rx_fifo_good_frame.next; field_storage.stats.rx_fifo_good_frame.value <= field_combo.stats.rx_fifo_good_frame.next;
end end
end end
assign hwif_out.mac.stats.rx_fifo_good_frame.value = field_storage.mac.stats.rx_fifo_good_frame.value; assign hwif_out.stats.rx_fifo_good_frame.value = field_storage.stats.rx_fifo_good_frame.value;
//-------------------------------------------------------------------------- //--------------------------------------------------------------------------
// Write response // Write response
@@ -520,21 +514,21 @@ module mac_regs (
// Assign readback values to a flattened array // Assign readback values to a flattened array
logic [31:0] readback_array[2]; logic [31:0] readback_array[2];
assign readback_array[0][0:0] = (decoded_reg_strb.mac.ctrl && !decoded_req_is_wr) ? field_storage.mac.ctrl.tx_en.value : '0; assign readback_array[0][0:0] = (decoded_reg_strb.ctrl && !decoded_req_is_wr) ? field_storage.ctrl.tx_en.value : '0;
assign readback_array[0][1:1] = (decoded_reg_strb.mac.ctrl && !decoded_req_is_wr) ? field_storage.mac.ctrl.rx_en.value : '0; assign readback_array[0][1:1] = (decoded_reg_strb.ctrl && !decoded_req_is_wr) ? field_storage.ctrl.rx_en.value : '0;
assign readback_array[0][2:2] = (decoded_reg_strb.mac.ctrl && !decoded_req_is_wr) ? field_storage.mac.ctrl.phy_rstn.value : '0; assign readback_array[0][2:2] = (decoded_reg_strb.ctrl && !decoded_req_is_wr) ? field_storage.ctrl.phy_rstn.value : '0;
assign readback_array[0][7:3] = '0; assign readback_array[0][7:3] = '0;
assign readback_array[0][15:8] = (decoded_reg_strb.mac.ctrl && !decoded_req_is_wr) ? field_storage.mac.ctrl.ifg.value : '0; assign readback_array[0][15:8] = (decoded_reg_strb.ctrl && !decoded_req_is_wr) ? field_storage.ctrl.ifg.value : '0;
assign readback_array[0][31:16] = '0; assign readback_array[0][31:16] = '0;
assign readback_array[1][0:0] = (decoded_reg_strb.mac.stats && !decoded_req_is_wr) ? field_storage.mac.stats.tx_error_underflow.value : '0; assign readback_array[1][0:0] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.tx_error_underflow.value : '0;
assign readback_array[1][1:1] = (decoded_reg_strb.mac.stats && !decoded_req_is_wr) ? field_storage.mac.stats.tx_fifo_overflow.value : '0; assign readback_array[1][1:1] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.tx_fifo_overflow.value : '0;
assign readback_array[1][2:2] = (decoded_reg_strb.mac.stats && !decoded_req_is_wr) ? field_storage.mac.stats.tx_fifo_bad_frame.value : '0; assign readback_array[1][2:2] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.tx_fifo_bad_frame.value : '0;
assign readback_array[1][3:3] = (decoded_reg_strb.mac.stats && !decoded_req_is_wr) ? field_storage.mac.stats.tx_fifo_good_frame.value : '0; assign readback_array[1][3:3] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.tx_fifo_good_frame.value : '0;
assign readback_array[1][4:4] = (decoded_reg_strb.mac.stats && !decoded_req_is_wr) ? field_storage.mac.stats.rx_error_bad_frame.value : '0; assign readback_array[1][4:4] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.rx_error_bad_frame.value : '0;
assign readback_array[1][5:5] = (decoded_reg_strb.mac.stats && !decoded_req_is_wr) ? field_storage.mac.stats.rx_error_bad_fcs.value : '0; assign readback_array[1][5:5] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.rx_error_bad_fcs.value : '0;
assign readback_array[1][6:6] = (decoded_reg_strb.mac.stats && !decoded_req_is_wr) ? field_storage.mac.stats.rx_fifo_overflow.value : '0; assign readback_array[1][6:6] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.rx_fifo_overflow.value : '0;
assign readback_array[1][7:7] = (decoded_reg_strb.mac.stats && !decoded_req_is_wr) ? field_storage.mac.stats.rx_fifo_bad_frame.value : '0; assign readback_array[1][7:7] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.rx_fifo_bad_frame.value : '0;
assign readback_array[1][8:8] = (decoded_reg_strb.mac.stats && !decoded_req_is_wr) ? field_storage.mac.stats.rx_fifo_good_frame.value : '0; assign readback_array[1][8:8] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.rx_fifo_good_frame.value : '0;
assign readback_array[1][31:9] = '0; assign readback_array[1][31:9] = '0;
// Reduce the array // Reduce the array

108
hw/super6502_fpga/src/sub/network_processor/src/regs/mac_regs_pkg.sv
View File

@@ -8,137 +8,129 @@ package mac_regs_pkg;
typedef struct { typedef struct {
logic hwset; logic hwset;
} mac_t__stats__tx_error_underflow__in_t; } mac_regs__stats__tx_error_underflow__in_t;
typedef struct { typedef struct {
logic hwset; logic hwset;
} mac_t__stats__tx_fifo_overflow__in_t; } mac_regs__stats__tx_fifo_overflow__in_t;
typedef struct { typedef struct {
logic hwset; logic hwset;
} mac_t__stats__tx_fifo_bad_frame__in_t; } mac_regs__stats__tx_fifo_bad_frame__in_t;
typedef struct { typedef struct {
logic hwset; logic hwset;
} mac_t__stats__tx_fifo_good_frame__in_t; } mac_regs__stats__tx_fifo_good_frame__in_t;
typedef struct { typedef struct {
logic hwset; logic hwset;
} mac_t__stats__rx_error_bad_frame__in_t; } mac_regs__stats__rx_error_bad_frame__in_t;
typedef struct { typedef struct {
logic hwset; logic hwset;
} mac_t__stats__rx_error_bad_fcs__in_t; } mac_regs__stats__rx_error_bad_fcs__in_t;
typedef struct { typedef struct {
logic hwset; logic hwset;
} mac_t__stats__rx_fifo_overflow__in_t; } mac_regs__stats__rx_fifo_overflow__in_t;
typedef struct { typedef struct {
logic hwset; logic hwset;
} mac_t__stats__rx_fifo_bad_frame__in_t; } mac_regs__stats__rx_fifo_bad_frame__in_t;
typedef struct { typedef struct {
logic hwset; logic hwset;
} mac_t__stats__rx_fifo_good_frame__in_t; } mac_regs__stats__rx_fifo_good_frame__in_t;
typedef struct { typedef struct {
mac_t__stats__tx_error_underflow__in_t tx_error_underflow; mac_regs__stats__tx_error_underflow__in_t tx_error_underflow;
mac_t__stats__tx_fifo_overflow__in_t tx_fifo_overflow; mac_regs__stats__tx_fifo_overflow__in_t tx_fifo_overflow;
mac_t__stats__tx_fifo_bad_frame__in_t tx_fifo_bad_frame; mac_regs__stats__tx_fifo_bad_frame__in_t tx_fifo_bad_frame;
mac_t__stats__tx_fifo_good_frame__in_t tx_fifo_good_frame; mac_regs__stats__tx_fifo_good_frame__in_t tx_fifo_good_frame;
mac_t__stats__rx_error_bad_frame__in_t rx_error_bad_frame; mac_regs__stats__rx_error_bad_frame__in_t rx_error_bad_frame;
mac_t__stats__rx_error_bad_fcs__in_t rx_error_bad_fcs; mac_regs__stats__rx_error_bad_fcs__in_t rx_error_bad_fcs;
mac_t__stats__rx_fifo_overflow__in_t rx_fifo_overflow; mac_regs__stats__rx_fifo_overflow__in_t rx_fifo_overflow;
mac_t__stats__rx_fifo_bad_frame__in_t rx_fifo_bad_frame; mac_regs__stats__rx_fifo_bad_frame__in_t rx_fifo_bad_frame;
mac_t__stats__rx_fifo_good_frame__in_t rx_fifo_good_frame; mac_regs__stats__rx_fifo_good_frame__in_t rx_fifo_good_frame;
} mac_t__stats__in_t; } mac_regs__stats__in_t;
typedef struct { typedef struct {
mac_t__stats__in_t stats; mac_regs__stats__in_t stats;
} mac_t__in_t;
typedef struct {
mac_t__in_t mac;
} mac_regs__in_t; } mac_regs__in_t;
typedef struct { typedef struct {
logic value; logic value;
} mac_t__ctrl__tx_en__out_t; } mac_regs__ctrl__tx_en__out_t;
typedef struct { typedef struct {
logic value; logic value;
} mac_t__ctrl__rx_en__out_t; } mac_regs__ctrl__rx_en__out_t;
typedef struct { typedef struct {
logic value; logic value;
} mac_t__ctrl__phy_rstn__out_t; } mac_regs__ctrl__phy_rstn__out_t;
typedef struct { typedef struct {
logic [7:0] value; logic [7:0] value;
} mac_t__ctrl__ifg__out_t; } mac_regs__ctrl__ifg__out_t;
typedef struct { typedef struct {
mac_t__ctrl__tx_en__out_t tx_en; mac_regs__ctrl__tx_en__out_t tx_en;
mac_t__ctrl__rx_en__out_t rx_en; mac_regs__ctrl__rx_en__out_t rx_en;
mac_t__ctrl__phy_rstn__out_t phy_rstn; mac_regs__ctrl__phy_rstn__out_t phy_rstn;
mac_t__ctrl__ifg__out_t ifg; mac_regs__ctrl__ifg__out_t ifg;
} mac_t__ctrl__out_t; } mac_regs__ctrl__out_t;
typedef struct { typedef struct {
logic value; logic value;
} mac_t__stats__tx_error_underflow__out_t; } mac_regs__stats__tx_error_underflow__out_t;
typedef struct { typedef struct {
logic value; logic value;
} mac_t__stats__tx_fifo_overflow__out_t; } mac_regs__stats__tx_fifo_overflow__out_t;
typedef struct { typedef struct {
logic value; logic value;
} mac_t__stats__tx_fifo_bad_frame__out_t; } mac_regs__stats__tx_fifo_bad_frame__out_t;
typedef struct { typedef struct {
logic value; logic value;
} mac_t__stats__tx_fifo_good_frame__out_t; } mac_regs__stats__tx_fifo_good_frame__out_t;
typedef struct { typedef struct {
logic value; logic value;
} mac_t__stats__rx_error_bad_frame__out_t; } mac_regs__stats__rx_error_bad_frame__out_t;
typedef struct { typedef struct {
logic value; logic value;
} mac_t__stats__rx_error_bad_fcs__out_t; } mac_regs__stats__rx_error_bad_fcs__out_t;
typedef struct { typedef struct {
logic value; logic value;
} mac_t__stats__rx_fifo_overflow__out_t; } mac_regs__stats__rx_fifo_overflow__out_t;
typedef struct { typedef struct {
logic value; logic value;
} mac_t__stats__rx_fifo_bad_frame__out_t; } mac_regs__stats__rx_fifo_bad_frame__out_t;
typedef struct { typedef struct {
logic value; logic value;
} mac_t__stats__rx_fifo_good_frame__out_t; } mac_regs__stats__rx_fifo_good_frame__out_t;
typedef struct { typedef struct {
mac_t__stats__tx_error_underflow__out_t tx_error_underflow; mac_regs__stats__tx_error_underflow__out_t tx_error_underflow;
mac_t__stats__tx_fifo_overflow__out_t tx_fifo_overflow; mac_regs__stats__tx_fifo_overflow__out_t tx_fifo_overflow;
mac_t__stats__tx_fifo_bad_frame__out_t tx_fifo_bad_frame; mac_regs__stats__tx_fifo_bad_frame__out_t tx_fifo_bad_frame;
mac_t__stats__tx_fifo_good_frame__out_t tx_fifo_good_frame; mac_regs__stats__tx_fifo_good_frame__out_t tx_fifo_good_frame;
mac_t__stats__rx_error_bad_frame__out_t rx_error_bad_frame; mac_regs__stats__rx_error_bad_frame__out_t rx_error_bad_frame;
mac_t__stats__rx_error_bad_fcs__out_t rx_error_bad_fcs; mac_regs__stats__rx_error_bad_fcs__out_t rx_error_bad_fcs;
mac_t__stats__rx_fifo_overflow__out_t rx_fifo_overflow; mac_regs__stats__rx_fifo_overflow__out_t rx_fifo_overflow;
mac_t__stats__rx_fifo_bad_frame__out_t rx_fifo_bad_frame; mac_regs__stats__rx_fifo_bad_frame__out_t rx_fifo_bad_frame;
mac_t__stats__rx_fifo_good_frame__out_t rx_fifo_good_frame; mac_regs__stats__rx_fifo_good_frame__out_t rx_fifo_good_frame;
} mac_t__stats__out_t; } mac_regs__stats__out_t;
typedef struct { typedef struct {
mac_t__ctrl__out_t ctrl; mac_regs__ctrl__out_t ctrl;
mac_t__stats__out_t stats; mac_regs__stats__out_t stats;
} mac_t__out_t;
typedef struct {
mac_t__out_t mac;
} mac_regs__out_t; } mac_regs__out_t;
endpackage endpackage

547
hw/super6502_fpga/src/sub/network_processor/src/regs/mac_t.sv
View File

@@ -1,547 +0,0 @@
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
module mac_t (
input wire clk,
input wire rst,
input wire s_cpuif_req,
input wire s_cpuif_req_is_wr,
input wire [2:0] s_cpuif_addr,
input wire [31:0] s_cpuif_wr_data,
input wire [31:0] s_cpuif_wr_biten,
output wire s_cpuif_req_stall_wr,
output wire s_cpuif_req_stall_rd,
output wire s_cpuif_rd_ack,
output wire s_cpuif_rd_err,
output wire [31:0] s_cpuif_rd_data,
output wire s_cpuif_wr_ack,
output wire s_cpuif_wr_err,
input mac_t_pkg::mac_t__in_t hwif_in,
output mac_t_pkg::mac_t__out_t hwif_out
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_req_is_wr;
logic [2:0] cpuif_addr;
logic [31:0] cpuif_wr_data;
logic [31:0] cpuif_wr_biten;
logic cpuif_req_stall_wr;
logic cpuif_req_stall_rd;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
logic cpuif_wr_ack;
logic cpuif_wr_err;
assign cpuif_req = s_cpuif_req;
assign cpuif_req_is_wr = s_cpuif_req_is_wr;
assign cpuif_addr = s_cpuif_addr;
assign cpuif_wr_data = s_cpuif_wr_data;
assign cpuif_wr_biten = s_cpuif_wr_biten;
assign s_cpuif_req_stall_wr = cpuif_req_stall_wr;
assign s_cpuif_req_stall_rd = cpuif_req_stall_rd;
assign s_cpuif_rd_ack = cpuif_rd_ack;
assign s_cpuif_rd_err = cpuif_rd_err;
assign s_cpuif_rd_data = cpuif_rd_data;
assign s_cpuif_wr_ack = cpuif_wr_ack;
assign s_cpuif_wr_err = cpuif_wr_err;
logic cpuif_req_masked;
// Read & write latencies are balanced. Stalls not required
assign cpuif_req_stall_rd = '0;
assign cpuif_req_stall_wr = '0;
assign cpuif_req_masked = cpuif_req
& !(!cpuif_req_is_wr & cpuif_req_stall_rd)
& !(cpuif_req_is_wr & cpuif_req_stall_wr);
//--------------------------------------------------------------------------
// Address Decode
//--------------------------------------------------------------------------
typedef struct {
logic ctrl;
logic stats;
} decoded_reg_strb_t;
decoded_reg_strb_t decoded_reg_strb;
logic decoded_req;
logic decoded_req_is_wr;
logic [31:0] decoded_wr_data;
logic [31:0] decoded_wr_biten;
always_comb begin
decoded_reg_strb.ctrl = cpuif_req_masked & (cpuif_addr == 3'h0);
decoded_reg_strb.stats = cpuif_req_masked & (cpuif_addr == 3'h4);
end
// Pass down signals to next stage
assign decoded_req = cpuif_req_masked;
assign decoded_req_is_wr = cpuif_req_is_wr;
assign decoded_wr_data = cpuif_wr_data;
assign decoded_wr_biten = cpuif_wr_biten;
//--------------------------------------------------------------------------
// Field logic
//--------------------------------------------------------------------------
typedef struct {
struct {
struct {
logic next;
logic load_next;
} tx_en;
struct {
logic next;
logic load_next;
} rx_en;
struct {
logic next;
logic load_next;
} phy_rstn;
struct {
logic [7:0] next;
logic load_next;
} ifg;
} ctrl;
struct {
struct {
logic next;
logic load_next;
} tx_error_underflow;
struct {
logic next;
logic load_next;
} tx_fifo_overflow;
struct {
logic next;
logic load_next;
} tx_fifo_bad_frame;
struct {
logic next;
logic load_next;
} tx_fifo_good_frame;
struct {
logic next;
logic load_next;
} rx_error_bad_frame;
struct {
logic next;
logic load_next;
} rx_error_bad_fcs;
struct {
logic next;
logic load_next;
} rx_fifo_overflow;
struct {
logic next;
logic load_next;
} rx_fifo_bad_frame;
struct {
logic next;
logic load_next;
} rx_fifo_good_frame;
} stats;
} field_combo_t;
field_combo_t field_combo;
typedef struct {
struct {
struct {
logic value;
} tx_en;
struct {
logic value;
} rx_en;
struct {
logic value;
} phy_rstn;
struct {
logic [7:0] value;
} ifg;
} ctrl;
struct {
struct {
logic value;
} tx_error_underflow;
struct {
logic value;
} tx_fifo_overflow;
struct {
logic value;
} tx_fifo_bad_frame;
struct {
logic value;
} tx_fifo_good_frame;
struct {
logic value;
} rx_error_bad_frame;
struct {
logic value;
} rx_error_bad_fcs;
struct {
logic value;
} rx_fifo_overflow;
struct {
logic value;
} rx_fifo_bad_frame;
struct {
logic value;
} rx_fifo_good_frame;
} stats;
} field_storage_t;
field_storage_t field_storage;
// Field: mac_t.ctrl.tx_en
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.ctrl.tx_en.value;
load_next_c = '0;
if(decoded_reg_strb.ctrl && decoded_req_is_wr) begin // SW write
next_c = (field_storage.ctrl.tx_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
load_next_c = '1;
end
field_combo.ctrl.tx_en.next = next_c;
field_combo.ctrl.tx_en.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.ctrl.tx_en.value <= 1'h0;
end else if(field_combo.ctrl.tx_en.load_next) begin
field_storage.ctrl.tx_en.value <= field_combo.ctrl.tx_en.next;
end
end
assign hwif_out.ctrl.tx_en.value = field_storage.ctrl.tx_en.value;
// Field: mac_t.ctrl.rx_en
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.ctrl.rx_en.value;
load_next_c = '0;
if(decoded_reg_strb.ctrl && decoded_req_is_wr) begin // SW write
next_c = (field_storage.ctrl.rx_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
load_next_c = '1;
end
field_combo.ctrl.rx_en.next = next_c;
field_combo.ctrl.rx_en.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.ctrl.rx_en.value <= 1'h0;
end else if(field_combo.ctrl.rx_en.load_next) begin
field_storage.ctrl.rx_en.value <= field_combo.ctrl.rx_en.next;
end
end
assign hwif_out.ctrl.rx_en.value = field_storage.ctrl.rx_en.value;
// Field: mac_t.ctrl.phy_rstn
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.ctrl.phy_rstn.value;
load_next_c = '0;
if(decoded_reg_strb.ctrl && decoded_req_is_wr) begin // SW write
next_c = (field_storage.ctrl.phy_rstn.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]);
load_next_c = '1;
end
field_combo.ctrl.phy_rstn.next = next_c;
field_combo.ctrl.phy_rstn.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.ctrl.phy_rstn.value <= 1'h1;
end else if(field_combo.ctrl.phy_rstn.load_next) begin
field_storage.ctrl.phy_rstn.value <= field_combo.ctrl.phy_rstn.next;
end
end
assign hwif_out.ctrl.phy_rstn.value = field_storage.ctrl.phy_rstn.value;
// Field: mac_t.ctrl.ifg
always_comb begin
automatic logic [7:0] next_c;
automatic logic load_next_c;
next_c = field_storage.ctrl.ifg.value;
load_next_c = '0;
if(decoded_reg_strb.ctrl && decoded_req_is_wr) begin // SW write
next_c = (field_storage.ctrl.ifg.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
load_next_c = '1;
end
field_combo.ctrl.ifg.next = next_c;
field_combo.ctrl.ifg.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.ctrl.ifg.value <= 8'h0;
end else if(field_combo.ctrl.ifg.load_next) begin
field_storage.ctrl.ifg.value <= field_combo.ctrl.ifg.next;
end
end
assign hwif_out.ctrl.ifg.value = field_storage.ctrl.ifg.value;
// Field: mac_t.stats.tx_error_underflow
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.stats.tx_error_underflow.value;
load_next_c = '0;
if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0;
load_next_c = '1;
end else if(hwif_in.stats.tx_error_underflow.hwset) begin // HW Set
next_c = '1;
load_next_c = '1;
end
field_combo.stats.tx_error_underflow.next = next_c;
field_combo.stats.tx_error_underflow.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.stats.tx_error_underflow.value <= 1'h0;
end else if(field_combo.stats.tx_error_underflow.load_next) begin
field_storage.stats.tx_error_underflow.value <= field_combo.stats.tx_error_underflow.next;
end
end
assign hwif_out.stats.tx_error_underflow.value = field_storage.stats.tx_error_underflow.value;
// Field: mac_t.stats.tx_fifo_overflow
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.stats.tx_fifo_overflow.value;
load_next_c = '0;
if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0;
load_next_c = '1;
end else if(hwif_in.stats.tx_fifo_overflow.hwset) begin // HW Set
next_c = '1;
load_next_c = '1;
end
field_combo.stats.tx_fifo_overflow.next = next_c;
field_combo.stats.tx_fifo_overflow.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.stats.tx_fifo_overflow.value <= 1'h0;
end else if(field_combo.stats.tx_fifo_overflow.load_next) begin
field_storage.stats.tx_fifo_overflow.value <= field_combo.stats.tx_fifo_overflow.next;
end
end
assign hwif_out.stats.tx_fifo_overflow.value = field_storage.stats.tx_fifo_overflow.value;
// Field: mac_t.stats.tx_fifo_bad_frame
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.stats.tx_fifo_bad_frame.value;
load_next_c = '0;
if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0;
load_next_c = '1;
end else if(hwif_in.stats.tx_fifo_bad_frame.hwset) begin // HW Set
next_c = '1;
load_next_c = '1;
end
field_combo.stats.tx_fifo_bad_frame.next = next_c;
field_combo.stats.tx_fifo_bad_frame.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.stats.tx_fifo_bad_frame.value <= 1'h0;
end else if(field_combo.stats.tx_fifo_bad_frame.load_next) begin
field_storage.stats.tx_fifo_bad_frame.value <= field_combo.stats.tx_fifo_bad_frame.next;
end
end
assign hwif_out.stats.tx_fifo_bad_frame.value = field_storage.stats.tx_fifo_bad_frame.value;
// Field: mac_t.stats.tx_fifo_good_frame
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.stats.tx_fifo_good_frame.value;
load_next_c = '0;
if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0;
load_next_c = '1;
end else if(hwif_in.stats.tx_fifo_good_frame.hwset) begin // HW Set
next_c = '1;
load_next_c = '1;
end
field_combo.stats.tx_fifo_good_frame.next = next_c;
field_combo.stats.tx_fifo_good_frame.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.stats.tx_fifo_good_frame.value <= 1'h0;
end else if(field_combo.stats.tx_fifo_good_frame.load_next) begin
field_storage.stats.tx_fifo_good_frame.value <= field_combo.stats.tx_fifo_good_frame.next;
end
end
assign hwif_out.stats.tx_fifo_good_frame.value = field_storage.stats.tx_fifo_good_frame.value;
// Field: mac_t.stats.rx_error_bad_frame
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.stats.rx_error_bad_frame.value;
load_next_c = '0;
if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0;
load_next_c = '1;
end else if(hwif_in.stats.rx_error_bad_frame.hwset) begin // HW Set
next_c = '1;
load_next_c = '1;
end
field_combo.stats.rx_error_bad_frame.next = next_c;
field_combo.stats.rx_error_bad_frame.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.stats.rx_error_bad_frame.value <= 1'h0;
end else if(field_combo.stats.rx_error_bad_frame.load_next) begin
field_storage.stats.rx_error_bad_frame.value <= field_combo.stats.rx_error_bad_frame.next;
end
end
assign hwif_out.stats.rx_error_bad_frame.value = field_storage.stats.rx_error_bad_frame.value;
// Field: mac_t.stats.rx_error_bad_fcs
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.stats.rx_error_bad_fcs.value;
load_next_c = '0;
if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0;
load_next_c = '1;
end else if(hwif_in.stats.rx_error_bad_fcs.hwset) begin // HW Set
next_c = '1;
load_next_c = '1;
end
field_combo.stats.rx_error_bad_fcs.next = next_c;
field_combo.stats.rx_error_bad_fcs.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.stats.rx_error_bad_fcs.value <= 1'h0;
end else if(field_combo.stats.rx_error_bad_fcs.load_next) begin
field_storage.stats.rx_error_bad_fcs.value <= field_combo.stats.rx_error_bad_fcs.next;
end
end
assign hwif_out.stats.rx_error_bad_fcs.value = field_storage.stats.rx_error_bad_fcs.value;
// Field: mac_t.stats.rx_fifo_overflow
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.stats.rx_fifo_overflow.value;
load_next_c = '0;
if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0;
load_next_c = '1;
end else if(hwif_in.stats.rx_fifo_overflow.hwset) begin // HW Set
next_c = '1;
load_next_c = '1;
end
field_combo.stats.rx_fifo_overflow.next = next_c;
field_combo.stats.rx_fifo_overflow.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.stats.rx_fifo_overflow.value <= 1'h0;
end else if(field_combo.stats.rx_fifo_overflow.load_next) begin
field_storage.stats.rx_fifo_overflow.value <= field_combo.stats.rx_fifo_overflow.next;
end
end
assign hwif_out.stats.rx_fifo_overflow.value = field_storage.stats.rx_fifo_overflow.value;
// Field: mac_t.stats.rx_fifo_bad_frame
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.stats.rx_fifo_bad_frame.value;
load_next_c = '0;
if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0;
load_next_c = '1;
end else if(hwif_in.stats.rx_fifo_bad_frame.hwset) begin // HW Set
next_c = '1;
load_next_c = '1;
end
field_combo.stats.rx_fifo_bad_frame.next = next_c;
field_combo.stats.rx_fifo_bad_frame.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.stats.rx_fifo_bad_frame.value <= 1'h0;
end else if(field_combo.stats.rx_fifo_bad_frame.load_next) begin
field_storage.stats.rx_fifo_bad_frame.value <= field_combo.stats.rx_fifo_bad_frame.next;
end
end
assign hwif_out.stats.rx_fifo_bad_frame.value = field_storage.stats.rx_fifo_bad_frame.value;
// Field: mac_t.stats.rx_fifo_good_frame
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.stats.rx_fifo_good_frame.value;
load_next_c = '0;
if(decoded_reg_strb.stats && !decoded_req_is_wr) begin // SW clear on read
next_c = '0;
load_next_c = '1;
end else if(hwif_in.stats.rx_fifo_good_frame.hwset) begin // HW Set
next_c = '1;
load_next_c = '1;
end
field_combo.stats.rx_fifo_good_frame.next = next_c;
field_combo.stats.rx_fifo_good_frame.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.stats.rx_fifo_good_frame.value <= 1'h0;
end else if(field_combo.stats.rx_fifo_good_frame.load_next) begin
field_storage.stats.rx_fifo_good_frame.value <= field_combo.stats.rx_fifo_good_frame.next;
end
end
assign hwif_out.stats.rx_fifo_good_frame.value = field_storage.stats.rx_fifo_good_frame.value;
//--------------------------------------------------------------------------
// Write response
//--------------------------------------------------------------------------
assign cpuif_wr_ack = decoded_req & decoded_req_is_wr;
// Writes are always granted with no error response
assign cpuif_wr_err = '0;
//--------------------------------------------------------------------------
// Readback
//--------------------------------------------------------------------------
logic readback_err;
logic readback_done;
logic [31:0] readback_data;
// Assign readback values to a flattened array
logic [31:0] readback_array[2];
assign readback_array[0][0:0] = (decoded_reg_strb.ctrl && !decoded_req_is_wr) ? field_storage.ctrl.tx_en.value : '0;
assign readback_array[0][1:1] = (decoded_reg_strb.ctrl && !decoded_req_is_wr) ? field_storage.ctrl.rx_en.value : '0;
assign readback_array[0][2:2] = (decoded_reg_strb.ctrl && !decoded_req_is_wr) ? field_storage.ctrl.phy_rstn.value : '0;
assign readback_array[0][7:3] = '0;
assign readback_array[0][15:8] = (decoded_reg_strb.ctrl && !decoded_req_is_wr) ? field_storage.ctrl.ifg.value : '0;
assign readback_array[0][31:16] = '0;
assign readback_array[1][0:0] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.tx_error_underflow.value : '0;
assign readback_array[1][1:1] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.tx_fifo_overflow.value : '0;
assign readback_array[1][2:2] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.tx_fifo_bad_frame.value : '0;
assign readback_array[1][3:3] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.tx_fifo_good_frame.value : '0;
assign readback_array[1][4:4] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.rx_error_bad_frame.value : '0;
assign readback_array[1][5:5] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.rx_error_bad_fcs.value : '0;
assign readback_array[1][6:6] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.rx_fifo_overflow.value : '0;
assign readback_array[1][7:7] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.rx_fifo_bad_frame.value : '0;
assign readback_array[1][8:8] = (decoded_reg_strb.stats && !decoded_req_is_wr) ? field_storage.stats.rx_fifo_good_frame.value : '0;
assign readback_array[1][31:9] = '0;
// Reduce the array
always_comb begin
automatic logic [31:0] readback_data_var;
readback_done = decoded_req & ~decoded_req_is_wr;
readback_err = '0;
readback_data_var = '0;
for(int i=0; i<2; i++) readback_data_var |= readback_array[i];
readback_data = readback_data_var;
end
assign cpuif_rd_ack = readback_done;
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;
endmodule

136
hw/super6502_fpga/src/sub/network_processor/src/regs/mac_t_pkg.sv
View File

@@ -1,136 +0,0 @@
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
package mac_t_pkg;
localparam MAC_T_DATA_WIDTH = 32;
localparam MAC_T_MIN_ADDR_WIDTH = 3;
typedef struct {
logic hwset;
} mac_t__stats__tx_error_underflow__in_t;
typedef struct {
logic hwset;
} mac_t__stats__tx_fifo_overflow__in_t;
typedef struct {
logic hwset;
} mac_t__stats__tx_fifo_bad_frame__in_t;
typedef struct {
logic hwset;
} mac_t__stats__tx_fifo_good_frame__in_t;
typedef struct {
logic hwset;
} mac_t__stats__rx_error_bad_frame__in_t;
typedef struct {
logic hwset;
} mac_t__stats__rx_error_bad_fcs__in_t;
typedef struct {
logic hwset;
} mac_t__stats__rx_fifo_overflow__in_t;
typedef struct {
logic hwset;
} mac_t__stats__rx_fifo_bad_frame__in_t;
typedef struct {
logic hwset;
} mac_t__stats__rx_fifo_good_frame__in_t;
typedef struct {
mac_t__stats__tx_error_underflow__in_t tx_error_underflow;
mac_t__stats__tx_fifo_overflow__in_t tx_fifo_overflow;
mac_t__stats__tx_fifo_bad_frame__in_t tx_fifo_bad_frame;
mac_t__stats__tx_fifo_good_frame__in_t tx_fifo_good_frame;
mac_t__stats__rx_error_bad_frame__in_t rx_error_bad_frame;
mac_t__stats__rx_error_bad_fcs__in_t rx_error_bad_fcs;
mac_t__stats__rx_fifo_overflow__in_t rx_fifo_overflow;
mac_t__stats__rx_fifo_bad_frame__in_t rx_fifo_bad_frame;
mac_t__stats__rx_fifo_good_frame__in_t rx_fifo_good_frame;
} mac_t__stats__in_t;
typedef struct {
mac_t__stats__in_t stats;
} mac_t__in_t;
typedef struct {
logic value;
} mac_t__ctrl__tx_en__out_t;
typedef struct {
logic value;
} mac_t__ctrl__rx_en__out_t;
typedef struct {
logic value;
} mac_t__ctrl__phy_rstn__out_t;
typedef struct {
logic [7:0] value;
} mac_t__ctrl__ifg__out_t;
typedef struct {
mac_t__ctrl__tx_en__out_t tx_en;
mac_t__ctrl__rx_en__out_t rx_en;
mac_t__ctrl__phy_rstn__out_t phy_rstn;
mac_t__ctrl__ifg__out_t ifg;
} mac_t__ctrl__out_t;
typedef struct {
logic value;
} mac_t__stats__tx_error_underflow__out_t;
typedef struct {
logic value;
} mac_t__stats__tx_fifo_overflow__out_t;
typedef struct {
logic value;
} mac_t__stats__tx_fifo_bad_frame__out_t;
typedef struct {
logic value;
} mac_t__stats__tx_fifo_good_frame__out_t;
typedef struct {
logic value;
} mac_t__stats__rx_error_bad_frame__out_t;
typedef struct {
logic value;
} mac_t__stats__rx_error_bad_fcs__out_t;
typedef struct {
logic value;
} mac_t__stats__rx_fifo_overflow__out_t;
typedef struct {
logic value;
} mac_t__stats__rx_fifo_bad_frame__out_t;
typedef struct {
logic value;
} mac_t__stats__rx_fifo_good_frame__out_t;
typedef struct {
mac_t__stats__tx_error_underflow__out_t tx_error_underflow;
mac_t__stats__tx_fifo_overflow__out_t tx_fifo_overflow;
mac_t__stats__tx_fifo_bad_frame__out_t tx_fifo_bad_frame;
mac_t__stats__tx_fifo_good_frame__out_t tx_fifo_good_frame;
mac_t__stats__rx_error_bad_frame__out_t rx_error_bad_frame;
mac_t__stats__rx_error_bad_fcs__out_t rx_error_bad_fcs;
mac_t__stats__rx_fifo_overflow__out_t rx_fifo_overflow;
mac_t__stats__rx_fifo_bad_frame__out_t rx_fifo_bad_frame;
mac_t__stats__rx_fifo_good_frame__out_t rx_fifo_good_frame;
} mac_t__stats__out_t;
typedef struct {
mac_t__ctrl__out_t ctrl;
mac_t__stats__out_t stats;
} mac_t__out_t;
endpackage

8
hw/super6502_fpga/src/sub/network_processor/src/regs/ntw_top_regfile_pkg.sv
View File

@@ -10,7 +10,7 @@ package ntw_top_regfile_pkg;
logic rd_ack; logic rd_ack;
logic [31:0] rd_data; logic [31:0] rd_data;
logic wr_ack; logic wr_ack;
} mac_t__external__in_t; } mac_regs__external__in_t;
typedef struct { typedef struct {
logic rd_ack; logic rd_ack;
@@ -19,7 +19,7 @@ package ntw_top_regfile_pkg;
} tcp_top_regfile__external__in_t; } tcp_top_regfile__external__in_t;
typedef struct { typedef struct {
mac_t__external__in_t mac; mac_regs__external__in_t mac;
tcp_top_regfile__external__in_t tcp_top; tcp_top_regfile__external__in_t tcp_top;
} ntw_top_regfile__in_t; } ntw_top_regfile__in_t;
@@ -29,7 +29,7 @@ package ntw_top_regfile_pkg;
logic req_is_wr; logic req_is_wr;
logic [31:0] wr_data; logic [31:0] wr_data;
logic [31:0] wr_biten; logic [31:0] wr_biten;
} mac_t__external__out_t; } mac_regs__external__out_t;
typedef struct { typedef struct {
logic req; logic req;
@@ -40,7 +40,7 @@ package ntw_top_regfile_pkg;
} tcp_top_regfile__external__out_t; } tcp_top_regfile__external__out_t;
typedef struct { typedef struct {
mac_t__external__out_t mac; mac_regs__external__out_t mac;
tcp_top_regfile__external__out_t tcp_top; tcp_top_regfile__external__out_t tcp_top;
} ntw_top_regfile__out_t; } ntw_top_regfile__out_t;
endpackage endpackage

2
hw/super6502_fpga/src/sub/network_processor/src/regs/ntw_top_regs.rdl
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@@ -1,4 +1,4 @@
addrmap ntw_top_regfile { addrmap ntw_top_regfile {
external mac_t mac; external mac_regs mac;
external tcp_top_regfile tcp_top; external tcp_top_regfile tcp_top;
}; };

2
hw/super6502_fpga/src/sub/network_processor/src/regs/run_precompile.sh
View File

@@ -1,4 +1,4 @@
peakrdl regblock -t tcp_top_regfile tcp_stream_regs.rdl tcp_top_regs.rdl -o . --cpuif passthrough peakrdl regblock -t tcp_top_regfile tcp_stream_regs.rdl tcp_top_regs.rdl -o . --cpuif passthrough
peakrdl regblock -t tcp_stream_regs tcp_stream_regs.rdl -o . --cpuif passthrough peakrdl regblock -t tcp_stream_regs tcp_stream_regs.rdl -o . --cpuif passthrough
peakrdl regblock -t mac_t mac_regs.rdl -o . --cpuif passthrough peakrdl regblock -t mac_regs mac_regs.rdl -o . --cpuif passthrough
peakrdl regblock -t ntw_top_regfile mac_regs.rdl tcp_stream_regs.rdl tcp_top_regs.rdl ntw_top_regs.rdl -o . --cpuif axi4-lite-flat peakrdl regblock -t ntw_top_regfile mac_regs.rdl tcp_stream_regs.rdl tcp_top_regs.rdl ntw_top_regs.rdl -o . --cpuif axi4-lite-flat