From b996d93c99384f5f0e7e1dcb270f78770813e7ac Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sat, 5 Mar 2022 16:38:12 -0600 Subject: [PATCH] Create quartus project --- hw/fpga/.gitignore | 70 +++++++++++++++++++++++++++++++++++++++++++ hw/fpga/super6502.qpf | 30 +++++++++++++++++++ hw/fpga/super6502.qsf | 51 +++++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+) create mode 100644 hw/fpga/.gitignore create mode 100644 hw/fpga/super6502.qpf create mode 100644 hw/fpga/super6502.qsf diff --git a/hw/fpga/.gitignore b/hw/fpga/.gitignore new file mode 100644 index 0000000..978cca1 --- /dev/null +++ b/hw/fpga/.gitignore @@ -0,0 +1,70 @@ +# Working with Altera Quartus II (Q2) and do proper versioning is not that easy +# but if you follow some rules it can be accomplished. :) +# This file should be placed into the main directory where the .qpf file is +# found. Generally Q2 throws all entities and so on in the main directory, but +# you can place all stuff also in separate folders. This approach is followed +# here. So when you create a new design create one or more folders where your +# entities will be located and put a .gitignore in there that overrides the +# ignores of this file, e.g. one single rule stating "!*" which allows now all +# type of files. When you add a MegaFunction or another entity to your design, +# simply add it to one of your private folders and Q2 will be happy and manage +# everything quite good. When you want to do versioning of your generated +# SOF/POF files, you can do this by redirecting the generated output to an own +# folder. To do this go to: +# "Assignments" +# -> "Settings +# -> "Compilation Process Settings" +# -> "Save project output files in specified directory" +# Now you can either place a .gitignore in the directory and allow the following +# list of types: +# !*.sof +# !*.pof +# or you create an own submodule in the folder to keep binary files out of your +# design. + +# Need to keep all HDL files +# *.vhd +# *.v + +# ignore Quartus II generated files +*_generation_script* +*_inst.vhd +*.bak +*.cmp +*.done +*.eqn +*.hex +*.html +*.jdi +*.jpg +# *.mif +*.pin +*.pof +*.ptf.* +*.qar +*.qarlog +*.qws +*.rpt +*.smsg +*.sof +*.sopc_builder +*.summary +*.tcl +*.txt # Explicitly add any text files used +*~ +*example* +*sopc_* +# *.sdc # I want those timing files + +# ignore Quartus II generated folders +*/db/ +*/incremental_db/ +*/simulation/ +*/timing/ +*/testbench/ +*/*_sim/ +incremental_db/ +db/ +_output_files/ +PLLJ_PLLSPE_INFO.txt + diff --git a/hw/fpga/super6502.qpf b/hw/fpga/super6502.qpf new file mode 100644 index 0000000..47ff9ae --- /dev/null +++ b/hw/fpga/super6502.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 16:36:56 March 05, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "16:36:56 March 05, 2022" + +# Revisions + +PROJECT_REVISION = "super6502" diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf new file mode 100644 index 0000000..cb21ad8 --- /dev/null +++ b/hw/fpga/super6502.qsf @@ -0,0 +1,51 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 16:36:56 March 05, 2022 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# super6502_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY super6502 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:36:56 MARCH 05, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation \ No newline at end of file