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Move data data segment to SDRAM

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This commit is contained in:
Byron Lathi
2022-03-17 15:05:25 -05:00
parent ee97c4cbaa
commit bbba99d099
2 changed files with 7 additions and 7 deletions
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6
sw/boot.s
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@@ -8,7 +8,7 @@
.import _main .import _main
.export __STARTUP__ : absolute = 1 ; Mark as startup .export __STARTUP__ : absolute = 1 ; Mark as startup
.import __RAM_START__, __RAM_SIZE__ ; Linker generated .import __SDRAM_START__, __SDRAM_SIZE__ ; Linker generated
.import copydata, zerobss, initlib, donelib .import copydata, zerobss, initlib, donelib
@@ -29,9 +29,9 @@ _init: LDX #$FF ; Initialize stack pointer to $01FF
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; Set cc65 argument stack pointer ; Set cc65 argument stack pointer
LDA #<(__RAM_START__ + __RAM_SIZE__) LDA #<(__SDRAM_START__ + __SDRAM_SIZE__)
STA sp STA sp
LDA #>(__RAM_START__ + __RAM_SIZE__) LDA #>(__SDRAM_START__ + __SDRAM_SIZE__)
STA sp+1 STA sp+1
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------

8
sw/link.ld
View File

@@ -2,15 +2,15 @@ MEMORY
{ {
ZP: start = $0, size = $100, type = rw, define = yes; ZP: start = $0, size = $100, type = rw, define = yes;
RAM: start = $0200, size = $3D00, type = rw, define = yes; RAM: start = $0200, size = $3D00, type = rw, define = yes;
SDRAM: start = $4000, size = $3ff00, type = rw, define = yes; SDRAM: start = $4000, size = $3ff0, type = rw, define = yes;
ROM: start = $8000, size = $8000, fill = yes, fillval = $ff, file = %O; ROM: start = $8000, size = $8000, fill = yes, fillval = $ff, file = %O;
} }
SEGMENTS { SEGMENTS {
ZEROPAGE: load = ZP, type = zp, define = yes; ZEROPAGE: load = ZP, type = zp, define = yes;
DATA: load = ROM, type = rw, define = yes, run = RAM; DATA: load = ROM, type = rw, define = yes, run = SDRAM;
BSS: load = RAM, type = bss, define = yes; BSS: load = SDRAM, type = bss, define = yes;
HEAP: load = RAM, type = bss, optional = yes; HEAP: load = SDRAM, type = bss, optional = yes;
STARTUP: load = ROM, type = ro; STARTUP: load = ROM, type = ro;
ONCE: load = ROM, type = ro, optional = yes; ONCE: load = ROM, type = ro, optional = yes;
CODE: load = ROM, type = ro; CODE: load = ROM, type = ro;