diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv
index 6f45efe..703ba35 100644
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -74,26 +74,26 @@ cpu_65c02 u_cpu(
 // Having the super6502 causes an infinite loop,
 // but just the rom works. Need to whittle down
 // which block is causing it.
-rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
-    .addr(w_cpu_addr[11:0]),
-    .clk(r_clk_2),
-    .data(w_cpu_data_from_dut)
-);
+// rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
+//     .addr(w_cpu_addr[11:0]),
+//     .clk(r_clk_2),
+//     .data(w_cpu_data_from_dut)
+// );
 
 //TODO: also this
-// super6502 u_dut(
-// 	.i_sysclk(r_sysclk),
-// 	.i_sdrclk(r_sdrclk),
-// 	.i_tACclk(r_sdrclk),
-// 	.clk_50(r_clk_50),
-// 	.clk_2(r_clk_2),
-// 	.button_reset(button_reset),
-// 	.cpu_resb(w_cpu_reset),
-// 	.cpu_addr(w_cpu_addr),
-// 	.cpu_data_out(w_cpu_data_from_dut),
-// 	// .cpu_data_in(w_cpu_data_from_cpu),
-// 	.cpu_rwb(~cpu_rwb)
-// );
+super6502 u_dut(
+	.i_sysclk(r_sysclk),
+	.i_sdrclk(r_sdrclk),
+	.i_tACclk(r_sdrclk),
+	.clk_50(r_clk_50),
+	.clk_2(r_clk_2),
+	.button_reset(button_reset),
+	.cpu_resb(w_cpu_reset),
+	.cpu_addr(w_cpu_addr),
+	.cpu_data_out(w_cpu_data_from_dut),
+	// .cpu_data_in(w_cpu_data_from_cpu),
+	.cpu_rwb(~cpu_rwb)
+);
 
 
 endmodule
\ No newline at end of file
diff --git a/hw/efinix_fpga/src/addr_decode.sv b/hw/efinix_fpga/src/addr_decode.sv
index b137400..9a131fb 100644
--- a/hw/efinix_fpga/src/addr_decode.sv
+++ b/hw/efinix_fpga/src/addr_decode.sv
@@ -1,17 +1,21 @@
 module addr_decode
 (
-    input [15:0] i_addr,
+    input logic [15:0] i_addr,
 
-    output o_rom_cs,
-    output o_leds_cs,
-    output o_timer_cs,
-    output o_multiplier_cs,
-    output o_divider_cs,
-    output o_uart_cs,
-    output o_spi_cs,
-    output o_sdram_cs
+    output logic o_rom_cs,
+    output logic o_leds_cs,
+    output logic o_timer_cs,
+    output logic o_multiplier_cs,
+    output logic o_divider_cs,
+    output logic o_uart_cs,
+    output logic o_spi_cs,
+    output logic o_sdram_cs
 );
 
+// assign o_rom_cs = '1;
+always_comb begin
+    o_rom_cs = (i_addr >= 16'hf000) ? 1 : 0;
+end
 assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff;
 assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffb;
 assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7;
diff --git a/hw/efinix_fpga/src/spi_controller.sv b/hw/efinix_fpga/src/spi_controller.sv
index 2d085e4..9f5c09d 100644
--- a/hw/efinix_fpga/src/spi_controller.sv
+++ b/hw/efinix_fpga/src/spi_controller.sv
@@ -90,6 +90,7 @@ always_comb begin
         1: o_data = r_input_data;
         2:;
         3: o_data = {active, r_control[6:0]};
+        default: o_data = 'x;
     endcase
 end
 
diff --git a/hw/efinix_fpga/src/super6502.sv b/hw/efinix_fpga/src/super6502.sv
index abe90d8..b0b1a49 100644
--- a/hw/efinix_fpga/src/super6502.sv
+++ b/hw/efinix_fpga/src/super6502.sv
@@ -81,17 +81,6 @@ logic w_divider_cs;
 logic w_uart_cs;
 logic w_spi_cs;
 
-addr_decode u_addr_decode(
-    .i_addr(cpu_addr),
-    .o_rom_cs(w_rom_cs),
-    .o_leds_cs(w_leds_cs),
-    .o_timer_cs(w_timer_cs),
-    .o_multiplier_cs(w_multiplier_cs),
-    .o_divider_cs(w_divider_cs),
-    .o_uart_cs(w_uart_cs),
-    .o_spi_cs(w_spi_cs),
-    .o_sdram_cs(w_sdram_cs)
-);
 
 logic [7:0] w_rom_data_out;
 logic [7:0] w_leds_data_out;
@@ -103,6 +92,16 @@ logic [7:0] w_spi_data_out;
 logic [7:0] w_sdram_data_out;
 
 always_comb begin
+    w_rom_cs = cpu_addr >= 16'hf000 && cpu_addr <= 16'hffff;
+    w_timer_cs = cpu_addr >= 16'heff8 && cpu_addr <= 16'heffb;
+    w_multiplier_cs = cpu_addr >= 16'heff0 && cpu_addr <= 16'heff7;
+    w_divider_cs = cpu_addr >= 16'hefe8 && cpu_addr <= 16'hefef;
+    w_uart_cs = cpu_addr >= 16'hefe6 && cpu_addr <= 16'hefe7;
+    w_spi_cs = cpu_addr >= 16'hefd8 && cpu_addr <= 16'hefdb;
+    w_leds_cs = cpu_addr == 16'hefff;
+    w_sdram_cs = cpu_addr < 16'he000;
+
+
     if (w_rom_cs)
         cpu_data_out = w_rom_data_out;
     else if (w_leds_cs)
diff --git a/hw/efinix_fpga/src/timer.sv b/hw/efinix_fpga/src/timer.sv
index fa7f743..abebef9 100644
--- a/hw/efinix_fpga/src/timer.sv
+++ b/hw/efinix_fpga/src/timer.sv
@@ -123,6 +123,8 @@ always_comb begin
             o_data = status;
         end
 
+        default: o_data = 'x;
+
     endcase
 end