From bdb3fc96d69fabce5f1edbc039d9b7f3fda1dd30 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Wed, 17 Jul 2024 21:18:07 -0700 Subject: [PATCH] Add new sd wrapper Wrapper is neccesary for the address offset and also because the controller will trigger on reads/writes to registers, but we need access to each byte of the 32 bit registers. The wrapper will need to somehow chose when to actually trigger the controller, maybe by having shadow registers? --- .gitmodules | 2 +- hw/super6502_fpga/sources.list | 37 ++-- hw/super6502_fpga/src/rtl/super_6502_fpga.sv | 18 +- .../sd_controller_wrapper.sv | 137 +++++++++++++ .../src/sub/{ => sd_controller_wrapper}/sdspi | 0 hw/super6502_fpga/super6502_fpga.xml | 194 +++++++++--------- sw/test_code/sd_controller_test/main.s | 116 +---------- 7 files changed, 261 insertions(+), 243 deletions(-) create mode 100644 hw/super6502_fpga/src/sub/sd_controller_wrapper/sd_controller_wrapper.sv rename hw/super6502_fpga/src/sub/{ => sd_controller_wrapper}/sdspi (100%) diff --git a/.gitmodules b/.gitmodules index 9f070bd..c68e2a0 100644 --- a/.gitmodules +++ b/.gitmodules @@ -14,5 +14,5 @@ path = hw/super6502_fpga/src/sub/wb2axip url = ../wb2axip.git [submodule "hw/super6502_fpga/src/sub/sdspi"] - path = hw/super6502_fpga/src/sub/sdspi + path = hw/super6502_fpga/src/sub/sd_controller_wrapper/sdspi url = ../sdspi.git diff --git a/hw/super6502_fpga/sources.list b/hw/super6502_fpga/sources.list index 5ab0581..9f8fa87 100644 --- a/hw/super6502_fpga/sources.list +++ b/hw/super6502_fpga/sources.list @@ -11,21 +11,22 @@ ip/sdram_controller/sdram_controller.v src/sub/wb2axip/rtl/axilxbar.v src/sub/wb2axip/rtl/addrdecode.v src/sub/wb2axip/rtl/skidbuffer.v -src/sub/sdspi/rtl/sdckgen.v -src/sub/sdspi/rtl/sddma_rxgears.v -src/sub/sdspi/rtl/sddma.v -src/sub/sdspi/rtl/sdrxframe.v -src/sub/sdspi/rtl/sdtxframe.v -src/sub/sdspi/rtl/sddma_s2mm.v -src/sub/sdspi/rtl/afifo.v -src/sub/sdspi/rtl/sddma_txgears.v -src/sub/sdspi/rtl/sdskid.v -src/sub/sdspi/rtl/sdfrontend.v -src/sub/sdspi/rtl/spicmd.v -src/sub/sdspi/rtl/sdaxil.v -src/sub/sdspi/rtl/sddma_mm2s.v -src/sub/sdspi/rtl/sdio_top.v -src/sub/sdspi/rtl/sdwb.v -src/sub/sdspi/rtl/sdio.v -src/sub/sdspi/rtl/sdcmd.v -src/sub/sdspi/rtl/sdfifo.v \ No newline at end of file +src/sub/sd_controller_wrapper/sd_controller_wrapper.sv +src/sub/sd_controller_wrapper/sdspi/rtl/sdckgen.v +src/sub/sd_controller_wrapper/sdspi/rtl/sddma_rxgears.v +src/sub/sd_controller_wrapper/sdspi/rtl/sddma.v +src/sub/sd_controller_wrapper/sdspi/rtl/sdrxframe.v +src/sub/sd_controller_wrapper/sdspi/rtl/sdtxframe.v +src/sub/sd_controller_wrapper/sdspi/rtl/sddma_s2mm.v +src/sub/sd_controller_wrapper/sdspi/rtl/afifo.v +src/sub/sd_controller_wrapper/sdspi/rtl/sddma_txgears.v +src/sub/sd_controller_wrapper/sdspi/rtl/sdskid.v +src/sub/sd_controller_wrapper/sdspi/rtl/sdfrontend.v +src/sub/sd_controller_wrapper/sdspi/rtl/spicmd.v +src/sub/sd_controller_wrapper/sdspi/rtl/sdaxil.v +src/sub/sd_controller_wrapper/sdspi/rtl/sddma_mm2s.v +src/sub/sd_controller_wrapper/sdspi/rtl/sdio_top.v +src/sub/sd_controller_wrapper/sdspi/rtl/sdwb.v +src/sub/sd_controller_wrapper/sdspi/rtl/sdio.v +src/sub/sd_controller_wrapper/sdspi/rtl/sdcmd.v +src/sub/sd_controller_wrapper/sdspi/rtl/sdfifo.v \ No newline at end of file diff --git a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv index 175346f..efb88a2 100644 --- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv +++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv @@ -430,24 +430,16 @@ sdram_controller u_sdram_controller( logic sd_irq; -sdio_top #( - .NUMIO (1), // board as it stands is in 1 bit mode - .ADDRESS_WIDTH (32), - .DW (32), - .OPT_DMA (1), - .OPT_EMMC (0), - .OPT_SERDES (0), - .OPT_DDR (0), - .OPT_1P8V (0) // doesn't really matter but we don't need it +sd_controller_wrapper #( + .NUMIO (1), // board as it stands is in 1 bit mode + .BASE_ADDRESS (32'h0000E000) ) u_sdio_top ( .i_clk (i_sysclk), .i_reset (~master_resetn), - .i_hsclk ('0), // Not using serdes .S_AXIL_AWVALID (sd_controller_ctrl_AWVALID), .S_AXIL_AWREADY (sd_controller_ctrl_AWREADY), .S_AXIL_AWADDR (sd_controller_ctrl_AWADDR), - .S_AXIL_AWPROT ('0), .S_AXIL_WVALID (sd_controller_ctrl_WVALID), .S_AXIL_WREADY (sd_controller_ctrl_WREADY), .S_AXIL_WDATA (sd_controller_ctrl_WDATA), @@ -458,7 +450,6 @@ sdio_top #( .S_AXIL_ARVALID (sd_controller_ctrl_ARVALID), .S_AXIL_ARREADY (sd_controller_ctrl_ARREADY), .S_AXIL_ARADDR (sd_controller_ctrl_ARADDR), - .S_AXIL_ARPROT ('0), .S_AXIL_RVALID (sd_controller_ctrl_RVALID), .S_AXIL_RREADY (sd_controller_ctrl_RREADY), .S_AXIL_RDATA (sd_controller_ctrl_RDATA), @@ -467,7 +458,6 @@ sdio_top #( .M_AXI_AWVALID (sd_controller_dma_AWVALID), .M_AXI_AWREADY (sd_controller_dma_AWREADY), .M_AXI_AWADDR (sd_controller_dma_AWADDR), - .M_AXI_AWPROT (), .M_AXI_WVALID (sd_controller_dma_WVALID), .M_AXI_WREADY (sd_controller_dma_WREADY), .M_AXI_WDATA (sd_controller_dma_WDATA), @@ -478,7 +468,6 @@ sdio_top #( .M_AXI_ARVALID (sd_controller_dma_ARVALID), .M_AXI_ARREADY (sd_controller_dma_ARREADY), .M_AXI_ARADDR (sd_controller_dma_ARADDR), - .M_AXI_ARPROT (), .M_AXI_RVALID (sd_controller_dma_RVALID), .M_AXI_RREADY (sd_controller_dma_RREADY), .M_AXI_RDATA (sd_controller_dma_RDATA), @@ -491,7 +480,6 @@ sdio_top #( .o_cmd (o_sd_cmd), .io_cmd_tristate (o_sd_cmd_oe), .o_ck (o_sd_clk), - .i_ds ('0), //emmc, don't care .i_card_detect (i_sd_cd), .o_int (sd_irq) ); diff --git a/hw/super6502_fpga/src/sub/sd_controller_wrapper/sd_controller_wrapper.sv b/hw/super6502_fpga/src/sub/sd_controller_wrapper/sd_controller_wrapper.sv new file mode 100644 index 0000000..ee799ae --- /dev/null +++ b/hw/super6502_fpga/src/sub/sd_controller_wrapper/sd_controller_wrapper.sv @@ -0,0 +1,137 @@ +module sd_controller_wrapper #( + parameter NUMIO=4, + parameter BASE_ADDRESS=32'h00000000 +)( + input wire i_clk, + input wire i_reset, + + input wire S_AXIL_AWVALID, + output wire S_AXIL_AWREADY, + input wire [31:0] S_AXIL_AWADDR, + + input wire S_AXIL_WVALID, + output wire S_AXIL_WREADY, + input wire [31:0] S_AXIL_WDATA, + input wire [3:0] S_AXIL_WSTRB, + + output wire S_AXIL_BVALID, + input wire S_AXIL_BREADY, + output wire [1:0] S_AXIL_BRESP, + + input wire S_AXIL_ARVALID, + output wire S_AXIL_ARREADY, + input wire [31:0] S_AXIL_ARADDR, + + output wire S_AXIL_RVALID, + input wire S_AXIL_RREADY, + output wire [31:0] S_AXIL_RDATA, + output wire [1:0] S_AXIL_RRESP, + + output wire M_AXI_AWVALID, + input wire M_AXI_AWREADY, + output wire [31:0] M_AXI_AWADDR, + + output wire M_AXI_WVALID, + input wire M_AXI_WREADY, + output wire [31:0] M_AXI_WDATA, + output wire [3:0] M_AXI_WSTRB, + output wire M_AXI_WLAST, + + input wire M_AXI_BVALID, + output wire M_AXI_BREADY, + input wire [1:0] M_AXI_BRESP, + + output wire M_AXI_ARVALID, + input wire M_AXI_ARREADY, + output wire [31:0] M_AXI_ARADDR, + + + input wire M_AXI_RVALID, + output wire M_AXI_RREADY, + input wire [31:0] M_AXI_RDATA, + input wire [1:0] M_AXI_RRESP, + + output wire o_ck, + output wire io_cmd_tristate, + output wire o_cmd, + input wire i_cmd, + + output wire [NUMIO-1:0] io_dat_tristate, + output wire [NUMIO-1:0] o_dat, + input wire [NUMIO-1:0] i_dat, + + input wire i_card_detect, + output wire o_hwreset_n, + output wire o_1p8v, + output wire o_int +); + + + +sdio_top #( + .NUMIO (NUMIO), // board as it stands is in 1 bit mode + .ADDRESS_WIDTH (32), + .DW (32), + .OPT_DMA (1), + .OPT_EMMC (0), + .OPT_SERDES (0), + .OPT_DDR (0), + .OPT_1P8V (0) // doesn't really matter but we don't need it +) u_sdio_top ( + .i_clk (i_clk), + .i_reset (i_reset), + .i_hsclk ('0), // Not using serdes + + .S_AXIL_AWVALID (S_AXIL_AWVALID), + .S_AXIL_AWREADY (S_AXIL_AWREADY), + .S_AXIL_AWADDR (S_AXIL_AWADDR-BASE_ADDRESS), + .S_AXIL_AWPROT ('0), + .S_AXIL_WVALID (S_AXIL_WVALID), + .S_AXIL_WREADY (S_AXIL_WREADY), + .S_AXIL_WDATA (S_AXIL_WDATA), + .S_AXIL_WSTRB (S_AXIL_WSTRB), + .S_AXIL_BVALID (S_AXIL_BVALID), + .S_AXIL_BREADY (S_AXIL_BREADY), + .S_AXIL_BRESP (S_AXIL_BRESP), + .S_AXIL_ARVALID (S_AXIL_ARVALID), + .S_AXIL_ARREADY (S_AXIL_ARREADY), + .S_AXIL_ARADDR (S_AXIL_ARADDR-BASE_ADDRESS), + .S_AXIL_ARPROT ('0), + .S_AXIL_RVALID (S_AXIL_RVALID), + .S_AXIL_RREADY (S_AXIL_RREADY), + .S_AXIL_RDATA (S_AXIL_RDATA), + .S_AXIL_RRESP (S_AXIL_RRESP), + + .M_AXI_AWVALID (M_AXI_AWVALID), + .M_AXI_AWREADY (M_AXI_AWREADY), + .M_AXI_AWADDR (M_AXI_AWADDR), + .M_AXI_AWPROT (), + .M_AXI_WVALID (M_AXI_WVALID), + .M_AXI_WREADY (M_AXI_WREADY), + .M_AXI_WDATA (M_AXI_WDATA), + .M_AXI_WSTRB (M_AXI_WSTRB), + .M_AXI_BVALID (M_AXI_BVALID), + .M_AXI_BREADY (M_AXI_BREADY), + .M_AXI_BRESP (M_AXI_BRESP), + .M_AXI_ARVALID (M_AXI_ARVALID), + .M_AXI_ARREADY (M_AXI_ARREADY), + .M_AXI_ARADDR (M_AXI_ARADDR), + .M_AXI_ARPROT (), + .M_AXI_RVALID (M_AXI_RVALID), + .M_AXI_RREADY (M_AXI_RREADY), + .M_AXI_RDATA (M_AXI_RDATA), + .M_AXI_RRESP (M_AXI_RRESP), + + .i_dat (i_dat), + .o_dat (o_dat), + .io_dat_tristate (io_dat_tristate), + .i_cmd (i_cmd), + .o_cmd (o_cmd), + .io_cmd_tristate (io_cmd_tristate), + .o_ck (o_ck), + .i_ds ('0), //emmc, don't care + .i_card_detect (i_card_detect), + .o_int (o_int) +); + +endmodule \ No newline at end of file diff --git a/hw/super6502_fpga/src/sub/sdspi b/hw/super6502_fpga/src/sub/sd_controller_wrapper/sdspi similarity index 100% rename from hw/super6502_fpga/src/sub/sdspi rename to hw/super6502_fpga/src/sub/sd_controller_wrapper/sdspi diff --git a/hw/super6502_fpga/super6502_fpga.xml b/hw/super6502_fpga/super6502_fpga.xml index 977f6b7..452ed76 100644 --- a/hw/super6502_fpga/super6502_fpga.xml +++ b/hw/super6502_fpga/super6502_fpga.xml @@ -1,115 +1,115 @@ - - + - - - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - + + + - + \ No newline at end of file diff --git a/sw/test_code/sd_controller_test/main.s b/sw/test_code/sd_controller_test/main.s index 8576a2a..56515eb 100644 --- a/sw/test_code/sd_controller_test/main.s +++ b/sw/test_code/sd_controller_test/main.s @@ -7,9 +7,11 @@ .addr _irq_int ; IRQ/BRK vector SD_CONTROLLER = $e000 +SD_CMD = SD_CONTROLLER SD_ARG = SD_CONTROLLER + $4 -SD_RESP = SD_CONTROLLER + $10 -CLK_DIV = $20 +SD_FIFO_0 = SD_CONTROLLER + $8 +SD_FIFO_2 = SD_CONTROLLER + $C +SD_PHY = SD_CONTROLLER + $10 SD_DMA_BASE = SD_CONTROLLER + $28 SD_DMA_STAT_CTRL = SD_CONTROLLER + $2C @@ -26,114 +28,4 @@ _init: ldx #$ff txs - lda #$00 - sta SD_CONTROLLER - - lda #$aa - sta SD_ARG - lda #$01 - sta SD_ARG+1 - lda #$00 - sta SD_ARG+2 - sta SD_ARG+3 - lda #$08 - sta SD_CONTROLLER - jsr delay - - lda #55 - sta SD_CONTROLLER - jsr delay - lda #41 - sta SD_CONTROLLER - jsr delay - -@acmd41: - lda #55 - sta SD_CONTROLLER - - jsr delay - - lda #$80 - sta SD_ARG+1 - lda #$ff - sta SD_ARG+2 - lda #$40 - sta SD_ARG+3 - lda #41 - sta SD_CONTROLLER - - jsr delay - - lda SD_RESP+3 - bmi card_ready - - - ldx #$10 -@loop: dex - bne @loop - - bra @acmd41 - -card_ready: - lda #2 - sta SD_CONTROLLER - - jsr delay - - lda #3 - sta SD_CONTROLLER - - jsr delay - - lda SD_RESP - sta rca - lda SD_RESP+1 - sta rca+1 - lda SD_RESP+2 - sta rca+2 - lda SD_RESP+3 - sta rca+3 - - lda rca - sta SD_ARG - lda rca+1 - sta SD_ARG+1 - lda rca+2 - sta SD_ARG+2 - lda rca+3 - sta SD_ARG+3 - lda #7 - sta SD_CONTROLLER - - jsr delay - - lda #17 - sta SD_CONTROLLER - - lda #$10 - sta SD_DMA_BASE + 1 - lda #1 - sta SD_DMA_STAT_CTRL - -@poll: lda SD_DMA_STAT_CTRL+2 - cmp #$1 - bne @poll - stz SD_DMA_STAT_CTRL - - lda $1000 - lda $1001 - lda $1002 - lda $1003 - - @end: bra @end - -delay: - nop - nop - nop - nop - nop - nop - nop - rts \ No newline at end of file