diff --git a/hw/fpga/memory_mapper.sv b/hw/fpga/memory_mapper.sv
index 193911a..00858d7 100644
--- a/hw/fpga/memory_mapper.sv
+++ b/hw/fpga/memory_mapper.sv
@@ -7,6 +7,7 @@
 
 module memory_mapper(
 	input clk,
+	input rst,
 
 	input rw,
 	input cs,
@@ -29,15 +30,19 @@ logic MM;
 
 
 always_ff @(posedge clk) begin
-	if (MM_cs & ~rw) begin					// can't read MM but do you really need too?
-		MM = |data_in;
-	end
+    if (rst) begin
+        MM <= '0;
+    end else begin
+        if (MM_cs & ~rw) begin					// can't read MM but do you really need too?
+            MM = |data_in;
+        end
 
-	if (cs & ~rw) begin					// write to registers
-		RAM[RS] <= data_in;
-	end else if (cs & rw) begin			// read registers
-		data_out <= RAM[RS];
-	end
+        if (cs & ~rw) begin					// write to registers
+            RAM[RS] <= data_in;
+        end else if (cs & rw) begin			// read registers
+            data_out <= RAM[RS];
+        end
+    end
 end
 
 
diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv
index 01cf4b8..f4587f3 100644
--- a/hw/fpga/super6502.sv
+++ b/hw/fpga/super6502.sv
@@ -94,6 +94,7 @@ assign mm_address = {mm_MO, cpu_addr[11:0]};
 
 memory_mapper memory_mapper(
 	.clk(clk),
+    .rst(rst),
 	.rw(cpu_rwb),
 	.cs(mm_cs1),
 	.MM_cs(mm_cs2),