From be68b4c9f930ea106da1b747121a6266c450c7bf Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 24 Sep 2023 14:53:38 -0700 Subject: [PATCH] Change sdrclk and sysclk to have aligned rising edges --- hw/efinix_fpga/simulation/src/sim_top.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv index 41bd4f0..bab1306 100644 --- a/hw/efinix_fpga/simulation/src/sim_top.sv +++ b/hw/efinix_fpga/simulation/src/sim_top.sv @@ -16,7 +16,7 @@ end // clk_200 initial begin - r_sdrclk <= '0; + r_sdrclk <= '1; forever begin #2.5 r_sdrclk <= ~r_sdrclk; end