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Change sdrclk and sysclk to have aligned rising edges

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Byron Lathi
2023-09-24 14:53:38 -07:00
parent 3fcfa4d3ac
commit be68b4c9f9
1 changed files with 1 additions and 1 deletions
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2
hw/efinix_fpga/simulation/src/sim_top.sv
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@@ -16,7 +16,7 @@ end
// clk_200 // clk_200
initial begin initial begin
r_sdrclk <= '0; r_sdrclk <= '1;
forever begin forever begin
#2.5 r_sdrclk <= ~r_sdrclk; #2.5 r_sdrclk <= ~r_sdrclk;
end end