Gate rdy behind sdram_cs #28

2023-09-25 23:45:23 -07:00
parent 4ee21f23b6
commit c2dd5d616b
2 changed files with 4 additions and 2 deletions
--- a/hw/efinix_fpga/src/sdram_adapter.sv
+++ b/hw/efinix_fpga/src/sdram_adapter.sv
@@ -104,7 +104,7 @@ end

 logic r_wait;
 logic _r_wait;
-assign o_wait = r_wait;
+assign o_wait = r_wait & i_cs;

 // we need to assert rdy low until a falling edge if a reset happens