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Gate rdy behind sdram_cs #28

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This commit is contained in:
Byron Lathi
2023-09-25 23:45:23 -07:00
parent 4ee21f23b6
commit c2dd5d616b
2 changed files with 4 additions and 2 deletions
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4
hw/efinix_fpga/simulation/src/sim_top.sv
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@@ -56,6 +56,7 @@ end
logic w_cpu_reset; logic w_cpu_reset;
logic [15:0] w_cpu_addr; logic [15:0] w_cpu_addr;
logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut; logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut;
logic w_cpu_rdy;
logic w_cpu_we; logic w_cpu_we;
logic w_cpu_phi2; logic w_cpu_phi2;
@@ -64,7 +65,7 @@ cpu_65c02 u_cpu(
.phi2(w_cpu_phi2), .phi2(w_cpu_phi2),
.reset(~w_cpu_reset), .reset(~w_cpu_reset),
.AB(w_cpu_addr), .AB(w_cpu_addr),
.RDY('1), .RDY(w_cpu_rdy),
.IRQ('0), .IRQ('0),
.NMI('0), .NMI('0),
.DI_s1(w_cpu_data_from_dut), .DI_s1(w_cpu_data_from_dut),
@@ -95,6 +96,7 @@ super6502 u_dut(
.cpu_data_out(w_cpu_data_from_dut), .cpu_data_out(w_cpu_data_from_dut),
.cpu_data_in(w_cpu_data_from_cpu), .cpu_data_in(w_cpu_data_from_cpu),
.cpu_rwb(~w_cpu_we), .cpu_rwb(~w_cpu_we),
.cpu_rdy(w_cpu_rdy),
.cpu_phi2(w_cpu_phi2), .cpu_phi2(w_cpu_phi2),
.o_sdr_CKE(w_sdr_CKE), .o_sdr_CKE(w_sdr_CKE),

2
hw/efinix_fpga/src/sdram_adapter.sv
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@@ -104,7 +104,7 @@ end
logic r_wait; logic r_wait;
logic _r_wait; logic _r_wait;
assign o_wait = r_wait; assign o_wait = r_wait & i_cs;
// we need to assert rdy low until a falling edge if a reset happens // we need to assert rdy low until a falling edge if a reset happens