From 5c32fe808ed726c60d72ecea246d72f6acb37973 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Fri, 18 Mar 2022 01:27:55 +0000 Subject: [PATCH] Add board-io, replace sevenseg in sw --- hw/fpga/addr_decode.sv | 4 +++- hw/fpga/board_io.sv | 27 +++++++++++++++++++++++++++ hw/fpga/hvl/cs_testbench.sv | 8 +++++++- hw/fpga/super6502.sv | 21 ++++++++++++++++++++- sw/{sevenseg.h => board_io.h} | 8 ++++++-- sw/{sevenseg.s => board_io.s} | 16 ++++++++++++++++ sw/io.inc65 | 3 +++ sw/irq.c | 1 - sw/main.c | 7 ++++++- sw/tests/test_main.c | 2 +- 10 files changed, 89 insertions(+), 8 deletions(-) create mode 100644 hw/fpga/board_io.sv rename sw/{sevenseg.h => board_io.h} (66%) rename sw/{sevenseg.s => board_io.s} (79%) diff --git a/hw/fpga/addr_decode.sv b/hw/fpga/addr_decode.sv index c791668..f1a8a9f 100644 --- a/hw/fpga/addr_decode.sv +++ b/hw/fpga/addr_decode.sv @@ -5,7 +5,8 @@ module addr_decode( output logic rom_cs, output logic hex_cs, output logic uart_cs, - output logic irq_cs + output logic irq_cs, + output logic board_io_cs ); assign rom_cs = addr >= 16'h8000; @@ -13,6 +14,7 @@ assign ram_cs = addr < 16'h4000; assign sdram_cs = addr >= 16'h4000 && addr < 16'h7ff0; assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4; assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6; +assign board_io_cs = addr == 16'h7ff6; assign irq_cs = addr == 16'h7fff; endmodule diff --git a/hw/fpga/board_io.sv b/hw/fpga/board_io.sv new file mode 100644 index 0000000..d83d1b3 --- /dev/null +++ b/hw/fpga/board_io.sv @@ -0,0 +1,27 @@ +module board_io( + input clk, + input rst, + + input rw, + + input [7:0] data_in, + input cs, + input [1:0] addr, + + output logic [7:0] data_out, + + output logic [7:0] led, + input [7:0] sw +); + +assign data_out = sw; + + +always_ff @(posedge clk) begin + if (rst) + led = '0; + if (~rw & cs) + led <= data_in; +end + +endmodule diff --git a/hw/fpga/hvl/cs_testbench.sv b/hw/fpga/hvl/cs_testbench.sv index e13a923..5fd187b 100644 --- a/hw/fpga/hvl/cs_testbench.sv +++ b/hw/fpga/hvl/cs_testbench.sv @@ -9,10 +9,11 @@ logic ram_cs; logic sdram_cs; logic rom_cs; logic hex_cs; +logic board_io_cs; logic uart_cs; logic irq_cs; -int cs_count = ram_cs + sdram_cs + rom_cs + hex_cs + uart_cs; +int cs_count = ram_cs + sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs; addr_decode dut(.*); @@ -44,6 +45,11 @@ initial begin : TEST_VECTORS else $error("Bad CS! addr=%4x should have uart_cs!", addr); end + if (i == 16'h7ff6) begin + assert(board_io_cs == '1) + else + $error("Bad CS! addr=%4x should have board_io_cs!", addr); + end if (i == 16'h7fff) begin assert(irq_cs == '1) else diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv index 8b6247d..af501d3 100644 --- a/hw/fpga/super6502.sv +++ b/hw/fpga/super6502.sv @@ -26,6 +26,9 @@ module super6502( input logic UART_RXD, output logic UART_TXD, + input [7:0] SW, + output [7:0] LED, + ///////// SDRAM ///////// output DRAM_CLK, output DRAM_CKE, @@ -57,6 +60,7 @@ logic [7:0] ram_data_out; logic [7:0] sdram_data_out; logic [7:0] uart_data_out; logic [7:0] irq_data_out; +logic [7:0] board_io_data_out; logic ram_cs; logic sdram_cs; @@ -64,6 +68,7 @@ logic rom_cs; logic hex_cs; logic uart_cs; logic irq_cs; +logic board_io_cs; cpu_clk cpu_clk( .inclk0(clk_50), @@ -88,7 +93,8 @@ addr_decode decode( .rom_cs(rom_cs), .hex_cs(hex_cs), .uart_cs(uart_cs), - .irq_cs(irq_cs) + .irq_cs(irq_cs), + .board_io_cs(board_io_cs) ); @@ -103,6 +109,8 @@ always_comb begin cpu_data_out = uart_data_out; else if (irq_cs) cpu_data_out = irq_data_out; + else if (board_io_cs) + cpu_data_out = board_io_data_out; else cpu_data_out = 'x; end @@ -157,6 +165,17 @@ SevenSeg segs( .HEX0(HEX0), .HEX1(HEX1), .HEX2(HEX2), .HEX3(HEX3), .HEX4(HEX4), .HEX5(HEX5) ); +board_io board_io( + .clk(clk), + .rst(rst), + .rw(cpu_rwb), + .data_in(cpu_data_in), + .data_out(board_io_data_out), + .cs(board_io_cs), + .led(LED), + .sw(SW) +); + logic uart_irq; uart uart( diff --git a/sw/sevenseg.h b/sw/board_io.h similarity index 66% rename from sw/sevenseg.h rename to sw/board_io.h index a2b2175..c55c7a5 100644 --- a/sw/sevenseg.h +++ b/sw/board_io.h @@ -1,5 +1,5 @@ -#ifndef _SEVEN_SEG -#define _SEVEN_SEG +#ifndef _BOARD_IO_H +#define _BOARD_IO_H #include @@ -9,4 +9,8 @@ uint8_t hex_set_24(uint32_t val); void hex_enable(uint8_t mask); +uint8_t sw_read(); + +void led_set(uint8_t val); + #endif \ No newline at end of file diff --git a/sw/sevenseg.s b/sw/board_io.s similarity index 79% rename from sw/sevenseg.s rename to sw/board_io.s index 6b9efc6..95656fe 100644 --- a/sw/sevenseg.s +++ b/sw/board_io.s @@ -6,6 +6,8 @@ .export _hex_set_16 .export _hex_set_24 .export _hex_enable +.export _sw_read +.export _led_set .autoimport on @@ -52,4 +54,18 @@ _hex_set_24: ; Set the mask for seven seg enables _hex_enable: sta SEVEN_SEG+3 + rts + +; @out A: The Value of the switches +; Reads the current values of the switches. +_sw_read: + lda SW + ldx #$0 + rts + +; @in A: val +; @out A: 0 for success, 1 for failure +; Sets the LEDs +_led_set: + sta LED rts \ No newline at end of file diff --git a/sw/io.inc65 b/sw/io.inc65 index f7f3155..61b079b 100644 --- a/sw/io.inc65 +++ b/sw/io.inc65 @@ -5,4 +5,7 @@ UART_TXB = UART UART_RXB = UART UART_STATUS = UART + 1 +LED = $7ff6 +SW = LED + IRQ_STATUS = $7fff diff --git a/sw/irq.c b/sw/irq.c index 04708a0..f1baddc 100644 --- a/sw/irq.c +++ b/sw/irq.c @@ -4,7 +4,6 @@ #include "interrupt.h" #include "uart.h" -#include "sevenseg.h" char lastchar; diff --git a/sw/main.c b/sw/main.c index b1830d0..1979789 100644 --- a/sw/main.c +++ b/sw/main.c @@ -1,11 +1,12 @@ #include #include -#include "sevenseg.h" +#include "board_io.h" #include "uart.h" int main() { int i; + uint8_t sw; char s[16]; s[15] = 0; @@ -13,6 +14,10 @@ int main() { cprintf("Hello, world!\n"); while (1) { + + sw = sw_read(); + led_set(sw); + cscanf("%15s", s); cprintf("\n"); for (i = 0; i < 16; i++) diff --git a/sw/tests/test_main.c b/sw/tests/test_main.c index 564fea6..0ce03a9 100644 --- a/sw/tests/test_main.c +++ b/sw/tests/test_main.c @@ -1,6 +1,6 @@ #include -#include "sevenseg.h" +#include "board_io.h" #include "uart.h" #include "interrupt.h"