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Refactor makefile, update verilog-sd-emulator

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Byron Lathi
2023-09-29 23:48:28 -07:00
parent 29aa369b33
commit cc32430f2a
4 changed files with 28 additions and 5 deletions
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8
hw/efinix_fpga/simulation/Makefile
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@@ -16,7 +16,13 @@ TARGET=sim_top
INIT_MEM=init_hex.mem
FLAGS=-DSIM -DRTL_SIM
all: $(INIT_MEM)
all: sim
.PHONY: sim
sim: $(TARGET)
vvp $(TARGET) -fst
$(TARGET): $(INIT_MEM) $(SRCS)
iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
$(INIT_MEM):