From cd11670fb17ef20f7038bb09bdc0be60e2e6ac5a Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 10 Apr 2022 17:54:08 -0500 Subject: [PATCH] Add sd controller to top level Also adds the logic required for the bidirectional sd lines and attaches the controller to the cpu. --- hw/fpga/super6502.qsf | 35 ++++++++++++++++++++++++++++++++++- hw/fpga/super6502.sv | 36 +++++++++++++++++++++++++++++++++--- 2 files changed, 67 insertions(+), 4 deletions(-) diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf index bd10e36..191ee02 100644 --- a/hw/fpga/super6502.qsf +++ b/hw/fpga/super6502.qsf @@ -188,7 +188,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_sob set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_sync set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_50 set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp2.stp +set_global_assignment -name USE_SIGNALTAP_FILE output_files/sd.stp set_location_assignment PIN_F20 -to HEX4[6] set_location_assignment PIN_F19 -to HEX4[5] set_location_assignment PIN_H19 -to HEX4[4] @@ -205,6 +205,20 @@ set_location_assignment PIN_F18 -to HEX4[0] set_location_assignment PIN_E20 -to HEX4[1] set_location_assignment PIN_AB5 -to UART_RXD set_location_assignment PIN_AB6 -to UART_TXD +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] @@ -367,4 +381,23 @@ set_global_assignment -name SYSTEMVERILOG_FILE SevenSeg.sv set_global_assignment -name QIP_FILE cpu_clk.qip set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp set_global_assignment -name SIGNALTAP_FILE output_files/stp2.stp +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[11] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[12] +set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv index fdfdafa..1e2009f 100644 --- a/hw/fpga/super6502.sv +++ b/hw/fpga/super6502.sv @@ -26,8 +26,10 @@ module super6502( input logic UART_RXD, output logic UART_TXD, - input [7:0] SW, - output [7:0] LED, + input [7:0] SW, + output logic [7:0] LED, + + inout logic [15: 0] ARDUINO_IO, ///////// SDRAM ///////// output DRAM_CLK, @@ -54,6 +56,16 @@ assign cpu_data_in = cpu_data; logic [7:0] cpu_data_out; assign cpu_data = cpu_rwb ? cpu_data_out : 'z; +logic o_sd_cmd, i_sd_cmd; +logic o_sd_data, i_sd_data; + +assign ARDUINO_IO[11] = o_sd_cmd ? 1'bz : 1'b0; +assign ARDUINO_IO[12] = o_sd_data ? 1'bz : 1'b0; +assign ARDUINO_IO[13] = cpu_phi2; +assign ARDUINO_IO[6] = 1'b1; + +assign i_sd_cmd = ARDUINO_IO[11]; +assign i_sd_data = ARDUINO_IO[12]; logic [7:0] rom_data_out; logic [7:0] sdram_data_out; @@ -70,6 +82,7 @@ logic irq_cs; logic board_io_cs; logic mm_cs1; logic mm_cs2; +logic sd_cs; cpu_clk cpu_clk( .inclk0(clk_50), @@ -114,7 +127,8 @@ addr_decode decode( .irq_cs(irq_cs), .board_io_cs(board_io_cs), .mm_cs1(mm_cs1), - .mm_cs2(mm_cs2) + .mm_cs2(mm_cs2), + .sd_cs(sd_cs) ); @@ -204,6 +218,22 @@ uart uart( .data_out(uart_data_out) ); +sd_controller sd_controller( + .clk(clk), + .sd_clk(cpu_phi2), + .rst(rst), + .addr(cpu_addr[2:0]), + .data(cpu_data_in), + .cs(sd_cs), + .rw(cpu_rwb), + + .i_sd_cmd(i_sd_cmd), + .o_sd_cmd(o_sd_cmd), + + .i_sd_data(i_sd_data), + .o_sd_data(o_sd_data) +); + always_ff @(posedge clk_50) begin if (rst) irq_data_out <= '0;