From cd1dfa39cb4c21abbb2e7896f3341997b15e873f Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 3 Mar 2024 09:45:04 -0800 Subject: [PATCH] Fix PLL settings, add cpu output clock --- hw/super6502_fpga/src/rtl/super_6502_fpga.sv | 4 ++-- hw/super6502_fpga/super6502_fpga.peri.xml | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv index 13b9ae4..62429b3 100644 --- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv +++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv @@ -21,14 +21,14 @@ module super6502_fpga( output logic o_cpu0_irqb, output logic o_cpu0_nmib, output logic o_cpu0_rdy, - output logic o_cpu0_reset + output logic o_cpu0_reset, + output logic o_clk_phi2 ); localparam ADDR_WIDTH = 32; localparam DATA_WIDTH = 32; - assign pll_cpu_reset = '1; assign o_pll_reset = '1; diff --git a/hw/super6502_fpga/super6502_fpga.peri.xml b/hw/super6502_fpga/super6502_fpga.peri.xml index 6be3434..a664a30 100644 --- a/hw/super6502_fpga/super6502_fpga.peri.xml +++ b/hw/super6502_fpga/super6502_fpga.peri.xml @@ -1,5 +1,5 @@ - + @@ -143,11 +143,11 @@ - - - - - + + + + +