Add hex drivers

hw/fpga/super6502.sv

@@ -1,7 +1,7 @@
 
 module super6502(
-    input                   clk,
-    input   logic           rst,
+    input                   clk_50,
+    input   logic           rst_n,
     
     input   logic [15:0]    cpu_addr,
     inout   logic [7:0]     cpu_data,
@@ -18,9 +18,15 @@ module super6502(
     output  logic           cpu_irqb,
     output  logic           cpu_phi2,
     output  logic           cpu_be,
-    output  logic           cpu_nmib
+    output  logic           cpu_nmib,
+    
+    output logic [6:0] HEX0, HEX1, HEX2, HEX3
   );
   
+logic rst;
+assign rst = ~rst_n;
+
+logic clk;
 
 logic [7:0] cpu_data_in;
 assign cpu_data_in = cpu_data;
@@ -29,19 +35,23 @@ logic [7:0] cpu_data_out;
 assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
 
 
-
-
 logic [7:0] rom_data_out;
 logic [7:0] ram_data_out;
 
 logic ram_cs;
 logic rom_cs;
+logic hex_cs;
 
+cpu_clk cpu_clk(
+	.inclk0(clk_50),
+	.c0(clk)
+);
 
 addr_decode decode(
     .addr(cpu_addr),
     .ram_cs(ram_cs),
-    .rom_cs(rom_cs)
+    .rom_cs(rom_cs),
+    .hex_cs(hex_cs)
 );
 
  
@@ -82,6 +92,16 @@ rom boot_rom(
     .clock(clk),
     .q(rom_data_out)
 );
+
+SevenSeg segs(
+    .clk(clk),
+    .rst(rst),
+    .rw(cpu_rwb),
+    .data(cpu_data_in),
+    .cs(hex_cs),
+    .addr(cpu_addr[0]),
+    .HEX0(HEX0), .HEX1(HEX1), .HEX2(HEX2), .HEX3(HEX3),
+);
  
  
 endmodule