Add hex drivers

hw/fpga/HexDriver.sv

@@ -0,0 +1,27 @@
+module HexDriver (input  [3:0]  In0,
+                  output logic [6:0]  Out0);
+	
+	always_comb
+	begin
+		unique case (In0)
+	 	   4'b0000   : Out0 = 7'b1000000; // '0'
+	 	   4'b0001   : Out0 = 7'b1111001; // '1'
+		   4'b0010   : Out0 = 7'b0100100; // '2'
+	 	   4'b0011   : Out0 = 7'b0110000; // '3'
+	 	   4'b0100   : Out0 = 7'b0011001; // '4'
+		   4'b0101   : Out0 = 7'b0010010; // '5'
+	 	   4'b0110   : Out0 = 7'b0000010; // '6'
+	 	   4'b0111   : Out0 = 7'b1111000; // '7'
+	 	   4'b1000   : Out0 = 7'b0000000; // '8'
+		   4'b1001   : Out0 = 7'b0010000; // '9'
+	 	   4'b1010   : Out0 = 7'b0001000; // 'A'
+	 	   4'b1011   : Out0 = 7'b0000011; // 'b'
+	 	   4'b1100   : Out0 = 7'b1000110; // 'C'
+		   4'b1101   : Out0 = 7'b0100001; // 'd'
+	 	   4'b1110   : Out0 = 7'b0000110; // 'E'
+	 	   4'b1111   : Out0 = 7'b0001110; // 'F'
+	 	   default   : Out0 = 7'bX;
+	  	 endcase
+	end
+
+endmodule

hw/fpga/SevenSeg.sv

@@ -0,0 +1,32 @@
+module SevenSeg(
+    input clk,
+    input rst,
+    
+    input rw,
+
+    input [7:0] data,
+    input cs,
+    input addr,
+    
+    output logic [6:0] HEX0, HEX1, HEX2, HEX3
+);
+
+logic [7:0] _data [2];
+
+always_ff @(posedge clk) begin
+    if (rst)
+        _data = '{default:'0};
+    if (~rw)
+        _data[addr] <= data;
+end
+
+
+logic [3:0] hex_4[3:0];
+
+assign {hex_4[3], hex_4[2]} = _data[1];
+assign {hex_4[1], hex_4[0]} = _data[0];
+
+HexDriver hex_drivers[3:0] (hex_4, {HEX3, HEX2, HEX1, HEX0});
+
+
+endmodule

hw/fpga/addr_decode.sv

@@ -2,11 +2,11 @@ module addr_decode(
     input logic [15:0] addr,
     output logic ram_cs,
     output logic rom_cs,
-    output logic io_cs
+    output logic hex_cs
 );
 
 assign rom_cs = addr[15];
 assign ram_cs = ~addr[15] && addr < 16'h7ff0;
-assign io_cs = addr >= 16'h7ff0 && addr < 16'h8000;
+assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff2;
 
 endmodule

hw/fpga/cpu_clk.ppf

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="MAX 10" variation_name="cpu_clk" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>

hw/fpga/cpu_clk.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "18.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cpu_clk.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cpu_clk.ppf"]

hw/fpga/cpu_clk.v

@@ -0,0 +1,305 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: cpu_clk.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2018  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module cpu_clk (
+	inclk0,
+	c0);
+
+	input	  inclk0;
+	output	  c0;
+
+	wire [4:0] sub_wire0;
+	wire [0:0] sub_wire4 = 1'h0;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  sub_wire2 = inclk0;
+	wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+	altpll	altpll_component (
+				.inclk (sub_wire3),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 50,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 1,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "MAX 10",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=cpu_clk",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "cpu_clk.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON

hw/fpga/greybox_tmp/cbx_args.txt

@@ -1,16 +1,58 @@
-CLOCK_ENABLE_INPUT_A=BYPASS
+BANDWIDTH_TYPE=AUTO
-CLOCK_ENABLE_OUTPUT_A=BYPASS
+CLK0_DIVIDE_BY=50
+CLK0_DUTY_CYCLE=50
+CLK0_MULTIPLY_BY=1
+CLK0_PHASE_SHIFT=0
+COMPENSATE_CLOCK=CLK0
+INCLK0_INPUT_FREQUENCY=20000
 INTENDED_DEVICE_FAMILY="MAX 10"
-NUMWORDS_A=32768
+LPM_TYPE=altpll
-OPERATION_MODE=SINGLE_PORT
+OPERATION_MODE=NORMAL
-OUTDATA_ACLR_A=NONE
+PLL_TYPE=AUTO
-OUTDATA_REG_A=UNREGISTERED
+PORT_ACTIVECLOCK=PORT_UNUSED
-POWER_UP_UNINITIALIZED=FALSE
+PORT_ARESET=PORT_UNUSED
-READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
+PORT_CLKBAD0=PORT_UNUSED
-WIDTHAD_A=15
+PORT_CLKBAD1=PORT_UNUSED
-WIDTH_A=8
+PORT_CLKLOSS=PORT_UNUSED
-WIDTH_BYTEENA_A=1
+PORT_CLKSWITCH=PORT_UNUSED
+PORT_CONFIGUPDATE=PORT_UNUSED
+PORT_FBIN=PORT_UNUSED
+PORT_INCLK0=PORT_USED
+PORT_INCLK1=PORT_UNUSED
+PORT_LOCKED=PORT_UNUSED
+PORT_PFDENA=PORT_UNUSED
+PORT_PHASECOUNTERSELECT=PORT_UNUSED
+PORT_PHASEDONE=PORT_UNUSED
+PORT_PHASESTEP=PORT_UNUSED
+PORT_PHASEUPDOWN=PORT_UNUSED
+PORT_PLLENA=PORT_UNUSED
+PORT_SCANACLR=PORT_UNUSED
+PORT_SCANCLK=PORT_UNUSED
+PORT_SCANCLKENA=PORT_UNUSED
+PORT_SCANDATA=PORT_UNUSED
+PORT_SCANDATAOUT=PORT_UNUSED
+PORT_SCANDONE=PORT_UNUSED
+PORT_SCANREAD=PORT_UNUSED
+PORT_SCANWRITE=PORT_UNUSED
+PORT_clk0=PORT_USED
+PORT_clk1=PORT_UNUSED
+PORT_clk2=PORT_UNUSED
+PORT_clk3=PORT_UNUSED
+PORT_clk4=PORT_UNUSED
+PORT_clk5=PORT_UNUSED
+PORT_clkena0=PORT_UNUSED
+PORT_clkena1=PORT_UNUSED
+PORT_clkena2=PORT_UNUSED
+PORT_clkena3=PORT_UNUSED
+PORT_clkena4=PORT_UNUSED
+PORT_clkena5=PORT_UNUSED
+PORT_extclk0=PORT_UNUSED
+PORT_extclk1=PORT_UNUSED
+PORT_extclk2=PORT_UNUSED
+PORT_extclk3=PORT_UNUSED
+WIDTH_CLOCK=5
 DEVICE_FAMILY="MAX 10"
-address_a
+CBX_AUTO_BLACKBOX=ALL
-clock0
+inclk
-q_a
+inclk
+clk

hw/fpga/super6502.qsf

@@ -90,11 +90,15 @@ set_location_assignment PIN_W7 -to cpu_mlb
 set_location_assignment PIN_W8 -to cpu_irqb
 set_location_assignment PIN_P11 -to clk
 set_location_assignment PIN_B8 -to rst
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name SYSTEMVERILOG_FILE addr_decode.sv
 set_global_assignment -name SYSTEMVERILOG_FILE bb_spi_controller.sv
 set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv
 set_global_assignment -name QIP_FILE ram.qip
 set_global_assignment -name SDC_FILE super6502.sdc
 set_global_assignment -name QIP_FILE rom.qip
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name SYSTEMVERILOG_FILE HexDriver.sv
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name SYSTEMVERILOG_FILE SevenSeg.sv
+set_global_assignment -name QIP_FILE cpu_clk.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

hw/fpga/super6502.sv

@@ -1,7 +1,7 @@
 
 module super6502(
-    input                   clk,
+    input                   clk_50,
-    input   logic           rst,
+    input   logic           rst_n,
     
     input   logic [15:0]    cpu_addr,
     inout   logic [7:0]     cpu_data,
@@ -18,9 +18,15 @@ module super6502(
     output  logic           cpu_irqb,
     output  logic           cpu_phi2,
     output  logic           cpu_be,
-    output  logic           cpu_nmib
+    output  logic           cpu_nmib,
+    
+    output logic [6:0] HEX0, HEX1, HEX2, HEX3
   );
   
+logic rst;
+assign rst = ~rst_n;
+
+logic clk;
 
 logic [7:0] cpu_data_in;
 assign cpu_data_in = cpu_data;
@@ -29,19 +35,23 @@ logic [7:0] cpu_data_out;
 assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
 
 
-
-
 logic [7:0] rom_data_out;
 logic [7:0] ram_data_out;
 
 logic ram_cs;
 logic rom_cs;
+logic hex_cs;
 
+cpu_clk cpu_clk(
+	.inclk0(clk_50),
+	.c0(clk)
+);
 
 addr_decode decode(
     .addr(cpu_addr),
     .ram_cs(ram_cs),
-    .rom_cs(rom_cs)
+    .rom_cs(rom_cs),
+    .hex_cs(hex_cs)
 );
 
  
@@ -82,6 +92,16 @@ rom boot_rom(
     .clock(clk),
     .q(rom_data_out)
 );
+
+SevenSeg segs(
+    .clk(clk),
+    .rst(rst),
+    .rw(cpu_rwb),
+    .data(cpu_data_in),
+    .cs(hex_cs),
+    .addr(cpu_addr[0]),
+    .HEX0(HEX0), .HEX1(HEX1), .HEX2(HEX2), .HEX3(HEX3),
+);
  
  
 endmodule