Add hex drivers
This commit is contained in:
Byron Lathi
27
hw/fpga/HexDriver.sv
Normal file
27
hw/fpga/HexDriver.sv
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@@ -0,0 +1,27 @@
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module HexDriver (input [3:0] In0,
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output logic [6:0] Out0);
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always_comb
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begin
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unique case (In0)
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4'b0000 : Out0 = 7'b1000000; // '0'
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4'b0001 : Out0 = 7'b1111001; // '1'
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4'b0010 : Out0 = 7'b0100100; // '2'
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4'b0011 : Out0 = 7'b0110000; // '3'
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4'b0100 : Out0 = 7'b0011001; // '4'
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4'b0101 : Out0 = 7'b0010010; // '5'
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4'b0110 : Out0 = 7'b0000010; // '6'
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4'b0111 : Out0 = 7'b1111000; // '7'
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4'b1000 : Out0 = 7'b0000000; // '8'
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4'b1001 : Out0 = 7'b0010000; // '9'
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4'b1010 : Out0 = 7'b0001000; // 'A'
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4'b1011 : Out0 = 7'b0000011; // 'b'
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4'b1100 : Out0 = 7'b1000110; // 'C'
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4'b1101 : Out0 = 7'b0100001; // 'd'
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4'b1110 : Out0 = 7'b0000110; // 'E'
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4'b1111 : Out0 = 7'b0001110; // 'F'
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default : Out0 = 7'bX;
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endcase
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end
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endmodule
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32
hw/fpga/SevenSeg.sv
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32
hw/fpga/SevenSeg.sv
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@@ -0,0 +1,32 @@
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module SevenSeg(
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input clk,
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input rst,
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input rw,
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input [7:0] data,
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input cs,
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input addr,
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output logic [6:0] HEX0, HEX1, HEX2, HEX3
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);
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logic [7:0] _data [2];
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always_ff @(posedge clk) begin
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if (rst)
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_data = '{default:'0};
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if (~rw)
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_data[addr] <= data;
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end
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logic [3:0] hex_4[3:0];
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assign {hex_4[3], hex_4[2]} = _data[1];
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assign {hex_4[1], hex_4[0]} = _data[0];
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HexDriver hex_drivers[3:0] (hex_4, {HEX3, HEX2, HEX1, HEX0});
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endmodule
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@@ -2,11 +2,11 @@ module addr_decode(
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input logic [15:0] addr,
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output logic ram_cs,
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output logic rom_cs,
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output logic io_cs
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output logic hex_cs
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);
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assign rom_cs = addr[15];
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assign ram_cs = ~addr[15] && addr < 16'h7ff0;
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assign io_cs = addr >= 16'h7ff0 && addr < 16'h8000;
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assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff2;
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endmodule
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9
hw/fpga/cpu_clk.ppf
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9
hw/fpga/cpu_clk.ppf
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@@ -0,0 +1,9 @@
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<?xml version="1.0" encoding="UTF-8" ?>
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<!DOCTYPE pinplan>
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<pinplan intended_family="MAX 10" variation_name="cpu_clk" megafunction_name="ALTPLL" specifies="all_ports">
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<global>
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<pin name="inclk0" direction="input" scope="external" source="clock" />
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<pin name="c0" direction="output" scope="external" source="clock" />
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</global>
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</pinplan>
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5
hw/fpga/cpu_clk.qip
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5
hw/fpga/cpu_clk.qip
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@@ -0,0 +1,5 @@
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
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set_global_assignment -name IP_TOOL_VERSION "18.1"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cpu_clk.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cpu_clk.ppf"]
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305
hw/fpga/cpu_clk.v
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305
hw/fpga/cpu_clk.v
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@@ -0,0 +1,305 @@
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// megafunction wizard: %ALTPLL%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altpll
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// ============================================================
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// File Name: cpu_clk.v
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// Megafunction Name(s):
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// altpll
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2018 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module cpu_clk (
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inclk0,
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c0);
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input inclk0;
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output c0;
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wire [4:0] sub_wire0;
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wire [0:0] sub_wire4 = 1'h0;
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wire [0:0] sub_wire1 = sub_wire0[0:0];
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wire c0 = sub_wire1;
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wire sub_wire2 = inclk0;
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wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
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altpll altpll_component (
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.inclk (sub_wire3),
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.clk (sub_wire0),
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.activeclock (),
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.areset (1'b0),
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.clkbad (),
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.clkena ({6{1'b1}}),
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.clkloss (),
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.clkswitch (1'b0),
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.configupdate (1'b0),
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.enable0 (),
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.enable1 (),
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.extclk (),
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.extclkena ({4{1'b1}}),
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.fbin (1'b1),
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.fbmimicbidir (),
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.fbout (),
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.fref (),
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.icdrclk (),
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.locked (),
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.pfdena (1'b1),
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.phasecounterselect ({4{1'b1}}),
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.phasedone (),
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.phasestep (1'b1),
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.phaseupdown (1'b1),
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.pllena (1'b1),
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.scanaclr (1'b0),
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.scanclk (1'b0),
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.scanclkena (1'b1),
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.scandata (1'b0),
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.scandataout (),
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.scandone (),
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.scanread (1'b0),
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.scanwrite (1'b0),
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.sclkout0 (),
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.sclkout1 (),
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.vcooverrange (),
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.vcounderrange ());
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defparam
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altpll_component.bandwidth_type = "AUTO",
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altpll_component.clk0_divide_by = 50,
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altpll_component.clk0_duty_cycle = 50,
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altpll_component.clk0_multiply_by = 1,
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altpll_component.clk0_phase_shift = "0",
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altpll_component.compensate_clock = "CLK0",
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altpll_component.inclk0_input_frequency = 20000,
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altpll_component.intended_device_family = "MAX 10",
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altpll_component.lpm_hint = "CBX_MODULE_PREFIX=cpu_clk",
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altpll_component.lpm_type = "altpll",
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altpll_component.operation_mode = "NORMAL",
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altpll_component.pll_type = "AUTO",
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altpll_component.port_activeclock = "PORT_UNUSED",
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altpll_component.port_areset = "PORT_UNUSED",
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altpll_component.port_clkbad0 = "PORT_UNUSED",
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altpll_component.port_clkbad1 = "PORT_UNUSED",
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altpll_component.port_clkloss = "PORT_UNUSED",
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altpll_component.port_clkswitch = "PORT_UNUSED",
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altpll_component.port_configupdate = "PORT_UNUSED",
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altpll_component.port_fbin = "PORT_UNUSED",
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altpll_component.port_inclk0 = "PORT_USED",
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altpll_component.port_inclk1 = "PORT_UNUSED",
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altpll_component.port_locked = "PORT_UNUSED",
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altpll_component.port_pfdena = "PORT_UNUSED",
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altpll_component.port_phasecounterselect = "PORT_UNUSED",
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altpll_component.port_phasedone = "PORT_UNUSED",
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altpll_component.port_phasestep = "PORT_UNUSED",
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altpll_component.port_phaseupdown = "PORT_UNUSED",
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altpll_component.port_pllena = "PORT_UNUSED",
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altpll_component.port_scanaclr = "PORT_UNUSED",
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altpll_component.port_scanclk = "PORT_UNUSED",
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altpll_component.port_scanclkena = "PORT_UNUSED",
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altpll_component.port_scandata = "PORT_UNUSED",
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altpll_component.port_scandataout = "PORT_UNUSED",
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altpll_component.port_scandone = "PORT_UNUSED",
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altpll_component.port_scanread = "PORT_UNUSED",
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altpll_component.port_scanwrite = "PORT_UNUSED",
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altpll_component.port_clk0 = "PORT_USED",
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altpll_component.port_clk1 = "PORT_UNUSED",
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altpll_component.port_clk2 = "PORT_UNUSED",
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altpll_component.port_clk3 = "PORT_UNUSED",
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altpll_component.port_clk4 = "PORT_UNUSED",
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altpll_component.port_clk5 = "PORT_UNUSED",
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altpll_component.port_clkena0 = "PORT_UNUSED",
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altpll_component.port_clkena1 = "PORT_UNUSED",
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altpll_component.port_clkena2 = "PORT_UNUSED",
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altpll_component.port_clkena3 = "PORT_UNUSED",
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altpll_component.port_clkena4 = "PORT_UNUSED",
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altpll_component.port_clkena5 = "PORT_UNUSED",
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altpll_component.port_extclk0 = "PORT_UNUSED",
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altpll_component.port_extclk1 = "PORT_UNUSED",
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altpll_component.port_extclk2 = "PORT_UNUSED",
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altpll_component.port_extclk3 = "PORT_UNUSED",
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altpll_component.width_clock = 5;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
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// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
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// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
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// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
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// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
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// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
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// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
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// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
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// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
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// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
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// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
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// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
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// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
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// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
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// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
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// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
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// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
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// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000"
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// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
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// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
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// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
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// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
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// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
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// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
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// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
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// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
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// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
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// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
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// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
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// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
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// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
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// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
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// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
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// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
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// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
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// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
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// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
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// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
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// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
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// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
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// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.00000000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
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// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
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// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
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// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
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// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
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// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
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// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
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// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
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// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
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// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
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// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
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// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
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// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
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// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
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// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
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// Retrieval info: PRIVATE: RECONFIG_FILE STRING "cpu_clk.mif"
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// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
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// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
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// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
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// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
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// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
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// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
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// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
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// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
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// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
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// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
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// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
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// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0"
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// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
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// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
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// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
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// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
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// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
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// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
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// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
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// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
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// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50"
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// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
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// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
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// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
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// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
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// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
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// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
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// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
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// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
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||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
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// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
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||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
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||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
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||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
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||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL cpu_clk_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
@@ -1,16 +1,58 @@
|
||||
CLOCK_ENABLE_INPUT_A=BYPASS
|
||||
CLOCK_ENABLE_OUTPUT_A=BYPASS
|
||||
BANDWIDTH_TYPE=AUTO
|
||||
CLK0_DIVIDE_BY=50
|
||||
CLK0_DUTY_CYCLE=50
|
||||
CLK0_MULTIPLY_BY=1
|
||||
CLK0_PHASE_SHIFT=0
|
||||
COMPENSATE_CLOCK=CLK0
|
||||
INCLK0_INPUT_FREQUENCY=20000
|
||||
INTENDED_DEVICE_FAMILY="MAX 10"
|
||||
NUMWORDS_A=32768
|
||||
OPERATION_MODE=SINGLE_PORT
|
||||
OUTDATA_ACLR_A=NONE
|
||||
OUTDATA_REG_A=UNREGISTERED
|
||||
POWER_UP_UNINITIALIZED=FALSE
|
||||
READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
|
||||
WIDTHAD_A=15
|
||||
WIDTH_A=8
|
||||
WIDTH_BYTEENA_A=1
|
||||
LPM_TYPE=altpll
|
||||
OPERATION_MODE=NORMAL
|
||||
PLL_TYPE=AUTO
|
||||
PORT_ACTIVECLOCK=PORT_UNUSED
|
||||
PORT_ARESET=PORT_UNUSED
|
||||
PORT_CLKBAD0=PORT_UNUSED
|
||||
PORT_CLKBAD1=PORT_UNUSED
|
||||
PORT_CLKLOSS=PORT_UNUSED
|
||||
PORT_CLKSWITCH=PORT_UNUSED
|
||||
PORT_CONFIGUPDATE=PORT_UNUSED
|
||||
PORT_FBIN=PORT_UNUSED
|
||||
PORT_INCLK0=PORT_USED
|
||||
PORT_INCLK1=PORT_UNUSED
|
||||
PORT_LOCKED=PORT_UNUSED
|
||||
PORT_PFDENA=PORT_UNUSED
|
||||
PORT_PHASECOUNTERSELECT=PORT_UNUSED
|
||||
PORT_PHASEDONE=PORT_UNUSED
|
||||
PORT_PHASESTEP=PORT_UNUSED
|
||||
PORT_PHASEUPDOWN=PORT_UNUSED
|
||||
PORT_PLLENA=PORT_UNUSED
|
||||
PORT_SCANACLR=PORT_UNUSED
|
||||
PORT_SCANCLK=PORT_UNUSED
|
||||
PORT_SCANCLKENA=PORT_UNUSED
|
||||
PORT_SCANDATA=PORT_UNUSED
|
||||
PORT_SCANDATAOUT=PORT_UNUSED
|
||||
PORT_SCANDONE=PORT_UNUSED
|
||||
PORT_SCANREAD=PORT_UNUSED
|
||||
PORT_SCANWRITE=PORT_UNUSED
|
||||
PORT_clk0=PORT_USED
|
||||
PORT_clk1=PORT_UNUSED
|
||||
PORT_clk2=PORT_UNUSED
|
||||
PORT_clk3=PORT_UNUSED
|
||||
PORT_clk4=PORT_UNUSED
|
||||
PORT_clk5=PORT_UNUSED
|
||||
PORT_clkena0=PORT_UNUSED
|
||||
PORT_clkena1=PORT_UNUSED
|
||||
PORT_clkena2=PORT_UNUSED
|
||||
PORT_clkena3=PORT_UNUSED
|
||||
PORT_clkena4=PORT_UNUSED
|
||||
PORT_clkena5=PORT_UNUSED
|
||||
PORT_extclk0=PORT_UNUSED
|
||||
PORT_extclk1=PORT_UNUSED
|
||||
PORT_extclk2=PORT_UNUSED
|
||||
PORT_extclk3=PORT_UNUSED
|
||||
WIDTH_CLOCK=5
|
||||
DEVICE_FAMILY="MAX 10"
|
||||
address_a
|
||||
clock0
|
||||
q_a
|
||||
CBX_AUTO_BLACKBOX=ALL
|
||||
inclk
|
||||
inclk
|
||||
clk
|
||||
|
||||
@@ -90,11 +90,15 @@ set_location_assignment PIN_W7 -to cpu_mlb
|
||||
set_location_assignment PIN_W8 -to cpu_irqb
|
||||
set_location_assignment PIN_P11 -to clk
|
||||
set_location_assignment PIN_B8 -to rst
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE addr_decode.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE bb_spi_controller.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv
|
||||
set_global_assignment -name QIP_FILE ram.qip
|
||||
set_global_assignment -name SDC_FILE super6502.sdc
|
||||
set_global_assignment -name QIP_FILE rom.qip
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE HexDriver.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE SevenSeg.sv
|
||||
set_global_assignment -name QIP_FILE cpu_clk.qip
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,7 +1,7 @@
|
||||
|
||||
module super6502(
|
||||
input clk,
|
||||
input logic rst,
|
||||
input clk_50,
|
||||
input logic rst_n,
|
||||
|
||||
input logic [15:0] cpu_addr,
|
||||
inout logic [7:0] cpu_data,
|
||||
@@ -18,9 +18,15 @@ module super6502(
|
||||
output logic cpu_irqb,
|
||||
output logic cpu_phi2,
|
||||
output logic cpu_be,
|
||||
output logic cpu_nmib
|
||||
output logic cpu_nmib,
|
||||
|
||||
output logic [6:0] HEX0, HEX1, HEX2, HEX3
|
||||
);
|
||||
|
||||
logic rst;
|
||||
assign rst = ~rst_n;
|
||||
|
||||
logic clk;
|
||||
|
||||
logic [7:0] cpu_data_in;
|
||||
assign cpu_data_in = cpu_data;
|
||||
@@ -29,19 +35,23 @@ logic [7:0] cpu_data_out;
|
||||
assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
|
||||
|
||||
|
||||
|
||||
|
||||
logic [7:0] rom_data_out;
|
||||
logic [7:0] ram_data_out;
|
||||
|
||||
logic ram_cs;
|
||||
logic rom_cs;
|
||||
logic hex_cs;
|
||||
|
||||
cpu_clk cpu_clk(
|
||||
.inclk0(clk_50),
|
||||
.c0(clk)
|
||||
);
|
||||
|
||||
addr_decode decode(
|
||||
.addr(cpu_addr),
|
||||
.ram_cs(ram_cs),
|
||||
.rom_cs(rom_cs)
|
||||
.rom_cs(rom_cs),
|
||||
.hex_cs(hex_cs)
|
||||
);
|
||||
|
||||
|
||||
@@ -82,6 +92,16 @@ rom boot_rom(
|
||||
.clock(clk),
|
||||
.q(rom_data_out)
|
||||
);
|
||||
|
||||
SevenSeg segs(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.rw(cpu_rwb),
|
||||
.data(cpu_data_in),
|
||||
.cs(hex_cs),
|
||||
.addr(cpu_addr[0]),
|
||||
.HEX0(HEX0), .HEX1(HEX1), .HEX2(HEX2), .HEX3(HEX3),
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user