diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 300a5bd..abf3ef9 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -18,6 +18,7 @@ sim:
   stage: sim
   tags:
     - linux
+    - efinity
   script:
     - source init_env.sh
     - make sim
diff --git a/Makefile b/Makefile
index 4a96722..f13bfba 100644
--- a/Makefile
+++ b/Makefile
@@ -14,6 +14,9 @@ fpga_image: $(INIT_HEX)
 sim: $(INIT_HEX)
 	$(MAKE) -C hw/super6502_fpga/src/sim
 
+waves: sim
+	gtkwave hw/super6502_fpga/src/sim/sim_top.vcd
+
 # SW
 .PHONY: toolchain
 toolchain:
diff --git a/hw/super6502_fpga/addr_map.mem b/hw/super6502_fpga/addr_map.mem
index 3d631b3..7a02cdc 100644
--- a/hw/super6502_fpga/addr_map.mem
+++ b/hw/super6502_fpga/addr_map.mem
@@ -2,4 +2,6 @@
 00000000 
 000001ff
 0000ff00
-0000ffff
\ No newline at end of file
+0000ffff
+00000200
+0000efff
\ No newline at end of file
diff --git a/hw/super6502_fpga/ip/sdram_controller/ipm/component.pickle b/hw/super6502_fpga/ip/sdram_controller/ipm/component.pickle
new file mode 100644
index 0000000..1ef144d
Binary files /dev/null and b/hw/super6502_fpga/ip/sdram_controller/ipm/component.pickle differ
diff --git a/hw/super6502_fpga/ip/sdram_controller/ipm/graph.pickle b/hw/super6502_fpga/ip/sdram_controller/ipm/graph.pickle
new file mode 100644
index 0000000..6bb69b6
Binary files /dev/null and b/hw/super6502_fpga/ip/sdram_controller/ipm/graph.pickle differ
diff --git a/hw/super6502_fpga/ip/sdram_controller/sdram_controller.v b/hw/super6502_fpga/ip/sdram_controller/sdram_controller.v
new file mode 100644
index 0000000..926328a
--- /dev/null
+++ b/hw/super6502_fpga/ip/sdram_controller/sdram_controller.v
@@ -0,0 +1,4347 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.1.150
+// IP Version: 5.0
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`define IP_UUID _5c381f4179ce404bb3abce25f7e88ca9
+`define IP_NAME_CONCAT(a,b) a``b
+`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
+module sdram_controller (
+input i_aresetn,
+input [23:0] i_AXI4_AWADDR,
+input i_sysclk,
+input i_sdrclk,
+input i_tACclk,
+input i_pll_locked,
+output o_dbg_ref_req,
+output o_dbg_wr_ack,
+output o_dbg_rd_ack,
+output [1:0] o_dbg_n_CS,
+output [1:0] o_dbg_n_RAS,
+output [1:0] o_dbg_n_CAS,
+output [1:0] o_dbg_n_WE,
+output [3:0] o_dbg_BA,
+output [25:0] o_dbg_ADDR,
+output [31:0] o_dbg_DATA_out,
+output [31:0] o_dbg_DATA_in,
+output o_pll_reset,
+output o_AXI4_AWREADY,
+input i_AXI4_AWVALID,
+output o_AXI4_WREADY,
+input [31:0] i_AXI4_WDATA,
+input [3:0] i_AXI4_WSTRB,
+input i_AXI4_WLAST,
+input i_AXI4_WVALID,
+output o_AXI4_BVALID,
+input i_AXI4_BREADY,
+output o_AXI4_ARREADY,
+input [23:0] i_AXI4_ARADDR,
+input i_AXI4_RREADY,
+output [31:0] o_AXI4_RDATA,
+output o_AXI4_RLAST,
+output o_AXI4_RVALID,
+input [3:0] i_AXI4_AWID,
+input [2:0] i_AXI4_AWSIZE,
+input i_AXI4_ARVALID,
+input [3:0] i_AXI4_ARID,
+input [7:0] i_AXI4_ARLEN,
+input [2:0] i_AXI4_ARSIZE,
+input [1:0] i_AXI4_ARBURST,
+input [7:0] i_AXI4_AWLEN,
+output [3:0] o_AXI4_RID,
+output o_dbg_we,
+output o_dbg_last,
+output [23:0] o_dbg_addr,
+output [31:0] o_dbg_din,
+output [1:0] o_axi4_wrstate,
+output o_fifo_wr,
+output o_fifo_full,
+output o_fifo_empty,
+output [7:0] o_dbg_fifo_waddr,
+output o_dbg_fifo_re,
+output [7:0] o_dbg_fifo_raddr,
+output o_dbg_fifo_we,
+output o_dbg_axi4_wlast,
+output [6:0] o_shift_cnt,
+output o_re_lock,
+output [1:0] o_axi4_rastate,
+output o_axi4_nwr,
+output [7:0] o_axi4_arlen,
+output [1:0] o_axi4_rdstate,
+output o_sdr_rd_valid,
+output [36:0] o_sdr_dout,
+output o_dbg_re,
+output [3:0] o_AXI4_BID,
+input [23:0] i_addr,
+input [31:0] i_din,
+input [3:0] i_dm,
+output [31:0] o_dout,
+output [3:0] o_sdr_state,
+output o_sdr_init_done,
+output o_wr_ack,
+output o_rd_ack,
+output o_ref_req,
+output o_rd_valid,
+output [1:0] o_sdr_CKE,
+output [1:0] o_sdr_n_CS,
+output [1:0] o_sdr_n_RAS,
+output [1:0] o_sdr_n_CAS,
+output [1:0] o_sdr_n_WE,
+output [3:0] o_sdr_BA,
+output [25:0] o_sdr_ADDR,
+output [31:0] o_sdr_DATA,
+output [31:0] o_sdr_DATA_oe,
+input [31:0] i_sdr_DATA,
+output [3:0] o_sdr_DQM
+);
+`IP_MODULE_NAME(efx_sdram_controller) #(
+.fSYS_MHz (100),
+.fCK_MHz (200),
+.tIORT_u (2),
+.CL (3),
+.BL (1),
+.DDIO_TYPE ("SOFT"),
+.DQ_WIDTH (8),
+.DQ_GROUP (2),
+.BA_WIDTH (2),
+.ROW_WIDTH (13),
+.COL_WIDTH (9),
+.tPWRUP (200000),
+.tRAS (44),
+.tRAS_MAX (120000),
+.tRC (66),
+.tRCD (20),
+.tREF (64000000),
+.tRFC (66),
+.tRP (20),
+.tWR (2),
+.tMRD (2),
+.SDRAM_MODE ("AXI4"),
+.DATA_RATE (2),
+.AXI_AWADDR_WIDTH (24),
+.AXI_WDATA_WIDTH (32),
+.AXI_ARADDR_WIDTH (24),
+.AXI_RDATA_WIDTH (32),
+.AXI_AWID_WIDTH (4),
+.AXI_AWUSER_WIDTH (2),
+.AXI_WUSER_WIDTH (2),
+.AXI_BID_WIDTH (4),
+.AXI_BUSER_WIDTH (2),
+.AXI_ARID_WIDTH (4),
+.AXI_ARUSER_WIDTH (3),
+.AXI_RUSER_WIDTH (3)
+) u_efx_sdram_controller(
+.i_aresetn ( i_aresetn ),
+.i_AXI4_AWADDR ( i_AXI4_AWADDR ),
+.i_sysclk ( i_sysclk ),
+.i_sdrclk ( i_sdrclk ),
+.i_tACclk ( i_tACclk ),
+.i_pll_locked ( i_pll_locked ),
+.o_dbg_ref_req ( o_dbg_ref_req ),
+.o_dbg_wr_ack ( o_dbg_wr_ack ),
+.o_dbg_rd_ack ( o_dbg_rd_ack ),
+.o_dbg_n_CS ( o_dbg_n_CS ),
+.o_dbg_n_RAS ( o_dbg_n_RAS ),
+.o_dbg_n_CAS ( o_dbg_n_CAS ),
+.o_dbg_n_WE ( o_dbg_n_WE ),
+.o_dbg_BA ( o_dbg_BA ),
+.o_dbg_ADDR ( o_dbg_ADDR ),
+.o_dbg_DATA_out ( o_dbg_DATA_out ),
+.o_dbg_DATA_in ( o_dbg_DATA_in ),
+.o_pll_reset ( o_pll_reset ),
+.o_AXI4_AWREADY ( o_AXI4_AWREADY ),
+.i_AXI4_AWVALID ( i_AXI4_AWVALID ),
+.o_AXI4_WREADY ( o_AXI4_WREADY ),
+.i_AXI4_WDATA ( i_AXI4_WDATA ),
+.i_AXI4_WSTRB ( i_AXI4_WSTRB ),
+.i_AXI4_WLAST ( i_AXI4_WLAST ),
+.i_AXI4_WVALID ( i_AXI4_WVALID ),
+.o_AXI4_BVALID ( o_AXI4_BVALID ),
+.i_AXI4_BREADY ( i_AXI4_BREADY ),
+.o_AXI4_ARREADY ( o_AXI4_ARREADY ),
+.i_AXI4_ARADDR ( i_AXI4_ARADDR ),
+.i_AXI4_RREADY ( i_AXI4_RREADY ),
+.o_AXI4_RDATA ( o_AXI4_RDATA ),
+.o_AXI4_RLAST ( o_AXI4_RLAST ),
+.o_AXI4_RVALID ( o_AXI4_RVALID ),
+.i_AXI4_AWID ( i_AXI4_AWID ),
+.i_AXI4_AWSIZE ( i_AXI4_AWSIZE ),
+.i_AXI4_ARVALID ( i_AXI4_ARVALID ),
+.i_AXI4_ARID ( i_AXI4_ARID ),
+.i_AXI4_ARLEN ( i_AXI4_ARLEN ),
+.i_AXI4_ARSIZE ( i_AXI4_ARSIZE ),
+.i_AXI4_ARBURST ( i_AXI4_ARBURST ),
+.i_AXI4_AWLEN ( i_AXI4_AWLEN ),
+.o_AXI4_RID ( o_AXI4_RID ),
+.o_dbg_we ( o_dbg_we ),
+.o_dbg_last ( o_dbg_last ),
+.o_dbg_addr ( o_dbg_addr ),
+.o_dbg_din ( o_dbg_din ),
+.o_axi4_wrstate ( o_axi4_wrstate ),
+.o_fifo_wr ( o_fifo_wr ),
+.o_fifo_full ( o_fifo_full ),
+.o_fifo_empty ( o_fifo_empty ),
+.o_dbg_fifo_waddr ( o_dbg_fifo_waddr ),
+.o_dbg_fifo_re ( o_dbg_fifo_re ),
+.o_dbg_fifo_raddr ( o_dbg_fifo_raddr ),
+.o_dbg_fifo_we ( o_dbg_fifo_we ),
+.o_dbg_axi4_wlast ( o_dbg_axi4_wlast ),
+.o_shift_cnt ( o_shift_cnt ),
+.o_re_lock ( o_re_lock ),
+.o_axi4_rastate ( o_axi4_rastate ),
+.o_axi4_nwr ( o_axi4_nwr ),
+.o_axi4_arlen ( o_axi4_arlen ),
+.o_axi4_rdstate ( o_axi4_rdstate ),
+.o_sdr_rd_valid ( o_sdr_rd_valid ),
+.o_sdr_dout ( o_sdr_dout ),
+.o_dbg_re ( o_dbg_re ),
+.o_AXI4_BID ( o_AXI4_BID ),
+.i_addr ( i_addr ),
+.i_din ( i_din ),
+.i_dm ( i_dm ),
+.o_dout ( o_dout ),
+.o_sdr_state ( o_sdr_state ),
+.o_sdr_init_done ( o_sdr_init_done ),
+.o_wr_ack ( o_wr_ack ),
+.o_rd_ack ( o_rd_ack ),
+.o_ref_req ( o_ref_req ),
+.o_rd_valid ( o_rd_valid ),
+.o_sdr_CKE ( o_sdr_CKE ),
+.o_sdr_n_CS ( o_sdr_n_CS ),
+.o_sdr_n_RAS ( o_sdr_n_RAS ),
+.o_sdr_n_CAS ( o_sdr_n_CAS ),
+.o_sdr_n_WE ( o_sdr_n_WE ),
+.o_sdr_BA ( o_sdr_BA ),
+.o_sdr_ADDR ( o_sdr_ADDR ),
+.o_sdr_DATA ( o_sdr_DATA ),
+.o_sdr_DATA_oe ( o_sdr_DATA_oe ),
+.i_sdr_DATA ( i_sdr_DATA ),
+.o_sdr_DQM ( o_sdr_DQM )
+);
+
+endmodule
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   `IP_MODULE_NAME(axi4_sdram_controller).v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      sdram contronller top with AXI4 interface
+//  /_/ /\ \_____/ /     
+// ____/  \_______/     
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//  Support ONLY AXI 32-bit data to SDRAM total DQ x16 half rate
+//
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+// AxSIZE
+`define	BYTES_TX_1		3'b000
+`define	BYTES_TX_2		3'b001
+`define	BYTES_TX_4		3'b010
+`define	BYTES_TX_8		3'b011
+`define	BYTES_TX_16		3'b100
+`define	BYTES_TX_32		3'b101
+`define	BYTES_TX_64		3'b110
+`define	BYTES_TX_128	3'b111
+`define	OKAY	2'b00
+
+module `IP_MODULE_NAME(axi4_sdram_controller)
+#(
+	parameter	AXI_AWADDR_WIDTH	= 32,
+	parameter	AXI_WDATA_WIDTH		= 32,
+	parameter	AXI_ARADDR_WIDTH	= 32,
+	parameter	AXI_RDATA_WIDTH		= 32,
+                                    
+	parameter	fSYS_MHz		= 100,
+	parameter	fCK_MHz			= 100,
+	parameter	DDIO_TYPE		= "SOFT",
+	parameter	tPWRUP			= 100,			// 100 us
+	parameter	tRAS			= 44,			// 44 ns
+	parameter	tRAS_MAX		= 120,		// 120 us
+	parameter	tRC			    = 66,			// 66 ns
+	parameter	tRCD			= 20,			// 20 ns
+	parameter	tREF			= 64,			// 64 ms
+	parameter	tRFC			= 66,			// 66 ns
+	parameter	tRP			    = 20,			// 20 ns
+	parameter	tWR			    = 2,			// 1 CK+7.5 ns
+	parameter	tMRD			= 2,			// 2 CK
+	parameter	CL			    = 3,			// 3 CK
+	parameter	BL			    = 1,
+    parameter   DATA_RATE       = 1,
+    parameter   tIORT_u		    = 2,
+	parameter	BA_WIDTH		= 2,
+	parameter	ROW_WIDTH		= 10,
+	parameter	COL_WIDTH		= 10,
+	parameter	DQ_WIDTH		= 8,	// x4, x8
+	parameter	DQ_GROUP		= 8,
+	//			x4	x8	x16	x32
+	// DQ_WIDTH	4	8	8	8
+	// DQ_GROUP	1	1	2	4
+	// AXI not support DQ_WIDTH = 4 DQ_GROUP = 1
+	
+	//----- parameter not configurable by user----
+	parameter	AXI_AWID_WIDTH		= 4,
+	parameter	AXI_AWUSER_WIDTH	= 2,
+	parameter	AXI_WUSER_WIDTH		= 2,
+	parameter	AXI_BID_WIDTH		= 4,
+	parameter	AXI_BUSER_WIDTH		= 2,
+	parameter	AXI_ARID_WIDTH		= 4,
+	parameter	AXI_ARUSER_WIDTH	= 2,
+	parameter	AXI_RUSER_WIDTH		= 2
+)
+(
+	input	i_aresetn,
+	input	i_sysclk,
+	input	i_sdrclk,
+	input	i_tACclk,
+	input	i_pll_locked,
+	output	o_pll_reset,
+	
+	// Compulsory
+	output	o_AXI4_AWREADY,
+	input	[AXI_AWADDR_WIDTH-1:0]i_AXI4_AWADDR,
+	input	[2:0]i_AXI4_AWPROT,	// Dummy
+	input	i_AXI4_AWVALID,
+	
+	output	o_AXI4_WREADY,
+	input	[AXI_WDATA_WIDTH/8-1:0]i_AXI4_WSTRB,
+	input	[AXI_WDATA_WIDTH-1:0]i_AXI4_WDATA,
+	input	i_AXI4_WLAST,
+	input	i_AXI4_WVALID,
+	
+	output	o_AXI4_BVALID,
+	input	i_AXI4_BREADY,
+	
+	output	o_AXI4_ARREADY,
+	input	[AXI_ARADDR_WIDTH-1:0]i_AXI4_ARADDR,
+	input	[2:0]i_AXI4_ARPROT,		// Dummy
+	input	i_AXI4_ARVALID,
+	
+	input	i_AXI4_RREADY,
+	output	[AXI_RDATA_WIDTH-1:0]o_AXI4_RDATA,
+	output	o_AXI4_RLAST,
+	output	o_AXI4_RVALID,
+	
+	// Optional
+	input	[AXI_AWID_WIDTH-1:0]i_AXI4_AWID,
+	input	[3:0]i_AXI4_AWREGION,					// Dummy
+	input	[7:0]i_AXI4_AWLEN,						// Dummy
+	input	[2:0]i_AXI4_AWSIZE,
+	input	[1:0]i_AXI4_AWBURST,					// Dummy
+	input	i_AXI4_AWLOCK,							// Dummy
+	input	[3:0]i_AXI4_AWCACHE,					// Dummy
+	input	[3:0]i_AXI4_AWQOS,						// Dummy
+	input	[AXI_AWUSER_WIDTH-1:0]i_AXI4_AWUSER,	// Dummy
+	
+	input	[AXI_WUSER_WIDTH-1:0]i_AXI4_WUSER,		// Dummy
+	
+	output	[AXI_BID_WIDTH-1:0]o_AXI4_BID,
+	output	[1:0]o_AXI4_BRESP,						// Dummy
+	output	[AXI_BUSER_WIDTH-1:0]o_AXI4_BUSER,		// Dummy
+	
+	input	[AXI_ARID_WIDTH-1:0]i_AXI4_ARID,
+	input	[3:0]i_AXI4_ARREGION,					// Dummy
+	input	[7:0]i_AXI4_ARLEN,
+	input	[2:0]i_AXI4_ARSIZE,
+	input	[1:0]i_AXI4_ARBURST,					// Dummy
+	input	i_AXI4_ARLOCK,							// Dummy
+	input	[3:0]i_AXI4_ARCACHE,					// Dummy
+	input	[3:0]i_AXI4_ARQOS,						// Dummy
+	input	[AXI_ARUSER_WIDTH-1:0]i_AXI4_ARUSER,	// Dummy
+	
+	output	[AXI_ARID_WIDTH-1:0]o_AXI4_RID,
+	output	[1:0]o_AXI4_RRESP,						// Dummy
+	output	[AXI_RUSER_WIDTH-1:0]o_AXI4_RUSER,		// Dummy
+	
+	output	[DATA_RATE							-1:0]	o_sdr_CKE,
+	output	[DATA_RATE							-1:0]	o_sdr_n_CS,
+	output	[DATA_RATE							-1:0]	o_sdr_n_RAS,
+	output	[DATA_RATE							-1:0]	o_sdr_n_CAS,
+	output	[DATA_RATE							-1:0]	o_sdr_n_WE,
+	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_sdr_BA,
+	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_sdr_ADDR,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_oe,
+	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA,
+	output	[DATA_RATE	*DQ_GROUP				-1:0]	o_sdr_DQM,
+	
+	// Debug port
+	output	[3:0]o_sdr_state,
+	output	o_dbg_we,
+	output	o_dbg_re,
+	output	o_dbg_last,
+	output	[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0]o_dbg_addr,
+	output	[AXI_WDATA_WIDTH-1:0]o_dbg_din,
+	output	o_dbg_wr_ack,
+	output	o_dbg_rd_ack,
+	output	o_sdr_rd_valid,
+	output	o_dbg_ref_req,
+	output	[DATA_RATE*DQ_GROUP*DQ_WIDTH+AXI_ARID_WIDTH:0]o_sdr_dout,
+	output	[1:0]o_axi4_wrstate,
+	output	o_dbg_axi4_wlast,
+	output	[1:0]o_axi4_rastate,
+	output	[1:0]o_axi4_rdstate,
+	output	o_axi4_nwr,
+	output	o_re_lock,
+	output	[6:0]o_shift_cnt,
+	output	[7:0]o_axi4_arlen,
+	output	o_fifo_wr,
+	output	o_fifo_full,
+	output	o_fifo_empty,
+	output	o_dbg_fifo_we,
+	output	[7:0]o_dbg_fifo_waddr,
+	output	o_dbg_fifo_re,
+	output	[7:0]o_dbg_fifo_raddr,
+	
+	output	[DATA_RATE							-1:0]	o_dbg_n_CS,
+	output	[DATA_RATE							-1:0]	o_dbg_n_RAS,
+	output	[DATA_RATE							-1:0]	o_dbg_n_CAS,
+	output	[DATA_RATE							-1:0]	o_dbg_n_WE,
+	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_dbg_BA,
+	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_dbg_ADDR,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_dbg_DATA_out,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_dbg_DATA_in
+);
+
+function integer log2;
+	input	integer	val;
+	integer	i;
+	begin
+		log2 = 0;
+		for (i=0; 2**i<val; i=i+1)
+			log2 = i+1;
+	end
+endfunction
+
+initial
+begin
+	$display("DQ_GROUP: %d\n", DQ_GROUP);
+	$display("DQ_WIDTH: %d\n", DQ_WIDTH);
+end
+
+`ifdef RTL_SIM
+        localparam   tIORT		    = 1; //(DATA_RATE == 2 && CL == 2) ? 1 : 0;
+`else
+        localparam   tIORT		    = tIORT_u;
+`endif
+
+localparam	s_INIT		= 2'b00;
+localparam	s_IDLE		= 2'b01;
+localparam	s_WR_SHIFT	= 2'b10;
+localparam	s_WR_RESP	= 2'b11;
+localparam	s_RD_ADDR	= 2'b10;
+localparam	s_RD_INIT	= 2'b10;
+localparam	s_RD_SHIFT	= 2'b11;
+localparam	SDR_DWIDTH	= DQ_GROUP*DQ_WIDTH;
+localparam	SDR_BWIDTH	= DATA_RATE*SDR_DWIDTH;
+localparam	DIN_WIDTH	= AXI_WDATA_WIDTH;
+localparam	DOUT_WIDTH	= AXI_RDATA_WIDTH;
+
+wire    r_AXI4_WREADY_c;
+
+reg		[1:0]r_axi4_wrstate_1P;
+reg		[1:0]r_axi4_rastate_1P;
+reg		[1:0]r_axi4_rdstate_1P;
+reg		r_axi4_nwr_1P;
+reg		r_AXI4_AWREADY_1P;
+reg		r_AXI4_AWLEN_1P;
+//reg		r_AXI4_WREADY_c;
+reg		r_AXI4_WLAST_1P;
+reg		r_AXI4_BVALID_1P;
+reg		r_AXI4_ARREADY_1P;
+reg		[7:0]r_AXI4_ARLEN_1P;
+reg		r_AXI4_RVALID_1P;
+reg		[AXI_BID_WIDTH-1:0]r_AXI4_BID_1P;
+reg		[AXI_ARID_WIDTH-1:0]r_AXI4_RID_1P;
+
+reg		r_we_1P;
+reg		r_re_1P;
+reg		r_last_1P;
+reg		[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0]r_addr_1P;
+reg		[DIN_WIDTH-1:0]r_din_1P;
+reg     [DIN_WIDTH/8-1:0]r_dm_1P;
+reg		[6:0]r_size_1P;
+reg		[6:0]r_shift_cnt_1P;
+reg		[6:0]r_addr_cnt_1P;
+reg		[7:0]r_arlen_cnt_1P;
+reg		[8:0]arlen_cnt;
+
+reg		r_wr_ack_1P;
+reg		r_AXI4_WREADY_2P;
+reg		r_re_lock_1P;
+
+reg		[AXI_ARID_WIDTH-1:0]r_AXI4_RID[0:CL+tIORT+1];
+reg		[DOUT_WIDTH+AXI_ARID_WIDTH:0]r_dout_1P;
+reg		r_fifo_wr_1P;
+reg		r_fifo_rd_1P;
+
+wire	[SDR_BWIDTH-1:0]w_dout;
+wire	w_sdr_init_done;
+wire	w_wr_ack;
+wire	w_rd_ack;
+wire	w_ref_req;
+wire	w_rd_valid;
+
+wire	[AXI_RDATA_WIDTH+AXI_ARID_WIDTH:0]w_fifo_dout;
+wire    rd_last;
+wire	w_afull;
+wire	w_empty;
+
+wire	[1:0]c_addr_increment;
+assign	c_addr_increment	= DATA_RATE;
+assign	o_pll_reset			= i_aresetn;
+
+`IP_MODULE_NAME(sdram_controller)
+#(
+	.fSYS_MHz			(fSYS_MHz),
+	.fCK_MHz			(fCK_MHz),
+	.REF_LATENCY		(4),
+	.tIORT_u		    (tIORT_u),
+	.DDIO_TYPE			(DDIO_TYPE),
+	.tPWRUP				(tPWRUP),	// 100 us
+	.tRAS				(tRAS),		// 44 ns
+	.tRAS_MAX			(tRAS_MAX),	// 120 us
+	.tRC				(tRC),		// 66 ns
+	.tRCD				(tRCD),		// 20 ns
+	.tREF				(tREF),		// 64 ms
+	.tRFC				(tRFC),		// 66 ns
+	.tRP				(tRP),		// 20 ns
+	.tWR				(tWR),		// 1 CK+7.5 ns
+	.tMRD				(tMRD),		// 2 CK
+	.CL					(CL),		// 3 CK
+	.BL					(BL),
+	.BA_WIDTH			(BA_WIDTH),
+	.ROW_WIDTH			(ROW_WIDTH),
+	.COL_WIDTH			(COL_WIDTH),
+    .DATA_RATE          (DATA_RATE),
+	.DQ_WIDTH			(DQ_WIDTH),	// x4, x8
+	.DQ_GROUP			(DQ_GROUP)
+	//			x4	x8	x16	x32
+	// DQ_WIDTH	4	8	8	8
+	// DQ_GROUP	1	1	2	4
+)
+inst_sdram_controller
+(
+	.i_arst			(~i_aresetn),
+	.i_sysclk		(i_sysclk),
+	.i_sdrclk		(i_sdrclk),
+	.i_tACclk		(i_tACclk),
+	.i_pll_locked	(i_pll_locked),
+	
+	.i_we			(r_we_1P),
+	.i_re			(r_re_1P),
+	.i_last			(r_last_1P),
+	.i_addr			(r_addr_1P),
+	.i_din			(r_din_1P[SDR_BWIDTH-1:0]),
+    .i_dm           (r_dm_1P[(SDR_BWIDTH/8)-1:0]),
+	.o_dout			(w_dout),
+	.o_sdr_state	(o_sdr_state),	// debug use
+	.o_sdr_init_done(w_sdr_init_done),
+	.o_wr_ack		(w_wr_ack),
+	.o_rd_ack		(w_rd_ack),
+	.o_ref_req		(w_ref_req),
+	.o_rd_valid		(w_rd_valid),
+	
+	.o_sdr_CKE		(o_sdr_CKE),
+	.o_sdr_n_CS		(o_sdr_n_CS),
+	.o_sdr_n_RAS	(o_sdr_n_RAS),
+	.o_sdr_n_CAS	(o_sdr_n_CAS),
+	.o_sdr_n_WE		(o_sdr_n_WE),
+	.o_sdr_BA		(o_sdr_BA),
+	.o_sdr_ADDR		(o_sdr_ADDR),
+	.o_sdr_DATA		(o_sdr_DATA),
+	.o_sdr_DATA_oe	(o_sdr_DATA_oe),
+	.i_sdr_DATA		(i_sdr_DATA),
+	.o_sdr_DQM		(o_sdr_DQM),
+	
+	.o_dbg_ref_req	(o_dbg_ref_req),
+	.o_dbg_n_CS		(o_dbg_n_CS),
+	.o_dbg_n_RAS	(o_dbg_n_RAS),
+	.o_dbg_n_CAS	(o_dbg_n_CAS),
+	.o_dbg_n_WE		(o_dbg_n_WE),
+	.o_dbg_BA		(o_dbg_BA),
+	.o_dbg_ADDR		(o_dbg_ADDR),
+	.o_dbg_DATA_out	(o_dbg_DATA_out),
+	.o_dbg_DATA_in	(o_dbg_DATA_in),
+	.o_dbg_wr_ack	(o_dbg_wr_ack),
+	.o_dbg_rd_ack	(o_dbg_rd_ack)
+);
+
+`IP_MODULE_NAME(dual_clock_fifo_wrapper)
+#(
+	.DATA_WIDTH(AXI_RDATA_WIDTH+AXI_ARID_WIDTH+1),
+	.ADDR_WIDTH(8),
+	.LATENCY(2),
+	.FIFO_MODE("STD_FIFO"),
+	.RAM_INIT_FILE(""),
+	.COMPATIBILITY("E"),
+	.OUTPUT_REG("FALSE"),
+	.CHECK_FULL("TRUE"),
+	.CHECK_EMPTY("TRUE"),
+	.AFULL_THRESHOLD(2**8-1),
+	.AEMPTY_THRESHOLD(1)
+)
+inst_dual_clock_fifo_wrapper
+(
+	.i_arst(~i_aresetn),
+	
+	.i_wclk(i_sysclk),
+	.i_we(r_fifo_wr_1P),
+	.i_wdata(r_dout_1P),
+	
+	.i_rclk(i_sysclk),
+	.i_re(r_fifo_rd_1P || (r_AXI4_RVALID_1P && i_AXI4_RREADY)),
+	
+	.o_full(w_afull),
+	.o_empty(w_empty),
+	.o_rdata(w_fifo_dout),
+
+	.o_afull(),
+	.o_wcnt(),
+	.o_aempty(),
+	.o_rcnt(),
+	
+	.o_dbg_we(o_dbg_fifo_we),
+	.o_dbg_waddr(o_dbg_fifo_waddr),
+	.o_dbg_re(o_dbg_fifo_re),
+	.o_dbg_raddr(o_dbg_fifo_raddr)
+);
+
+always@(negedge i_aresetn or posedge i_sysclk)
+begin
+	if (~i_aresetn)
+	begin
+		r_axi4_wrstate_1P	<= s_INIT;
+		r_axi4_rastate_1P	<= s_INIT;
+		r_axi4_rdstate_1P	<= s_INIT;
+		r_axi4_nwr_1P		<= 1'b0;
+		
+		r_AXI4_AWREADY_1P	<= 1'b0;
+		r_AXI4_AWLEN_1P		<= 1'b0;
+		//r_AXI4_WREADY_c	<= 1'b0;
+		r_AXI4_WLAST_1P		<= 1'b0;
+		r_AXI4_BVALID_1P	<= 1'b0;
+		r_AXI4_ARREADY_1P	<= 1'b0;
+		r_AXI4_ARLEN_1P		<= {8{1'b0}};
+		r_AXI4_RVALID_1P	<= 1'b0;
+		r_AXI4_BID_1P		<= {AXI_BID_WIDTH{1'b0}};
+		r_AXI4_RID_1P		<= {AXI_ARID_WIDTH{1'b0}};
+		
+		r_we_1P				<= 1'b0;
+		r_re_1P				<= 1'b0;
+		r_last_1P			<= 1'b0;
+		r_addr_1P			<= {BA_WIDTH+ROW_WIDTH+COL_WIDTH{1'b0}};
+		r_din_1P			<= {DIN_WIDTH{1'b0}};
+		r_dm_1P             <= {DIN_WIDTH/8{1'b0}};
+		r_size_1P			<= {7{1'b0}};
+		r_shift_cnt_1P		<= {7{1'b0}};
+		arlen_cnt           <= {9{1'b0}};
+		r_addr_cnt_1P		<= {7{1'b0}};
+		r_arlen_cnt_1P		<= {8{1'b0}};
+		
+		r_wr_ack_1P			<= 1'b0;
+		r_AXI4_WREADY_2P	<= 1'b0;
+		r_re_lock_1P		<= 1'b0;
+		
+		r_AXI4_RID[0]		<= {AXI_ARID_WIDTH{1'b0}};
+		r_dout_1P			<= {DOUT_WIDTH+AXI_ARID_WIDTH+1{1'b0}};
+		r_fifo_wr_1P		<= 1'b0;
+		r_fifo_rd_1P		<= 1'b0;
+	end
+	else if (i_pll_locked)
+	begin
+		r_axi4_nwr_1P		<= ~r_axi4_nwr_1P;
+		r_AXI4_AWREADY_1P	<= 1'b0;
+		//r_AXI4_WREADY_c	<= 1'b0;
+		r_AXI4_ARREADY_1P	<= 1'b0;
+		
+		r_wr_ack_1P			<= w_wr_ack;
+		r_AXI4_WREADY_2P	<= r_AXI4_WREADY_c;
+		
+		r_AXI4_RID[0]		<= r_AXI4_RID_1P;
+		r_fifo_wr_1P		<= 1'b0;
+		r_fifo_rd_1P		<= 1'b0;
+		
+		case (r_axi4_wrstate_1P)
+			s_INIT:
+			begin
+				if (w_sdr_init_done)
+					r_axi4_wrstate_1P	<= s_IDLE;
+			end
+			
+			s_IDLE:
+			begin
+				if (i_AXI4_AWVALID && i_AXI4_WVALID &&
+					~r_axi4_nwr_1P && ~r_re_lock_1P)
+				begin
+					r_axi4_wrstate_1P	<= s_WR_SHIFT;
+					r_AXI4_AWREADY_1P	<= 1'b1;
+					if (i_AXI4_AWLEN != {8{1'b0}})
+						r_AXI4_AWLEN_1P	<= 1'b1;
+					else
+						r_AXI4_AWLEN_1P	<= 1'b0;
+					r_AXI4_WLAST_1P		<= i_AXI4_WLAST;
+					if (AXI_AWID_WIDTH >= AXI_BID_WIDTH)
+						r_AXI4_BID_1P	<= i_AXI4_AWID[AXI_BID_WIDTH-1:0];
+					else
+						r_AXI4_BID_1P	<= {{AXI_BID_WIDTH-AXI_AWID_WIDTH{1'b0}}, i_AXI4_AWID};
+					
+					r_we_1P			<= 1'b1;
+					// TODO AXI different width support
+					if (SDR_BWIDTH > AXI_WDATA_WIDTH)
+					begin
+						r_addr_1P[0+:BA_WIDTH+ROW_WIDTH+COL_WIDTH-(0-SDR_BWIDTH/AXI_WDATA_WIDTH+1)]	<= i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0-SDR_BWIDTH/AXI_WDATA_WIDTH+1];
+						// $display("foo_gt\n");
+					end
+					else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
+					begin
+						r_addr_1P	<= {i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:COL_WIDTH], {(DATA_RATE-1){1'b0}}, i_AXI4_AWADDR[COL_WIDTH-1:DATA_RATE-1]};
+						//r_addr_1P	<= {{(DATA_RATE-1){1'b0}},i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:DATA_RATE-1]};
+						// $display("foo_eq\n");
+					end
+					
+					if (SDR_BWIDTH > AXI_WDATA_WIDTH)
+					begin
+						//r_AXI4_WREADY_c				<= 1'b1;
+						r_size_1P						<= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1;
+						r_shift_cnt_1P					<= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1;
+						// $display("SDR_BWIDTH %d > AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
+					end
+					else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
+					begin
+						if (i_AXI4_WLAST)
+						begin
+							r_din_1P			<= i_AXI4_WDATA;
+							r_dm_1P             <= i_AXI4_WSTRB ^ {(AXI_WDATA_WIDTH/8){1'b1}}; //bitwise XOR to inver the bit
+							r_last_1P			<= 1'b1;
+						end
+						r_size_1P			<= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1;
+						r_shift_cnt_1P		<= {7{1'b0}};
+						// $display("SDR_BWIDTH %d = AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
+					end
+					else
+					begin
+						//r_AXI4_WREADY_c	<= 1'b1;
+						r_size_1P			<= AXI_WDATA_WIDTH/SDR_BWIDTH-1'b1;
+						r_shift_cnt_1P		<= AXI_WDATA_WIDTH/SDR_BWIDTH-1'b1;
+						// $display("SDR_BWIDTH %d < AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
+					end
+				end
+			end
+			
+			s_WR_SHIFT:
+			begin
+				if (SDR_BWIDTH > AXI_WDATA_WIDTH)
+				begin
+					if (r_shift_cnt_1P != 7'd0)
+					begin
+						if (r_AXI4_WREADY_c)
+							r_shift_cnt_1P		<= r_shift_cnt_1P-1'b1;
+					end
+					else
+					begin
+						r_shift_cnt_1P		<= r_size_1P;
+					end
+				end		
+				else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
+				begin
+					if (r_AXI4_WREADY_2P)
+						r_addr_1P	<= r_addr_1P+c_addr_increment;
+					
+					if (r_AXI4_WREADY_c) 
+				    begin
+						r_din_1P	<= i_AXI4_WDATA;
+					    r_dm_1P     <= i_AXI4_WSTRB ^ {(AXI_WDATA_WIDTH/8){1'b1}}; //bitwise XOR to inver the bit;
+					end
+					
+					if (~r_AXI4_WREADY_c & r_AXI4_WREADY_2P & i_AXI4_WLAST)
+					begin
+						r_din_1P	<= i_AXI4_WDATA;
+						r_dm_1P     <= i_AXI4_WSTRB ^ {(AXI_WDATA_WIDTH/8){1'b1}}; //bitwise XOR to inver the bit;
+					end
+				end
+				
+				if (w_wr_ack)
+				begin
+					/*if (SDR_BWIDTH < AXI_WDATA_WIDTH)
+					begin
+						if (r_size_1P != `BYTES_TX_1)
+							r_addr_1P	<= r_addr_1P+c_addr_increment;
+						else if (~r_wr_ack_1P)
+							r_addr_1P	<= r_addr_1P+c_addr_increment;
+						else if (r_AXI4_WREADY_2P)
+							r_addr_1P	<= r_addr_1P+c_addr_increment;
+						
+						r_shift_cnt_1P	<= r_shift_cnt_1P-1'b1;
+						if (r_AXI4_WLAST_1P && r_shift_cnt_1P == 7'd1)
+							r_last_1P	<= 1'b1;
+					end
+					else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
+					begin
+						r_AXI4_WREADY_c	<= 1'b1;
+					end
+					else
+					begin
+						r_AXI4_WREADY_c	<= 1'b1;
+						
+						if (r_AXI4_WREADY_c)
+							r_addr_1P	<= r_addr_1P+1'b1;
+						
+						if (r_shift_cnt_1P == 7'd1)
+						begin
+							if (i_AXI4_WLAST || r_AXI4_WLAST_1P)
+							begin
+								r_axi4_wrstate_1P	<= s_WR_RESP;
+								r_AXI4_WREADY_c	<= 1'b0;
+								r_AXI4_WLAST_1P		<= 1'b0;
+								r_AXI4_BVALID_1P	<= 1'b1;
+								
+								r_last_1P			<= 1'b1;
+							end
+						end
+					end*/
+					
+					if (r_shift_cnt_1P == 7'd0)
+					begin	
+						//r_AXI4_WREADY_c	<= 1'b1;
+						
+						r_AXI4_WLAST_1P	<= i_AXI4_WLAST;
+						r_shift_cnt_1P	<= r_size_1P;
+						
+						if (i_AXI4_WLAST && r_size_1P == {7{1'b0}} && r_AXI4_AWLEN_1P)
+						begin
+							r_axi4_wrstate_1P	<= s_WR_RESP;
+							//r_AXI4_WREADY_c	<= ~r_AXI4_WREADY_c;
+							r_AXI4_WLAST_1P		<= 1'b0;
+							r_AXI4_BVALID_1P	<= 1'b1;
+							
+							r_we_1P				<= 1'b1;
+							r_last_1P			<= 1'b1;
+						end
+						else if (r_AXI4_WLAST_1P)
+						begin
+							r_axi4_wrstate_1P	<= s_WR_RESP;
+							//r_AXI4_WREADY_c	<= ~r_AXI4_WREADY_c;
+							r_AXI4_WLAST_1P		<= 1'b0;
+							r_AXI4_BVALID_1P	<= 1'b1;
+							
+							r_we_1P				<= 1'b0;
+							r_last_1P			<= 1'b0;
+						end
+					end
+				end
+			end
+			
+			s_WR_RESP:
+			begin
+				r_we_1P		<= 1'b0;
+				r_last_1P	<= 1'b0;
+				
+				if (i_AXI4_BREADY)
+				begin
+					r_axi4_wrstate_1P	<= s_IDLE;
+					r_AXI4_BVALID_1P	<= 1'b0;
+				end
+			end
+		endcase
+		
+		case (r_axi4_rastate_1P)
+			s_INIT:
+			begin
+				if (w_sdr_init_done)
+					r_axi4_rastate_1P	<= s_IDLE;
+			end
+			
+			s_IDLE:
+			begin
+				if (i_AXI4_ARVALID && r_axi4_nwr_1P
+					&& ~r_we_1P && ~w_afull && ~r_AXI4_RVALID_1P)
+				begin
+					r_axi4_rastate_1P	<= s_RD_ADDR;
+					r_AXI4_ARREADY_1P	<= 1'b1;
+					r_AXI4_RID_1P		<= i_AXI4_ARID;
+					
+					r_re_1P				<= 1'b1;
+					r_re_lock_1P		<= 1'b1;
+					if (i_AXI4_ARLEN == 8'd0 && (SDR_BWIDTH == AXI_RDATA_WIDTH))
+						r_last_1P		<= 1'b1;
+					
+					// TODO AXI different width support
+					if (SDR_BWIDTH > AXI_RDATA_WIDTH)
+					begin
+						r_addr_1P[0+:BA_WIDTH+ROW_WIDTH+COL_WIDTH-(0-SDR_BWIDTH/AXI_RDATA_WIDTH+1)]	<= i_AXI4_ARADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0-SDR_BWIDTH/AXI_RDATA_WIDTH+1];
+					end
+					else if (SDR_BWIDTH == AXI_RDATA_WIDTH)
+					begin
+						r_addr_1P	<= {i_AXI4_ARADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:COL_WIDTH], {(DATA_RATE-1){1'b0}}, i_AXI4_ARADDR[COL_WIDTH-1:DATA_RATE-1]};
+						//r_addr_1P	<= {{(DATA_RATE-1){1'b0}},i_AXI4_ARADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:DATA_RATE-1]};
+					end
+					
+					if (SDR_BWIDTH > AXI_WDATA_WIDTH)
+					begin
+						r_size_1P		<= SDR_BWIDTH/AXI_RDATA_WIDTH-1'b1;
+						r_shift_cnt_1P	<= SDR_BWIDTH/AXI_RDATA_WIDTH-1'b1;
+						r_addr_cnt_1P	<= SDR_BWIDTH/AXI_RDATA_WIDTH-1'b1;
+					end
+					else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
+					begin
+						r_AXI4_ARLEN_1P	<= i_AXI4_ARLEN;
+						r_size_1P		<= 7'd0;
+						r_shift_cnt_1P	<= 7'd0;
+						r_addr_cnt_1P	<= 7'd0;
+						r_arlen_cnt_1P	<= i_AXI4_ARLEN;
+					end
+					else
+					begin
+						r_AXI4_ARLEN_1P	<= i_AXI4_ARLEN;
+						r_size_1P		<= AXI_RDATA_WIDTH/SDR_BWIDTH-1'b1;
+						r_shift_cnt_1P	<= AXI_RDATA_WIDTH/SDR_BWIDTH-1'b1;
+						r_addr_cnt_1P	<= AXI_RDATA_WIDTH/SDR_BWIDTH-1'b1;
+						r_arlen_cnt_1P	<= i_AXI4_ARLEN;
+					end
+				end
+			end
+			
+			s_RD_ADDR:
+			begin
+				if (~w_afull)
+					r_re_1P	<= 1'b1;
+				
+				if (w_rd_ack)
+				begin
+					if (w_afull)
+						r_re_1P	<= 1'b0;
+					if (SDR_BWIDTH < AXI_WDATA_WIDTH)
+						r_addr_1P		<= r_addr_1P+c_addr_increment;
+					else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
+						r_addr_1P		<= r_addr_1P+c_addr_increment;
+					else
+						r_addr_1P		<= r_addr_1P+1'b1;
+					
+					r_addr_cnt_1P	<= r_addr_cnt_1P-1'b1;
+					if (r_addr_cnt_1P == 7'd0)
+					begin
+						r_addr_cnt_1P	<= r_size_1P;
+						r_arlen_cnt_1P	<= r_arlen_cnt_1P-1'b1;
+					end
+					
+					if (r_arlen_cnt_1P == 8'd1 && (SDR_BWIDTH == AXI_RDATA_WIDTH))
+						r_last_1P	<= 1'b1;
+					
+					if (r_arlen_cnt_1P == 8'd0)
+					begin
+						if (r_addr_cnt_1P == 8'd1)
+							r_last_1P	<= 1'b1;
+						
+						if (r_addr_cnt_1P == 8'd0)
+						begin
+							r_axi4_rastate_1P	<= s_IDLE;
+							
+							r_re_1P			<= 1'b0;
+							r_last_1P		<= 1'b0;
+							r_re_lock_1P	<= 1'b0;
+						end
+					end
+				end
+			end
+		endcase
+		
+		if (w_rd_valid)
+		begin
+			if (SDR_BWIDTH >= AXI_RDATA_WIDTH)
+			begin
+				r_dout_1P[DOUT_WIDTH-1:0]	<= w_dout;
+			end
+			
+			r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH-1:DOUT_WIDTH]	<= r_AXI4_RID[CL+tIORT+1];
+			
+			r_shift_cnt_1P	<= r_shift_cnt_1P-1'b1;
+			
+			if (r_shift_cnt_1P == 7'd0)
+			begin
+				r_fifo_wr_1P	<= 1'b1;
+				
+				if (arlen_cnt == r_AXI4_ARLEN_1P) begin
+			        arlen_cnt   <= {9{1'b0}};
+			    end
+				else begin
+					arlen_cnt	<= arlen_cnt+1'b1;
+		        end
+		        
+		        if (arlen_cnt == r_AXI4_ARLEN_1P)
+		            r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH]    <= 1'b1;
+		        else
+		        	r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH]    <= 1'b0;
+				r_shift_cnt_1P	<= r_size_1P;
+			end
+		end
+		
+		case (r_axi4_rdstate_1P)
+			s_INIT:
+			begin
+				if (w_sdr_init_done)
+					r_axi4_rdstate_1P	<= s_IDLE;
+			end
+			
+			s_IDLE:
+			begin
+				if (~w_empty & r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH])
+				begin
+					r_axi4_rdstate_1P	<= s_RD_SHIFT;
+					r_fifo_rd_1P		<= 1'b1;
+					r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH]	<= 1'b0;
+				end
+			end
+			
+			s_RD_SHIFT:
+			begin
+				r_AXI4_RVALID_1P	<= 1'b1;
+				
+				if (i_AXI4_RREADY)
+				begin
+					if (w_empty)
+					begin
+						r_axi4_rdstate_1P	<= s_IDLE;
+						r_AXI4_RVALID_1P	<= 1'b0;
+					end
+				
+					if (rd_last)
+					begin
+						r_axi4_rdstate_1P	<= s_IDLE;
+						r_AXI4_RVALID_1P	<= 1'b0;
+					end
+				end
+			end
+		endcase
+	end
+end
+
+genvar i;
+generate
+	for (i=0; i<CL+tIORT+1; i=i+1)
+	begin: pipe
+		always@(negedge i_aresetn or posedge i_sysclk)
+		begin
+			if (~i_aresetn)
+				r_AXI4_RID[i+1]	<= {AXI_ARID_WIDTH{1'b0}};
+			else
+				r_AXI4_RID[i+1]	<= r_AXI4_RID[i];
+		end
+	end
+endgenerate
+
+assign r_AXI4_WREADY_c = w_wr_ack;
+assign rd_last = r_AXI4_RVALID_1P ? w_fifo_dout[AXI_RDATA_WIDTH+AXI_ARID_WIDTH] : 1'b0;
+
+assign	o_AXI4_AWREADY	= r_AXI4_AWREADY_1P;
+assign	o_AXI4_WREADY	= r_AXI4_WREADY_c;
+assign	o_AXI4_BVALID	= r_AXI4_BVALID_1P;
+assign	o_AXI4_ARREADY	= r_AXI4_ARREADY_1P;
+assign	o_AXI4_RVALID	= r_AXI4_RVALID_1P;
+assign	o_AXI4_RDATA	= w_fifo_dout[AXI_RDATA_WIDTH-1:0];
+assign	o_AXI4_RLAST	= rd_last;
+assign	o_AXI4_BID		= r_AXI4_BID_1P;
+assign	o_AXI4_RID		= w_fifo_dout[AXI_RDATA_WIDTH+AXI_ARID_WIDTH-1:AXI_RDATA_WIDTH];
+assign	o_AXI4_BRESP	= `OKAY;
+assign	o_AXI4_BUSER	= {AXI_BUSER_WIDTH{1'b0}};
+assign	o_AXI4_RRESP	= `OKAY;
+assign	o_AXI4_RUSER	= {AXI_RUSER_WIDTH{1'b0}};
+
+assign	o_dbg_we			= r_we_1P;
+assign	o_dbg_re			= r_re_1P;
+assign	o_dbg_last			= r_last_1P;
+assign	o_dbg_addr			= r_addr_1P;
+assign	o_dbg_din			= r_din_1P;
+assign	o_sdr_rd_valid		= w_rd_valid;
+assign	o_sdr_dout			= r_dout_1P;
+assign	o_axi4_wrstate		= r_axi4_wrstate_1P;
+assign	o_dbg_axi4_wlast	= r_AXI4_WLAST_1P;
+assign	o_axi4_rastate		= r_axi4_rastate_1P;
+assign	o_axi4_rdstate		= r_axi4_rdstate_1P;
+assign	o_axi4_nwr			= r_axi4_nwr_1P;
+assign	o_re_lock			= r_re_lock_1P;
+assign	o_shift_cnt			= r_shift_cnt_1P;
+assign	o_axi4_arlen		= r_AXI4_ARLEN_1P;
+assign	o_fifo_wr			= r_fifo_wr_1P;
+assign	o_fifo_full			= w_afull;
+assign	o_fifo_empty		= w_empty;
+
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+//////////////////////////////////////////////////////////////////////////////projects/SWIP/hxlai/workplace/test/20201008_184659/testbench_random
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   axi4.vh
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      axi4 header file
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+// AxSIZE
+`define	BYTES_TX_1		3'b000
+`define	BYTES_TX_2		3'b001
+`define	BYTES_TX_4		3'b010
+`define	BYTES_TX_8		3'b011
+`define	BYTES_TX_16		3'b100
+`define	BYTES_TX_32		3'b101
+`define	BYTES_TX_64		3'b110
+`define	BYTES_TX_128	3'b111
+
+// AxBURST
+`define	FIXED		2'b00
+`define	INCR		2'b01
+`define	WRAP		2'b10
+`define	RESERVED	2'b11
+
+// xRESP
+`define	OKAY	2'b00
+`define	EXOKAY	2'b01
+`define	SLVERR	2'b10
+`define	DECERR	2'b11
+
+// AxCACHE
+`define	B_BIT	0
+`define	M_BIT	1
+`define	OA_BIT	2
+`define	A_BIT	3
+
+// AxPROT
+`define	PRIVILEGED	0
+`define	SECURE		1
+`define	DATA_INSTR	2
+
+// AxLOCK
+`define	NORMAL		1'b0
+`define	EXCLUSIVE	1'b1
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   `IP_MODULE_NAME(dual_clock_fifo_wrapper).v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      wraps around dual clock fifo
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+module `IP_MODULE_NAME(dual_clock_fifo_wrapper)
+#(
+	parameter	DATA_WIDTH		= 8,
+	parameter	ADDR_WIDTH		= 8,
+	parameter	LATENCY			= 1,
+	parameter	FIFO_MODE		= "STD_FIFO",
+	parameter	RAM_INIT_FILE	= "",
+	/////////////////////////////////////////////////////////////////////////////////////
+	// compatibility	output_reg			check_full_overflow		check_empty_underflow
+	/////////////////////////////////////////////////////////////////////////////////////
+	// E				user configurable	user configurable		user configurable
+	// X				user configurable	always on				always on
+	// A				always off			user configurable		user configurable
+	parameter	COMPATIBILITY	= "E",
+	parameter	OUTPUT_REG		= "TRUE",
+	parameter	CHECK_FULL		= "TRUE",
+	parameter	CHECK_EMPTY		= "TRUE",
+	parameter	AFULL_THRESHOLD	= 2**ADDR_WIDTH-1,
+	parameter	AEMPTY_THRESHOLD= 1
+)
+(
+	input						i_arst,
+	
+	input						i_wclk,
+	input						i_we,
+	input	[DATA_WIDTH-1:0]	i_wdata,
+	
+	input						i_rclk,
+	input						i_re,
+	
+	output						o_full,
+	output						o_empty,
+	output	[DATA_WIDTH-1:0]	o_rdata,
+	
+	output						o_afull,
+	output	[ADDR_WIDTH-1:0]	o_wcnt,
+	output						o_aempty,
+	output	[ADDR_WIDTH-1:0]	o_rcnt,
+	
+	output						o_dbg_we,
+	output	[ADDR_WIDTH-1:0]	o_dbg_waddr,
+	output						o_dbg_re,
+	output	[ADDR_WIDTH-1:0]	o_dbg_raddr
+);
+
+generate
+	if (COMPATIBILITY == "X")
+	begin
+		if (FIFO_MODE == "BYPASS")
+		begin
+			`IP_MODULE_NAME(dual_clock_fifo)
+			#(
+				.DATA_WIDTH			(DATA_WIDTH),
+				.ADDR_WIDTH			(ADDR_WIDTH),
+				.LATENCY			(LATENCY+4),
+				.FIFO_MODE			(FIFO_MODE),
+				.RAM_INIT_FILE		(RAM_INIT_FILE),
+				.COMPATIBILITY		(COMPATIBILITY),
+				.OUTPUT_REG			("FALSE"),
+				.CHECK_FULL			("TRUE"),
+				.CHECK_EMPTY		("TRUE"),
+				.AFULL_THRESHOLD	(AFULL_THRESHOLD),
+				.AEMPTY_THRESHOLD	(AEMPTY_THRESHOLD)
+			)
+			inst_dual_clock_fifo
+			(
+				.i_arst		(i_arst),
+				.i_wclk		(i_wclk),
+				.i_we		(i_we),
+				.i_wdata	(i_wdata),
+				.i_rclk		(i_rclk),
+				.i_re		(i_re),
+				.o_full		(o_full),
+				.o_empty	(o_empty),
+				.o_rdata	(o_rdata),
+				
+				.o_afull	(o_afull),
+				.o_wcnt		(o_wcnt),
+				.o_aempty	(o_aempty),
+				.o_rcnt		(o_rcnt),
+				
+				.o_dbg_we	(o_dbg_we),
+				.o_dbg_waddr(o_dbg_waddr),
+				.o_dbg_re	(o_dbg_re),
+				.o_dbg_raddr(o_dbg_raddr)
+			);
+		end
+		else
+		begin
+			`IP_MODULE_NAME(dual_clock_fifo)
+			#(
+				.DATA_WIDTH			(DATA_WIDTH),
+				.ADDR_WIDTH			(ADDR_WIDTH),
+				.LATENCY			(LATENCY+2),
+				.FIFO_MODE			(FIFO_MODE),
+				.RAM_INIT_FILE		(RAM_INIT_FILE),
+				.COMPATIBILITY		(COMPATIBILITY),
+				.OUTPUT_REG			(OUTPUT_REG),
+				.CHECK_FULL			("TRUE"),
+				.CHECK_EMPTY		("TRUE"),
+				.AFULL_THRESHOLD	(AFULL_THRESHOLD),
+				.AEMPTY_THRESHOLD	(AEMPTY_THRESHOLD)
+			)
+			inst_dual_clock_fifo
+			(
+				.i_arst		(i_arst),
+				.i_wclk		(i_wclk),
+				.i_we		(i_we),
+				.i_wdata	(i_wdata),
+				.i_rclk		(i_rclk),
+				.i_re		(i_re),
+				.o_full		(o_full),
+				.o_empty	(o_empty),
+				.o_rdata	(o_rdata),
+				
+				.o_afull	(o_afull),
+				.o_wcnt		(o_wcnt),
+				.o_aempty	(o_aempty),
+				.o_rcnt		(o_rcnt),
+				
+				.o_dbg_we	(o_dbg_we),
+				.o_dbg_waddr(o_dbg_waddr),
+				.o_dbg_re	(o_dbg_re),
+				.o_dbg_raddr(o_dbg_raddr)
+			);
+		end
+	end
+	else if (COMPATIBILITY == "A")
+	begin
+		`IP_MODULE_NAME(dual_clock_fifo)
+		#(
+			.DATA_WIDTH			(DATA_WIDTH),
+			.ADDR_WIDTH			(ADDR_WIDTH),
+			.LATENCY			(LATENCY),
+			.FIFO_MODE			(FIFO_MODE),
+			.RAM_INIT_FILE		(RAM_INIT_FILE),
+			.COMPATIBILITY		(COMPATIBILITY),
+			.OUTPUT_REG			("FALSE"),
+			.CHECK_FULL			(CHECK_FULL),
+			.CHECK_EMPTY		(CHECK_EMPTY),
+			.AFULL_THRESHOLD	(AFULL_THRESHOLD),
+			.AEMPTY_THRESHOLD	(AEMPTY_THRESHOLD)
+		)
+		inst_dual_clock_fifo
+		(
+			.i_arst		(i_arst),
+			.i_wclk		(i_wclk),
+			.i_we		(i_we),
+			.i_wdata	(i_wdata),
+			.i_rclk		(i_rclk),
+			.i_re		(i_re),
+			.o_full		(o_full),
+			.o_empty	(o_empty),
+			.o_rdata	(o_rdata),
+			
+			.o_afull	(o_afull),
+			.o_wcnt		(o_wcnt),
+			.o_aempty	(o_aempty),
+			.o_rcnt		(o_rcnt),
+			
+			.o_dbg_we	(o_dbg_we),
+			.o_dbg_waddr(o_dbg_waddr),
+			.o_dbg_re	(o_dbg_re),
+			.o_dbg_raddr(o_dbg_raddr)
+		);
+	end
+	else
+	begin
+		`IP_MODULE_NAME(dual_clock_fifo)
+		#(
+			.DATA_WIDTH			(DATA_WIDTH),
+			.ADDR_WIDTH			(ADDR_WIDTH),
+			.LATENCY			(LATENCY),
+			.FIFO_MODE			(FIFO_MODE),
+			.RAM_INIT_FILE		(RAM_INIT_FILE),
+			.COMPATIBILITY		(COMPATIBILITY),
+			.OUTPUT_REG			(OUTPUT_REG),
+			.CHECK_FULL			(CHECK_FULL),
+			.CHECK_EMPTY		(CHECK_EMPTY),
+			.AFULL_THRESHOLD	(AFULL_THRESHOLD),
+			.AEMPTY_THRESHOLD	(AEMPTY_THRESHOLD)
+		)
+		inst_dual_clock_fifo
+		(
+			.i_arst		(i_arst),
+			.i_wclk		(i_wclk),
+			.i_we		(i_we),
+			.i_wdata	(i_wdata),
+			.i_rclk		(i_rclk),
+			.i_re		(i_re),
+			.o_full		(o_full),
+			.o_empty	(o_empty),
+			.o_rdata	(o_rdata),
+			
+			.o_afull	(o_afull),
+			.o_wcnt		(o_wcnt),
+			.o_aempty	(o_aempty),
+			.o_rcnt		(o_rcnt),
+			
+			.o_dbg_we	(o_dbg_we),
+			.o_dbg_waddr(o_dbg_waddr),
+			.o_dbg_re	(o_dbg_re),
+			.o_dbg_raddr(o_dbg_raddr)
+		);
+	end
+endgenerate
+
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   `IP_MODULE_NAME(dual_clock_fifo).v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      dual clock fifo
+//  /_/ /\ \_____/ /     
+// ____/  \_______/     
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module `IP_MODULE_NAME(dual_clock_fifo)
+#(
+	parameter	DATA_WIDTH		= 8,
+	parameter	ADDR_WIDTH		= 8,
+	parameter	LATENCY			= 1,
+	parameter	FIFO_MODE		= "STD_FIFO",
+	parameter	RAM_INIT_FILE	= "",
+	parameter	COMPATIBILITY	= "E",
+	parameter	OUTPUT_REG		= "FALSE",
+	parameter	CHECK_FULL		= "TRUE",
+	parameter	CHECK_EMPTY		= "TRUE",
+	parameter	AFULL_THRESHOLD	= 2**ADDR_WIDTH-1,
+	parameter	AEMPTY_THRESHOLD= 1
+)
+(
+	input						i_arst,
+	
+	input						i_wclk,
+	input						i_we,
+	input	[DATA_WIDTH-1:0]	i_wdata,
+	
+	input						i_rclk,
+	input						i_re,
+	
+	output						o_full,
+	output						o_empty,
+	output	[DATA_WIDTH-1:0]	o_rdata,
+	
+	output						o_afull,
+	output	[ADDR_WIDTH-1:0]	o_wcnt,
+	output						o_aempty,
+	output	[ADDR_WIDTH-1:0]	o_rcnt,
+	
+	output						o_dbg_we,
+	output	[ADDR_WIDTH-1:0]	o_dbg_waddr,
+	output						o_dbg_re,
+	output	[ADDR_WIDTH-1:0]	o_dbg_raddr
+);
+
+reg		[ADDR_WIDTH:0]	r_waddrb_1P;
+reg						r_wflag_1P;
+reg		[ADDR_WIDTH-1:0]r_waddrg_1P;
+reg		[ADDR_WIDTH-1:0]r_waddrg_2P;
+
+reg		[ADDR_WIDTH:0]r_raddrb_wclk_1P;
+reg		[ADDR_WIDTH:0]r_raddrb_wclk_neg;
+reg		[ADDR_WIDTH:0]wr_cnt;
+
+reg		[ADDR_WIDTH:0]r_waddrb_rclk_1P;
+reg		[ADDR_WIDTH:0]r_waddrb_rclk_neg;
+reg		[ADDR_WIDTH:0]rd_cnt;
+
+reg						r_we_1P;
+reg						r_re_1P;
+reg		[ADDR_WIDTH:0]	r_raddrb_1P;
+reg						r_rflag_1P;
+reg		[ADDR_WIDTH-1:0]r_raddrg_1P;
+reg						r_rflag_2P;
+reg		[ADDR_WIDTH-1:0]r_raddrg_2P;
+
+reg		[LATENCY-1:0]	r_empty;
+reg		[LATENCY:0]		r_full;
+
+wire	[ADDR_WIDTH:0]	w_waddrb_1P;
+wire					w_wflag_1P;
+wire	[ADDR_WIDTH-1:0]w_waddrg_1P;
+
+wire	[ADDR_WIDTH:0]	w_raddrb_1P;
+wire					w_rflag_1P;
+wire	[ADDR_WIDTH-1:0]w_raddrg_1P;
+
+wire	w_empty;
+wire	w_full;
+
+wire	w_empty_P;
+wire	w_full_P;
+
+wire					w_we;
+wire					w_re;
+wire	[ADDR_WIDTH-1:0]w_raddr;
+
+assign	w_waddrb_1P					=	r_waddrb_1P + 1'b1;
+assign	w_wflag_1P					=	w_waddrb_1P[ADDR_WIDTH];
+assign	w_waddrg_1P[ADDR_WIDTH-1]	=	w_waddrb_1P[ADDR_WIDTH-1] ^ 1'b0;
+assign	w_waddrg_1P[ADDR_WIDTH-2:0]	=	w_waddrb_1P[ADDR_WIDTH-2:0] ^ w_waddrb_1P[ADDR_WIDTH-1:1];
+
+assign	w_full	=	((r_waddrg_1P == r_raddrg_1P) &
+					(r_wflag_1P != r_rflag_1P))?
+						1'b1:
+					(i_we &
+					((w_waddrg_1P == r_raddrg_2P) &
+					(w_wflag_1P != r_rflag_2P)))?
+						1'b1:
+						1'b0;
+
+always@(posedge i_arst or posedge i_wclk)
+begin
+	if (i_arst) begin
+		r_raddrb_wclk_1P	<= {ADDR_WIDTH+1{1'b0}};
+	end
+	else begin
+		r_raddrb_wclk_1P	<= r_raddrb_1P;
+	end
+end
+
+always@(posedge i_arst or posedge i_wclk)
+begin
+	if (i_arst) begin
+		r_raddrb_wclk_neg	<= {ADDR_WIDTH+1{1'b0}};
+	end
+	else begin
+		r_raddrb_wclk_neg	<= ~r_raddrb_wclk_1P + 1'b1;
+	end
+end
+
+always@(posedge i_arst or posedge i_wclk)
+begin
+	if (i_arst) begin
+		wr_cnt			<= {ADDR_WIDTH+1{1'b0}};
+	end
+	else begin
+		wr_cnt			<= r_waddrb_1P + r_raddrb_wclk_neg;
+	end
+end
+
+always@(posedge i_arst or posedge i_rclk)
+begin
+	if (i_arst) begin
+		r_waddrb_rclk_1P	<= {ADDR_WIDTH+1{1'b0}};
+	end
+	else begin
+		r_waddrb_rclk_1P	<= r_waddrb_1P;
+	end
+end
+
+always@(posedge i_arst or posedge i_rclk)
+begin
+	if (i_arst) begin
+		r_waddrb_rclk_neg	<= {ADDR_WIDTH+1{1'b0}};
+	end
+	else begin
+		r_waddrb_rclk_neg	<= ~r_waddrb_rclk_1P;
+	end
+end
+
+always@(posedge i_arst or posedge i_rclk)
+begin
+	if (i_arst) begin
+		rd_cnt			<= {ADDR_WIDTH+1{1'b0}};
+	end
+	else begin
+		rd_cnt			<= r_raddrb_1P + r_waddrb_rclk_neg;
+	end
+end
+
+always@(posedge i_arst or posedge i_wclk)
+begin
+	if (i_arst)
+	begin
+		r_we_1P			<= 1'b0;
+		r_waddrb_1P		<= {ADDR_WIDTH{1'b0}};
+		r_wflag_1P		<= 1'b0;
+		r_waddrg_1P		<= {ADDR_WIDTH{1'b0}};
+		r_waddrg_2P		<= {ADDR_WIDTH{1'b0}};
+		
+		r_full[0]		<= 1'b0;
+	end
+	else
+	begin
+		r_we_1P	<= 1'b0;
+
+		if (CHECK_FULL == "TRUE")
+		begin
+			if (i_we & ~w_full_P)
+			begin
+				r_we_1P			<= 1'b1;
+				r_waddrb_1P		<= w_waddrb_1P;
+				r_wflag_1P		<= w_wflag_1P;
+				r_waddrg_1P		<= w_waddrg_1P;
+			end
+		end
+		else
+		begin
+			if (i_we)
+			begin
+				r_we_1P			<= 1'b1;
+				r_waddrb_1P		<= w_waddrb_1P;
+				r_wflag_1P		<= w_wflag_1P;
+				r_waddrg_1P		<= w_waddrg_1P;
+			end
+		end
+		
+		if (r_we_1P)
+			r_waddrg_2P		<= r_waddrg_1P;
+		
+		r_full[0]		<= w_full;
+	end
+end
+
+assign	w_raddrb_1P					=	r_raddrb_1P + 1'b1;
+assign	w_rflag_1P					=	w_raddrb_1P[ADDR_WIDTH];
+assign	w_raddrg_1P[ADDR_WIDTH-1]	=	w_raddrb_1P[ADDR_WIDTH-1] ^ 1'b0;
+assign	w_raddrg_1P[ADDR_WIDTH-2:0]	=	w_raddrb_1P[ADDR_WIDTH-2:0] ^ w_raddrb_1P[ADDR_WIDTH-1:1];
+
+assign	w_empty	=	((r_waddrg_2P == r_raddrg_1P) &
+					(r_wflag_1P == r_rflag_2P))?
+						1'b1:
+					(i_re &
+					((r_waddrg_1P == r_raddrg_1P) &
+					(r_wflag_1P == r_rflag_1P)))?
+						1'b1:
+						1'b0;
+
+always@(posedge i_arst or posedge i_rclk)
+begin
+	if (i_arst)
+	begin
+		r_re_1P			<= 1'b0;
+		r_raddrb_1P		<= {ADDR_WIDTH{1'b0}};
+		r_rflag_1P		<= 1'b0;
+		r_raddrg_1P		<= {ADDR_WIDTH{1'b0}};
+		r_rflag_2P		<= 1'b0;
+		r_raddrg_2P		<= {ADDR_WIDTH{1'b0}};
+		
+		r_empty[0]		<= 1'b1;
+	end
+	else
+	begin
+		r_re_1P	<= 1'b0;
+		
+		if (CHECK_FULL == "TRUE")
+		begin
+			if (i_re & ~w_empty_P)
+			begin
+				r_re_1P			<= 1'b1;
+				r_raddrb_1P		<= w_raddrb_1P;
+				r_rflag_1P		<= w_rflag_1P;
+				r_raddrg_1P		<= w_raddrg_1P;
+			end
+		end
+		else
+		begin
+			if (i_re)
+			begin
+				r_re_1P			<= 1'b1;
+				r_raddrb_1P		<= w_raddrb_1P;
+				r_rflag_1P		<= w_rflag_1P;
+				r_raddrg_1P		<= w_raddrg_1P;
+			end
+		end
+		
+		if (r_re_1P)
+		begin
+			r_raddrg_2P		<= r_raddrg_1P;
+			r_rflag_2P		<= r_rflag_1P;
+		end
+		
+		r_empty[0]		<= w_empty;
+	end
+end
+
+genvar i, j;
+generate
+	for (i=1; i<LATENCY; i=i+1)
+	begin: pipe_empty
+		always@(posedge i_arst or posedge i_rclk)
+		begin
+			if (i_arst)
+				r_empty[i]	<= 1'b1;
+			else
+				r_empty[i]	<= r_empty[i-1];
+		end
+	end
+	
+	assign	w_empty_P	= w_empty | r_empty[LATENCY-1];
+	
+	for (j=1; j<LATENCY+1; j=j+1)
+	begin: pipe_full
+		always@(posedge i_arst or posedge i_wclk)
+		begin
+			if (i_arst)
+				r_full[j]	<= 1'b0;
+			else
+				r_full[j]	<= r_full[j-1];
+		end
+	end
+	
+	if (COMPATIBILITY == "X")
+		if (FIFO_MODE == "BYPASS")
+			assign	w_full_P	= r_full[0] | r_full[LATENCY-2];
+		else
+			assign	w_full_P	= r_full[0]	| r_full[LATENCY];
+	else
+		assign	w_full_P	= r_full[0] | r_full[LATENCY-1];
+	
+	if (CHECK_FULL == "TRUE")
+		assign	w_we	= i_we & ~w_full_P;
+	else
+		assign	w_we	= i_we;
+	
+	if (FIFO_MODE == "BYPASS")
+	begin
+		assign	w_re	= 1'b1;
+		if (CHECK_EMPTY == "TRUE")
+			assign	w_raddr	= (i_re & ~w_empty_P)?
+								w_raddrg_1P[ADDR_WIDTH-1:0]:
+								r_raddrg_1P[ADDR_WIDTH-1:0];
+		else
+			assign	w_raddr	= (i_re)?
+								w_raddrg_1P[ADDR_WIDTH-1:0]:
+								r_raddrg_1P[ADDR_WIDTH-1:0];
+	end
+	else
+	begin
+		if (CHECK_EMPTY == "TRUE")
+			assign	w_re	= i_re & ~w_empty_P;
+		else
+			assign	w_re	= i_re;
+		assign	w_raddr	= r_raddrg_1P[ADDR_WIDTH-1:0];
+	end
+
+	`IP_MODULE_NAME(sdram_simple_dual_port_ram)
+	#(
+		.DATA_WIDTH(DATA_WIDTH),
+		.ADDR_WIDTH(ADDR_WIDTH),
+		.OUTPUT_REG(OUTPUT_REG),
+		.RAM_INIT_FILE(RAM_INIT_FILE)
+	)
+	inst_simple_dual_port_ram
+	(
+		.wdata(i_wdata),
+		.waddr(r_waddrg_1P[ADDR_WIDTH-1:0]),
+		.raddr(w_raddr),
+		.we(w_we),
+		.wclk(i_wclk),
+		.re(w_re),
+		.rclk(i_rclk),
+		.rdata(o_rdata)
+	);
+endgenerate
+
+assign	o_empty	= w_empty_P;
+assign	o_full	= w_full_P;
+
+assign	o_aempty= w_empty_P | (rd_cnt[ADDR_WIDTH-1] & rd_cnt[ADDR_WIDTH-2] & rd_cnt[ADDR_WIDTH-3]);
+assign	o_wcnt	= wr_cnt[ADDR_WIDTH] ? {ADDR_WIDTH{1'b1}} : wr_cnt[ADDR_WIDTH-1:0];
+assign	o_afull	= w_full_P | wr_cnt[ADDR_WIDTH] | (wr_cnt[ADDR_WIDTH-1] & wr_cnt[ADDR_WIDTH-2] & wr_cnt[ADDR_WIDTH-3]);
+assign	o_rcnt	= w_full_P ? {ADDR_WIDTH{1'b0}} : rd_cnt[ADDR_WIDTH-1:0];
+
+assign	o_dbg_we	= w_we;
+assign	o_dbg_waddr	= r_waddrg_1P[ADDR_WIDTH-1:0];
+assign	o_dbg_re	= w_re;
+assign	o_dbg_raddr	= w_raddr;
+
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   `IP_MODULE_NAME(efx_sdram_controller).v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      SDRAM controller top module
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_sdram_controller)
+(
+	i_aresetn,
+	i_arst,
+	i_sysclk,
+	i_sdrclk,
+	i_tACclk,
+	i_pll_locked,
+	o_pll_reset,
+	i_we,
+	i_re,
+	i_last,
+	i_addr,
+	i_din,
+        i_dm,
+	o_dout,
+	o_sdr_init_done,
+	o_wr_ack,
+	o_rd_ack,
+	o_ref_req,
+	o_rd_valid,
+	o_AXI4_AWREADY,
+	i_AXI4_AWADDR,
+	i_AXI4_AWPROT,
+	i_AXI4_AWVALID,
+	o_AXI4_WREADY,
+	i_AXI4_WDATA,
+	i_AXI4_WLAST,
+	i_AXI4_WVALID,
+	o_AXI4_BVALID,
+	i_AXI4_BREADY,
+	o_AXI4_ARREADY,
+	i_AXI4_ARADDR,
+	i_AXI4_ARPROT,
+    i_AXI4_ARVALID,
+	i_AXI4_RREADY,
+	o_AXI4_RDATA,
+	o_AXI4_RLAST,
+	o_AXI4_RVALID,
+	i_AXI4_AWID,
+	i_AXI4_AWREGION,
+	i_AXI4_AWLEN,
+	i_AXI4_AWSIZE,
+	i_AXI4_AWBURST,
+	i_AXI4_AWLOCK,
+	i_AXI4_AWCACHE,
+	i_AXI4_AWQOS,
+	i_AXI4_AWUSER,
+	i_AXI4_WSTRB,
+	i_AXI4_WUSER,
+	o_AXI4_BID,
+	o_AXI4_BRESP,					
+	o_AXI4_BUSER,	
+	i_AXI4_ARID,
+	i_AXI4_ARREGION,				
+	i_AXI4_ARLEN,
+	i_AXI4_ARSIZE,
+	i_AXI4_ARBURST,					
+	i_AXI4_ARLOCK,							
+	i_AXI4_ARCACHE,				
+	i_AXI4_ARQOS,					
+	i_AXI4_ARUSER,	
+	o_AXI4_RID,
+	o_AXI4_RRESP,						
+	o_AXI4_RUSER,
+	o_sdr_CKE,
+	o_sdr_n_CS,
+	o_sdr_n_RAS,
+	o_sdr_n_CAS,
+	o_sdr_n_WE,
+	o_sdr_BA,
+	o_sdr_ADDR,
+	o_sdr_DATA,
+	o_sdr_DATA_oe,
+	i_sdr_DATA,
+	o_sdr_DQM,
+	o_dbg_dly_cnt_b,
+	o_dbg_tRCD_done,
+	o_dbg_tRTW_done,
+	o_dbg_ref_req,
+	o_dbg_wr_ack,
+	o_dbg_rd_ack,
+	o_sdr_state,
+	o_dbg_we,
+	o_dbg_re,
+	o_dbg_last,
+	o_dbg_addr,
+	o_dbg_din,
+	o_sdr_rd_valid,
+	o_sdr_dout,
+	o_axi4_wrstate,
+	o_dbg_axi4_wlast,
+	o_axi4_rastate,
+	o_axi4_rdstate,
+	o_axi4_nwr,
+	o_re_lock,
+	o_shift_cnt,
+	o_axi4_arlen,
+	o_fifo_wr,
+	o_fifo_full,
+	o_fifo_empty,
+	o_dbg_fifo_we,
+	o_dbg_fifo_waddr,
+	o_dbg_fifo_re,
+	o_dbg_fifo_raddr,
+    o_dbg_n_CS,
+    o_dbg_n_RAS,
+    o_dbg_n_CAS,
+    o_dbg_n_WE,
+    o_dbg_BA,
+    o_dbg_ADDR,
+    o_dbg_DATA_out,
+    o_dbg_DATA_in
+);
+
+	parameter	AXI_AWADDR_WIDTH	= 25;
+	parameter	AXI_WDATA_WIDTH		= 64;
+	parameter	AXI_ARADDR_WIDTH	= 25;
+	parameter	AXI_RDATA_WIDTH		= 64;
+                                    
+	parameter	fSYS_MHz		= 100;
+	parameter	fCK_MHz			= 200;
+	parameter   DATA_RATE       = 2;
+	parameter	DDIO_TYPE		= "SOFT";
+	parameter	tPWRUP			= 200000;			// 100 us
+	parameter	tRAS			= 44;			// 44 ns
+	parameter	tRAS_MAX		= 120000;		// 120 us
+	parameter	tRC			    = 66;			// 66 ns
+	parameter	tRCD			= 20;			// 20 ns
+	parameter	tREF			= 64000000;			// 64 ms
+	parameter	tRFC			= 66;			// 66 ns
+	parameter	tRP			    = 20;			// 20 ns
+	parameter	tWR			    = 2;			// 1 CK+7.5 ns
+	parameter	tMRD			= 2;			// 2 CK
+	parameter	CL			    = 3;			// 3 CK
+	parameter	BL			    = 1;
+    parameter   tIORT_u		    = 2;
+	parameter	BA_WIDTH		= 2;
+	parameter	ROW_WIDTH		= 13;
+	parameter	COL_WIDTH		= 10;
+	parameter	DQ_WIDTH		= 8;	// x4; x8
+	parameter	DQ_GROUP		= 4;
+	parameter   SDRAM_MODE      = "AXI4";
+	
+	//----- parameter not configurable by user----
+	parameter	AXI_AWID_WIDTH		= 4;
+	parameter	AXI_AWUSER_WIDTH	= 2;
+	parameter	AXI_WUSER_WIDTH		= 2;
+	parameter	AXI_BID_WIDTH		= 4;
+	parameter	AXI_BUSER_WIDTH		= 2;
+	parameter	AXI_ARID_WIDTH		= 4;
+	parameter	AXI_ARUSER_WIDTH	= 3;
+	parameter	AXI_RUSER_WIDTH		= 3;
+	
+	//Common
+	input i_aresetn;
+	input i_arst;
+	input i_sysclk;
+	input i_sdrclk;
+	input i_tACclk;
+	input i_pll_locked;
+	output	o_pll_reset;
+	
+	//Native 
+	input	i_we;
+	input	i_re;
+	input	i_last;
+	input	[(BA_WIDTH+ROW_WIDTH+COL_WIDTH)	-1:0]				i_addr;
+	input	[DATA_RATE	*DQ_GROUP		*DQ_WIDTH		-1:0]	i_din;
+        input   [(DATA_RATE     *DQ_GROUP               *DQ_WIDTH)/8    -1:0]           i_dm;
+	output	[DATA_RATE	*DQ_GROUP		*DQ_WIDTH		-1:0]	o_dout;
+	output	o_sdr_init_done;
+	output	o_wr_ack;
+	output	o_rd_ack;
+	output	o_ref_req;
+	output	o_rd_valid;
+	
+	//AXI4
+	output wire o_AXI4_AWREADY;
+	input  	[AXI_AWADDR_WIDTH-1:0] i_AXI4_AWADDR;
+	input  	[2:0] i_AXI4_AWPROT;
+	input  	i_AXI4_AWVALID;
+	
+	output 	o_AXI4_WREADY;
+	input  	[AXI_WDATA_WIDTH-1:0] i_AXI4_WDATA;
+	input  	i_AXI4_WLAST;
+	input  	i_AXI4_WVALID;
+	
+	output 	o_AXI4_BVALID;
+	input 	i_AXI4_BREADY;
+	
+	output 	o_AXI4_ARREADY;
+	input 	[AXI_ARADDR_WIDTH-1:0] i_AXI4_ARADDR;
+	input 	[2:0] i_AXI4_ARPROT;
+    input 	i_AXI4_ARVALID;
+	
+	input 	i_AXI4_RREADY;
+	output	[AXI_RDATA_WIDTH-1:0] o_AXI4_RDATA;
+	output 	o_AXI4_RLAST;
+	output  o_AXI4_RVALID;
+	
+	input	[AXI_AWID_WIDTH-1:0] i_AXI4_AWID;
+	input	[3:0] i_AXI4_AWREGION;
+	input	[7:0] i_AXI4_AWLEN;
+	input	[2:0] i_AXI4_AWSIZE;
+	input	[1:0] i_AXI4_AWBURST;
+	input  	i_AXI4_AWLOCK;
+	input	[3:0] i_AXI4_AWCACHE;
+	input	[3:0] i_AXI4_AWQOS;
+	input	[AXI_AWUSER_WIDTH-1:0] i_AXI4_AWUSER;
+	input	[AXI_WDATA_WIDTH/8-1:0] i_AXI4_WSTRB;
+	input	[AXI_WUSER_WIDTH-1:0] i_AXI4_WUSER;
+	
+	output	[AXI_BID_WIDTH-1:0] o_AXI4_BID;
+	output	[1:0] o_AXI4_BRESP;					
+	output	[AXI_BUSER_WIDTH-1:0] o_AXI4_BUSER;	
+	
+	input	[AXI_ARID_WIDTH-1:0] i_AXI4_ARID;
+	input	[3:0] i_AXI4_ARREGION;				
+	input	[7:0] i_AXI4_ARLEN;
+	input	[2:0] i_AXI4_ARSIZE;
+	input	[1:0] i_AXI4_ARBURST;					
+	input	i_AXI4_ARLOCK;							
+	input	[3:0] i_AXI4_ARCACHE;				
+	input	[3:0] i_AXI4_ARQOS;					
+	input	[AXI_ARUSER_WIDTH-1:0] i_AXI4_ARUSER;	
+	
+	output	[AXI_ARID_WIDTH-1:0] o_AXI4_RID;
+	output	[1:0] o_AXI4_RRESP;						
+	output	[AXI_RUSER_WIDTH-1:0] o_AXI4_RUSER;
+	
+	output	[DATA_RATE							-1:0]	o_sdr_CKE;
+	output	[DATA_RATE							-1:0]	o_sdr_n_CS;
+	output	[DATA_RATE							-1:0]	o_sdr_n_RAS;
+	output	[DATA_RATE							-1:0]	o_sdr_n_CAS;
+	output	[DATA_RATE							-1:0]	o_sdr_n_WE;
+	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_sdr_BA;
+	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_sdr_ADDR;
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA;
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_oe;
+	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA;
+	output	[DATA_RATE	*DQ_GROUP				-1:0]	o_sdr_DQM;
+	
+	// Debug port
+	output	[5:0] o_dbg_dly_cnt_b;
+	output	o_dbg_tRCD_done;
+	output	o_dbg_tRTW_done;
+	output	o_dbg_ref_req;
+	output	o_dbg_wr_ack;
+	output	o_dbg_rd_ack;
+	output	[3:0] o_sdr_state;
+	output	o_dbg_we;
+	output	o_dbg_re;
+	output	o_dbg_last;
+	output	[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0] o_dbg_addr;
+	output	[AXI_WDATA_WIDTH-1:0] o_dbg_din;
+	output	o_sdr_rd_valid;
+	output	[DATA_RATE*DQ_GROUP*DQ_WIDTH+AXI_ARID_WIDTH:0] o_sdr_dout;
+	output	[1:0] o_axi4_wrstate;
+	output	o_dbg_axi4_wlast;
+	output	[1:0] o_axi4_rastate;
+	output	[1:0] o_axi4_rdstate;
+	output	o_axi4_nwr;
+	output	o_re_lock;
+	output	[6:0] o_shift_cnt;
+	output	[7:0] o_axi4_arlen;
+	output	o_fifo_wr;
+	output	o_fifo_full;
+	output	o_fifo_empty;
+	output	o_dbg_fifo_we;
+	output	[7:0] o_dbg_fifo_waddr;
+	output	o_dbg_fifo_re;
+	output	[7:0] o_dbg_fifo_raddr;
+	
+	output	[DATA_RATE							-1:0]	o_dbg_n_CS;
+	output	[DATA_RATE							-1:0]	o_dbg_n_RAS;
+	output	[DATA_RATE							-1:0]	o_dbg_n_CAS;
+	output	[DATA_RATE							-1:0]	o_dbg_n_WE;
+	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_dbg_BA;
+	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_dbg_ADDR;
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_dbg_DATA_out;
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_dbg_DATA_in;
+	
+generate
+   if (SDRAM_MODE == "AXI4") begin
+   `IP_MODULE_NAME(axi4_sdram_controller)
+   #(
+	.AXI_AWADDR_WIDTH	(AXI_AWADDR_WIDTH),
+	.AXI_WDATA_WIDTH	(AXI_WDATA_WIDTH),
+	.AXI_ARADDR_WIDTH	(AXI_ARADDR_WIDTH),
+	.AXI_RDATA_WIDTH	(AXI_RDATA_WIDTH),
+	.fSYS_MHz			(fSYS_MHz),
+	.fCK_MHz			(fCK_MHz),
+	.DDIO_TYPE	        (DDIO_TYPE),
+	.tPWRUP		        (tPWRUP),
+	.tRAS		        (tRAS),
+	.tRAS_MAX	        (tRAS_MAX),
+	.tRC		        (tRC),
+	.tRCD		        (tRCD),
+	.tREF		        (tREF),
+	.tRFC		        (tRFC),
+	.tRP		        (tRP),
+	.tWR		        (tWR),
+	.tMRD		        (tMRD),
+	.CL			        (CL),
+	.BL			        (BL),
+	.DATA_RATE          (DATA_RATE),
+	.tIORT_u		    (tIORT_u),
+	.BA_WIDTH	        (BA_WIDTH),
+	.ROW_WIDTH	        (ROW_WIDTH),
+	.COL_WIDTH	        (COL_WIDTH),
+	.DQ_WIDTH	        (DQ_WIDTH),
+	.DQ_GROUP	        (DQ_GROUP),
+    .AXI_AWID_WIDTH	    (AXI_AWID_WIDTH	     ),
+    .AXI_AWUSER_WIDTH   (AXI_AWUSER_WIDTH    ),
+    .AXI_WUSER_WIDTH	(AXI_WUSER_WIDTH	 ),
+    .AXI_BID_WIDTH	    (AXI_BID_WIDTH	     ),
+    .AXI_BUSER_WIDTH	(AXI_BUSER_WIDTH	 ),
+    .AXI_ARID_WIDTH	    (AXI_ARID_WIDTH	     ),
+    .AXI_ARUSER_WIDTH   (AXI_ARUSER_WIDTH    ),
+    .AXI_RUSER_WIDTH	(AXI_RUSER_WIDTH	 )
+	)
+	inst_axi4_sdram_controller
+	(
+	.i_aresetn			(i_aresetn),
+	.i_sysclk			(i_sysclk),
+	.i_sdrclk			(i_sdrclk),
+	.i_tACclk			(i_tACclk),
+	.i_pll_locked		(i_pll_locked),
+	
+	.o_AXI4_AWREADY		(o_AXI4_AWREADY),
+	.i_AXI4_AWADDR		(i_AXI4_AWADDR),
+	.i_AXI4_AWPROT		(i_AXI4_AWPROT),
+	.i_AXI4_AWVALID		(i_AXI4_AWVALID),
+	
+	.o_AXI4_WREADY		(o_AXI4_WREADY),
+	.i_AXI4_WDATA		(i_AXI4_WDATA),
+	.i_AXI4_WLAST		(i_AXI4_WLAST),
+	.i_AXI4_WVALID		(i_AXI4_WVALID),
+	
+	.o_AXI4_BVALID		(o_AXI4_BVALID),
+	.i_AXI4_BREADY		(i_AXI4_BREADY),
+	
+	.o_AXI4_ARREADY		(o_AXI4_ARREADY),
+	.i_AXI4_ARADDR		(i_AXI4_ARADDR),
+	.i_AXI4_ARPROT		(i_AXI4_ARPROT),
+	.i_AXI4_ARVALID		(i_AXI4_ARVALID),
+	
+	.i_AXI4_RREADY		(i_AXI4_RREADY),
+	.o_AXI4_RDATA		(o_AXI4_RDATA),
+	.o_AXI4_RLAST		(o_AXI4_RLAST),
+	.o_AXI4_RVALID		(o_AXI4_RVALID),
+	
+	.i_AXI4_AWID		(i_AXI4_AWID),
+	.i_AXI4_AWREGION	(i_AXI4_AWREGION),
+	.i_AXI4_AWLEN		(i_AXI4_AWLEN),
+	.i_AXI4_AWSIZE		(i_AXI4_AWSIZE),
+	.i_AXI4_AWBURST		(i_AXI4_AWBURST),
+	.i_AXI4_AWLOCK		(i_AXI4_AWLOCK),
+	.i_AXI4_AWCACHE		(i_AXI4_AWCACHE),
+	.i_AXI4_AWQOS		(i_AXI4_AWQOS),
+	.i_AXI4_AWUSER		(i_AXI4_AWUSER),
+	
+	.i_AXI4_WSTRB		(i_AXI4_WSTRB),
+	.i_AXI4_WUSER		(i_AXI4_WUSER),
+	
+	.o_AXI4_BID			(o_AXI4_BID),
+	.o_AXI4_BRESP		(o_AXI4_BRESP),
+	.o_AXI4_BUSER		(o_AXI4_BUSER),
+	
+	.i_AXI4_ARID		(i_AXI4_ARID),
+	.i_AXI4_ARREGION	(i_AXI4_ARREGION),
+	.i_AXI4_ARLEN		(i_AXI4_ARLEN),
+	.i_AXI4_ARSIZE		(i_AXI4_ARSIZE),
+	.i_AXI4_ARBURST		(i_AXI4_ARBURST),
+	.i_AXI4_ARLOCK		(i_AXI4_ARLOCK),
+	.i_AXI4_ARCACHE		(i_AXI4_ARCACHE),
+	.i_AXI4_ARQOS		(i_AXI4_ARQOS),
+	.i_AXI4_ARUSER		(i_AXI4_ARUSER),
+	
+	.o_AXI4_RID			(o_AXI4_RID),
+	.o_AXI4_RRESP		(o_AXI4_RRESP),
+	.o_AXI4_RUSER		(o_AXI4_RUSER),
+	
+	.o_sdr_CKE			(o_sdr_CKE),
+	.o_sdr_n_CS			(o_sdr_n_CS),
+	.o_sdr_n_RAS		(o_sdr_n_RAS),
+	.o_sdr_n_CAS		(o_sdr_n_CAS),
+	.o_sdr_n_WE			(o_sdr_n_WE),
+	.o_sdr_BA			(o_sdr_BA),
+	.o_sdr_ADDR			(o_sdr_ADDR),
+	.o_sdr_DATA			(o_sdr_DATA),
+	.o_sdr_DATA_oe		(o_sdr_DATA_oe),
+	.i_sdr_DATA			(i_sdr_DATA),
+	.o_sdr_DQM			(o_sdr_DQM),
+	
+	.o_sdr_state		(o_sdr_state),
+	.o_dbg_we			(o_dbg_we),
+	.o_dbg_re			(o_dbg_re),
+	.o_dbg_last			(o_dbg_last),
+	.o_dbg_addr			(o_dbg_addr),
+	.o_dbg_din			(o_dbg_din),
+	.o_dbg_wr_ack		(o_dbg_wr_ack),
+	.o_dbg_rd_ack		(o_dbg_rd_ack),
+	.o_sdr_rd_valid		(o_sdr_rd_valid),
+	.o_dbg_ref_req		(o_dbg_ref_req),
+	.o_sdr_dout			(o_sdr_dout),
+	.o_axi4_wrstate		(o_axi4_wrstate),
+	.o_dbg_axi4_wlast	(o_dbg_axi4_wlast),
+	.o_axi4_rastate		(o_axi4_rastate),
+	.o_axi4_rdstate		(o_axi4_rdstate),
+	.o_axi4_nwr			(o_axi4_nwr),
+	.o_re_lock			(o_re_lock),
+	.o_shift_cnt		(o_shift_cnt),
+	.o_axi4_arlen		(o_axi4_arlen),
+	.o_fifo_wr			(o_fifo_wr),
+	.o_fifo_full		(o_fifo_full),
+	.o_fifo_empty		(o_fifo_empty),
+	.o_dbg_fifo_we		(o_dbg_fifo_we),
+	.o_dbg_fifo_waddr	(o_dbg_fifo_waddr),
+	.o_dbg_fifo_re		(o_dbg_fifo_re),
+	.o_dbg_fifo_raddr	(o_dbg_fifo_raddr),
+	
+	.o_dbg_n_CS			(o_dbg_n_CS),
+	.o_dbg_n_RAS		(o_dbg_n_RAS),
+	.o_dbg_n_CAS		(o_dbg_n_CAS),
+	.o_dbg_n_WE			(o_dbg_n_WE),
+	.o_dbg_BA			(o_dbg_BA),
+	.o_dbg_ADDR			(o_dbg_ADDR),
+	.o_dbg_DATA_out		(o_dbg_DATA_out),
+	.o_dbg_DATA_in		(o_dbg_DATA_in)
+);
+end
+else begin
+`IP_MODULE_NAME(sdram_controller)
+#(
+	.fSYS_MHz			(fSYS_MHz),
+	.fCK_MHz			(fCK_MHz),
+	.REF_LATENCY		(2),
+	.tIORT_u	        (tIORT_u),
+	.DDIO_TYPE			(DDIO_TYPE),	
+	.tPWRUP				(tPWRUP),
+	.tRAS				(tRAS),
+	.tRAS_MAX			(tRAS_MAX),
+	.tRC				(tRC),
+	.tRCD				(tRCD),
+	.tREF				(tREF),
+	.tRFC				(tRFC),
+	.tRP				(tRP),
+	.tWR				(tWR),
+	.tMRD				(tMRD),
+	.CL					(CL),
+	.BL					(BL),
+	.BA_WIDTH			(BA_WIDTH),
+	.ROW_WIDTH			(ROW_WIDTH),
+	.COL_WIDTH			(COL_WIDTH),
+    .DATA_RATE          (DATA_RATE),
+	.DQ_WIDTH			(DQ_WIDTH),
+	.DQ_GROUP			(DQ_GROUP)
+)
+inst_sdram_controller
+(
+	.i_arst				(i_arst),
+	.i_sysclk			(i_sysclk),
+	.i_sdrclk			(i_sdrclk),
+	.i_tACclk			(i_tACclk),
+	.i_pll_locked		(i_pll_locked),
+	
+	.i_we				(i_we),
+	.i_re				(i_re),
+	.i_last				(i_last),
+	.i_addr				(i_addr),
+	.i_din				(i_din),
+        .i_dm                           (i_dm),
+	.o_dout				(o_dout),
+	.o_sdr_state		(o_sdr_state),
+	.o_sdr_init_done	(o_sdr_init_done),
+	.o_wr_ack			(o_wr_ack),
+	.o_rd_ack			(o_rd_ack),
+	.o_ref_req			(o_ref_req),
+	.o_rd_valid			(o_rd_valid),
+	
+	.o_sdr_CKE			(o_sdr_CKE),
+	.o_sdr_n_CS			(o_sdr_n_CS),
+	.o_sdr_n_RAS		(o_sdr_n_RAS),
+	.o_sdr_n_CAS		(o_sdr_n_CAS),
+	.o_sdr_n_WE			(o_sdr_n_WE),
+	.o_sdr_BA			(o_sdr_BA),
+	.o_sdr_ADDR			(o_sdr_ADDR),
+	.o_sdr_DATA			(o_sdr_DATA),
+	.o_sdr_DATA_oe		(o_sdr_DATA_oe),
+	.i_sdr_DATA			(i_sdr_DATA),
+	.o_sdr_DQM			(o_sdr_DQM),
+	
+	.o_dbg_dly_cnt_b	(o_dbg_dly_cnt_b),
+	.o_dbg_tRCD_done	(o_dbg_tRCD_done),
+	.o_dbg_tRTW_done	(o_dbg_tRTW_done),
+	.o_dbg_ref_req		(o_dbg_ref_req),
+	.o_dbg_wr_ack		(o_dbg_wr_ack),
+	.o_dbg_rd_ack		(o_dbg_rd_ack),
+	.o_dbg_n_CS			(o_dbg_n_CS),
+	.o_dbg_n_RAS		(o_dbg_n_RAS),
+	.o_dbg_n_CAS		(o_dbg_n_CAS),
+	.o_dbg_n_WE			(o_dbg_n_WE),
+	.o_dbg_BA			(o_dbg_BA),
+	.o_dbg_ADDR			(o_dbg_ADDR),
+	.o_dbg_DATA_out		(o_dbg_DATA_out),
+	.o_dbg_DATA_in		(o_dbg_DATA_in)
+);
+end
+endgenerate
+
+endmodule
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   `IP_MODULE_NAME(sdram_controller).v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      sdram controller top with native interface
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// 1.0 Initial rev
+// *******************************
+////////////////////////////////////////////////////////////////
+
+module `IP_MODULE_NAME(sdram_controller)
+#(
+	parameter	fSYS_MHz		= 100,
+	parameter	fCK_MHz			= 100,
+	parameter	REF_LATENCY		= 2,			// 2 for Native interface, 4 for AXI interface
+	parameter	DDIO_TYPE		= "SOFT",		// SOFT, RTL
+												// HARD, Interface Designer
+	//sdram parameters
+	parameter	tPWRUP			= 100,			// 100 us
+	parameter	tRAS			= 44,			// 44 ns
+	parameter	tRAS_MAX		= 120,			// 120 us
+	parameter	tRC				= 66,		// 66 ns
+	parameter	tRCD			= 20,			// 20 ns
+	parameter	tREF			= 64,			// 64 ms
+	parameter	tRFC			= 66,			// 66 ns
+	parameter	tRP				= 20,		// 20 ns
+	parameter	tWR				= 2,		// 1 CK+7.5 ns
+	parameter	tMRD			= 2,			// 2 CK
+	parameter	CL				= 3,		// 3 CK
+	parameter	BL				= 1,
+	parameter	BA_WIDTH		= 2,
+	parameter	ROW_WIDTH		= 13,
+	parameter	COL_WIDTH		= 10,
+	parameter	DATA_RATE		= 1,	// 1, 2
+    parameter   tIORT_u		    = 2,
+	parameter	DQ_WIDTH		= 8,	// x4, x8
+	parameter	DQ_GROUP		= 8
+	//			x4	x8	x16	x32
+	// DQ_WIDTH	4	8	8	8
+	// DQ_GROUP	1	1	2	4
+)
+(
+	input	i_arst,
+	input	i_sysclk,
+	input	i_sdrclk,	// x2 i_sysclk
+	input	i_tACclk,	// x2 i_sysclk
+	input	i_pll_locked,
+	
+	input	i_we,
+	input	i_re,
+	input	i_last,
+	input	[			(BA_WIDTH+ROW_WIDTH+COL_WIDTH)	-1:0]	i_addr,
+	input	[DATA_RATE	*DQ_GROUP		*DQ_WIDTH		-1:0]	i_din,
+	input	[(DATA_RATE	*DQ_GROUP)                      -1:0]	i_dm,
+	output	[DATA_RATE	*DQ_GROUP		*DQ_WIDTH		-1:0]	o_dout,
+	output	[3:0]o_sdr_state,
+	output	o_sdr_init_done,
+	output	o_wr_ack,
+	output	o_rd_ack,
+	output	o_ref_req,
+	output	o_rd_valid,
+	
+	output	[DATA_RATE							-1:0]	o_sdr_CKE,
+	output	[DATA_RATE							-1:0]	o_sdr_n_CS,
+	output	[DATA_RATE							-1:0]	o_sdr_n_RAS,
+	output	[DATA_RATE							-1:0]	o_sdr_n_CAS,
+	output	[DATA_RATE							-1:0]	o_sdr_n_WE,
+	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_sdr_BA,
+	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_sdr_ADDR,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_oe,
+	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA,
+	output	[DATA_RATE	*DQ_GROUP				-1:0]	o_sdr_DQM,
+	
+	// Debug port
+	output	[5:0]o_dbg_dly_cnt_b,
+	output	o_dbg_tRCD_done,
+	output	o_dbg_tRTW_done,
+	output	o_dbg_ref_req,
+	output	o_dbg_wr_ack,
+	output	o_dbg_rd_ack,
+	output	[DATA_RATE							-1:0]	o_dbg_n_CS,
+	output	[DATA_RATE							-1:0]	o_dbg_n_RAS,
+	output	[DATA_RATE							-1:0]	o_dbg_n_CAS,
+	output	[DATA_RATE							-1:0]	o_dbg_n_WE,
+	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_dbg_BA,
+	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_dbg_ADDR,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_dbg_DATA_out,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_dbg_DATA_in
+);
+`ifdef RTL_SIM
+    localparam   tIORT		    = (DATA_RATE == 2 && CL == 2) ? 1 : 0;
+`else
+    localparam   tIORT		    = tIORT_u;
+`endif
+localparam  PARTIAL_FEATURES = (fCK_MHz == 166 && fSYS_MHz == 166) ? 1 : 0;  //partial features only applicable to 166Mhz fullrate
+localparam  DLY_CNT_A_WIDTH	= (PARTIAL_FEATURES == 1) ? 4 : 6;
+localparam  DLY_CNT_B_WIDTH	= (PARTIAL_FEATURES == 1) ? 4 : 6;
+localparam  CHECK_ACT_BA	= (PARTIAL_FEATURES == 1) ? 1 : 4;
+localparam	BA_MSB	= BA_WIDTH+	ROW_WIDTH+	COL_WIDTH-	1;
+localparam	BA_LSB	= 			ROW_WIDTH+	COL_WIDTH;
+localparam	ROW_MSB	= 			ROW_WIDTH+	COL_WIDTH-	1;
+localparam	ROW_LSB	= 						COL_WIDTH;
+localparam	COL_MSB	=						COL_WIDTH-	1;
+localparam	COL_LSB	= 0;
+
+localparam	CYC_A	= 0;
+localparam	CYC_B	= 1;
+localparam	CYC_C	= 2;
+localparam	CYC_D	= 3;
+
+wire	[DATA_RATE							-1:0]w_sdr_CKE;
+wire	[DATA_RATE							-1:0]w_sdr_n_CS;
+wire	[DATA_RATE							-1:0]w_sdr_n_RAS;
+wire	[DATA_RATE							-1:0]w_sdr_n_CAS;
+wire	[DATA_RATE							-1:0]w_sdr_n_WE;
+wire	[DATA_RATE	*BA_WIDTH				-1:0]w_sdr_BA;
+wire	[DATA_RATE	*ROW_WIDTH				-1:0]w_sdr_ADDR;
+wire	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]w_sdr_DATA_out;
+wire	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]w_sdr_DATA_oe;
+wire	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]w_sdr_DATA_in;
+wire	[DATA_RATE	*DQ_GROUP				-1:0]w_sdr_DQM;
+
+`IP_MODULE_NAME(sdram_fsm)
+#(
+	.fSYS_MHz			(fSYS_MHz),
+	.fCK_MHz			(fCK_MHz),
+	.DLY_CNT_A_WIDTH	(DLY_CNT_A_WIDTH),
+	.DLY_CNT_B_WIDTH	(DLY_CNT_B_WIDTH),
+	.CHECK_ACT_BA		(CHECK_ACT_BA),
+	.REF_LATENCY		(REF_LATENCY),
+    .DATA_RATE	        (DATA_RATE),
+	.tPWRUP				(tPWRUP),
+	.tRAS				(tRAS),
+	.tRAS_MAX			(tRAS_MAX),
+	.tRC				(tRC),
+	.tRCD				(tRCD),
+	.tREF				(tREF),
+	.tRFC				(tRFC),
+	.tRP				(tRP),
+	.tWR				(tWR),
+	.tMRD				(tMRD),
+	.CL					(CL),
+	.BL					(BL),
+	.tIORT				(tIORT),
+	.DDIO_TYPE          (DDIO_TYPE),
+	.BA_WIDTH			(BA_WIDTH),
+	.ROW_WIDTH			(ROW_WIDTH),
+	.COL_WIDTH			(COL_WIDTH),
+	.DQ_WIDTH			(DQ_WIDTH),
+	.DQ_GROUP			(DQ_GROUP)
+)
+inst_sdram_fsm
+(
+	.i_arst				(i_arst),
+	.i_sysclk			(i_sysclk),
+	.i_pll_locked		(i_pll_locked),
+	
+	.i_we				(i_we),
+	.i_re				(i_re),
+	.i_last				(i_last),
+	.i_addr				(i_addr),
+	.i_din				(i_din),
+    .i_dm               (i_dm),
+	.o_dout				(o_dout),
+	.o_sdr_state		(o_sdr_state),
+	.o_sdr_init_done	(o_sdr_init_done),
+	.o_wr_ack			(o_wr_ack),
+	.o_rd_ack			(o_rd_ack),
+	.o_ref_req			(o_ref_req),
+	.o_rd_valid			(o_rd_valid),
+	
+	.o_sdr_CKE			(w_sdr_CKE),
+	.o_sdr_n_CS			(w_sdr_n_CS),
+	.o_sdr_n_RAS		(w_sdr_n_RAS),
+	.o_sdr_n_CAS		(w_sdr_n_CAS),
+	.o_sdr_n_WE			(w_sdr_n_WE),
+	.o_sdr_BA			(w_sdr_BA),
+	.o_sdr_ADDR			(w_sdr_ADDR),
+	.o_sdr_DATA			(w_sdr_DATA_out),
+	.o_sdr_DATA_oe		(w_sdr_DATA_oe),
+	.i_sdr_DATA			(w_sdr_DATA_in),
+	.o_sdr_DQM			(w_sdr_DQM),
+	
+	.o_dbg_dly_cnt_b	(o_dbg_dly_cnt_b),
+	.o_dbg_tRCD_done	(o_dbg_tRCD_done),
+	.o_dbg_tRTW_done	(o_dbg_tRTW_done),
+	.o_dbg_ref_req		(o_dbg_ref_req),
+	.o_dbg_wr_ack		(o_dbg_wr_ack),
+	.o_dbg_rd_ack		(o_dbg_rd_ack),
+	.o_dbg_n_CS			(o_dbg_n_CS),
+	.o_dbg_n_RAS		(o_dbg_n_RAS),
+	.o_dbg_n_CAS		(o_dbg_n_CAS),
+	.o_dbg_n_WE			(o_dbg_n_WE),
+	.o_dbg_BA			(o_dbg_BA),
+	.o_dbg_ADDR			(o_dbg_ADDR)
+);
+
+generate if (DDIO_TYPE == "SOFT" && DATA_RATE > 1) begin
+    `IP_MODULE_NAME(sdram_io_block)
+    #(
+    	.DATA_RATE	(DATA_RATE),
+    	.BA_WIDTH	(BA_WIDTH),
+    	.ROW_WIDTH	(ROW_WIDTH),
+    	.COL_WIDTH	(COL_WIDTH),
+    	.DQ_WIDTH	(DQ_WIDTH),
+    	.DQ_GROUP	(DQ_GROUP)
+    )
+    inst_sdram_io_block
+    (
+    	.i_arst				(i_arst),
+    	.i_sysclk			(i_sysclk),
+    	.i_sdrclk			(i_sdrclk),
+    	.i_tACclk			(i_tACclk),
+    	.i_pll_locked		(i_pll_locked),
+    	
+    	.i_sdr_CKE_core		(w_sdr_CKE),
+    	.i_sdr_n_CS_core	(w_sdr_n_CS),
+    	.i_sdr_n_RAS_core	(w_sdr_n_RAS),
+    	.i_sdr_n_CAS_core	(w_sdr_n_CAS),
+    	.i_sdr_n_WE_core	(w_sdr_n_WE),
+    	.i_sdr_BA_core		(w_sdr_BA),
+    	.i_sdr_ADDR_core	(w_sdr_ADDR),
+    	.i_sdr_DATA_core	(w_sdr_DATA_out),
+    	.i_sdr_DATA_oe_core	(w_sdr_DATA_oe),
+    	.o_sdr_DATA_core	(w_sdr_DATA_in),
+    	.i_sdr_DQM_core		(w_sdr_DQM),
+    	
+    	.o_sdr_CKE_pad		(o_sdr_CKE),
+    	.o_sdr_n_CS_pad		(o_sdr_n_CS),
+    	.o_sdr_n_RAS_pad	(o_sdr_n_RAS),
+    	.o_sdr_n_CAS_pad	(o_sdr_n_CAS),
+    	.o_sdr_n_WE_pad		(o_sdr_n_WE),
+    	.o_sdr_BA_pad		(o_sdr_BA),
+    	.o_sdr_ADDR_pad		(o_sdr_ADDR),
+    	.o_sdr_DATA_pad		(o_sdr_DATA),
+    	.o_sdr_DATA_oe_pad	(o_sdr_DATA_oe),
+    	.i_sdr_DATA_pad		(i_sdr_DATA),
+    	.o_sdr_DQM_pad		(o_sdr_DQM)
+    );
+end
+else begin
+    reg		[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]r_sdr_DATA_in_tACclk_1P;
+    
+    always@(posedge i_arst or posedge i_tACclk)
+    begin
+    	if (i_arst)
+    		r_sdr_DATA_in_tACclk_1P	<= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}};
+    	else
+    		r_sdr_DATA_in_tACclk_1P	<= i_sdr_DATA;
+    end
+    
+    assign	w_sdr_DATA_in	= r_sdr_DATA_in_tACclk_1P;
+    assign	o_sdr_CKE		= w_sdr_CKE;
+    assign	o_sdr_n_CS		= w_sdr_n_CS;
+    assign	o_sdr_n_RAS		= w_sdr_n_RAS;
+    assign	o_sdr_n_CAS		= w_sdr_n_CAS;
+    assign	o_sdr_n_WE		= w_sdr_n_WE;
+    assign	o_sdr_BA		= w_sdr_BA;
+    assign	o_sdr_ADDR		= w_sdr_ADDR;
+    assign	o_sdr_DATA		= w_sdr_DATA_out;
+    assign	o_sdr_DATA_oe	= w_sdr_DATA_oe;
+    assign	o_sdr_DQM		= w_sdr_DQM;   
+end
+endgenerate
+
+assign	o_dbg_DATA_out	= w_sdr_DATA_out;
+assign	o_dbg_DATA_in	= w_sdr_DATA_in;
+
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   `IP_MODULE_NAME(sdram_fsm).v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      sdram controller state machine
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+module `IP_MODULE_NAME(sdram_fsm)
+#(
+	parameter	fSYS_MHz		= 100,
+	parameter	fCK_MHz			= 200,				// MHz
+	parameter	DLY_CNT_A_WIDTH	= 6,
+	parameter	DLY_CNT_B_WIDTH	= 6,
+	parameter	CHECK_ACT_BA	= 4,
+	parameter	REF_LATENCY		= 2,				// 
+	
+	parameter	tPWRUP			= 200,				// 100 us
+	parameter	tRAS			= 44,				// 44 ns
+	parameter	tRAS_MAX		= 120000,			// 120 us
+	parameter	tRC				= 66,				// 66 ns
+	parameter	tRCD			= 20,				// 20 ns
+	parameter	tREF			= 64,				// 64 ms
+	parameter	tRFC			= 66,				// 66 ns
+	parameter	tRP				= 20,				// 20 ns
+	parameter	tWR				= 2,				// 1 CK+7.5 ns
+	parameter	tMRD			= 2,				// 2 CK
+	parameter	CL				= 3,				// 3 CK
+	parameter	BL				= 1,
+	parameter	tIORT			= 2,
+	parameter   DDIO_TYPE       = "SOFT",
+	parameter	DATA_RATE		= 2,	
+	parameter	BA_WIDTH		= 2,
+	parameter	ROW_WIDTH		= 13,
+	parameter	COL_WIDTH		= 10,
+	parameter	DQ_WIDTH		= 8,	// x4, x8
+	parameter	DQ_GROUP		= 4
+	//			x4	x8	x16	x32
+	// DQ_WIDTH	4	8	8	8
+	// DQ_GROUP	1	1	2	4
+)
+(
+	input	i_arst,
+	input	i_sysclk,
+	input	i_pll_locked,
+	
+	input	i_we,
+	input	i_re,
+	input	i_last,
+	input	[			(BA_WIDTH+ROW_WIDTH+COL_WIDTH)	-1:0]	i_addr,
+	input	[DATA_RATE	*DQ_GROUP		*DQ_WIDTH		-1:0]	i_din,
+	input	[(DATA_RATE	*DQ_GROUP)                      -1:0]   i_dm,
+	output	[DATA_RATE	*DQ_GROUP		*DQ_WIDTH		-1:0]	o_dout,
+	output	[3:0]o_sdr_state,
+	output	o_sdr_init_done,
+	output	o_wr_ack,
+	output	o_rd_ack,
+	output	o_ref_req,
+	output	o_rd_valid,
+	
+	output	[DATA_RATE							-1:0]	o_sdr_CKE,
+	output	[DATA_RATE							-1:0]	o_sdr_n_CS,
+	output	[DATA_RATE							-1:0]	o_sdr_n_RAS,
+	output	[DATA_RATE							-1:0]	o_sdr_n_CAS,
+	output	[DATA_RATE							-1:0]	o_sdr_n_WE,
+	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_sdr_BA,
+	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_sdr_ADDR,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_oe,
+	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA,
+	output	[DATA_RATE	*DQ_GROUP				-1:0]	o_sdr_DQM,
+	
+	output	[5:0]o_dbg_dly_cnt_b,
+	output	o_dbg_tRCD_done,
+	output	o_dbg_tRTW_done,
+	output	o_dbg_ref_req,
+	output	o_dbg_wr_ack,
+	output	o_dbg_rd_ack,
+	output	[DATA_RATE							-1:0]	o_dbg_n_CS,
+	output	[DATA_RATE							-1:0]	o_dbg_n_RAS,
+	output	[DATA_RATE							-1:0]	o_dbg_n_CAS,
+	output	[DATA_RATE							-1:0]	o_dbg_n_WE,
+	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_dbg_BA,
+	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_dbg_ADDR
+);
+
+function integer log2;
+	input	integer	val;
+	integer	i;
+	begin
+		log2 = 0;
+		for (i=0; 2**i<val; i=i+1)
+			log2 = i+1;
+	end
+endfunction
+
+localparam	DLY_CNT_C_WIDTH	= 16;  // counter for tPWRUP & tRAS_MAX
+localparam	DLY_CNT_D_WIDTH	= 17;  // counter for tREF
+	
+//localparam	tCK		= (1000/fCK_MHz);
+//+1 for parameter with minimum value, -1 for parameter wth maximum value
+localparam	nPWRUP	= tPWRUP/(1000/fSYS_MHz) + 1;
+localparam	nRAS	= tRAS/(1000/fSYS_MHz) + 1;
+localparam	nRAS_MAX= tRAS_MAX/(1000/fSYS_MHz);
+localparam	nRC		= tRC/(1000/fSYS_MHz) + 1;
+localparam	nRCD	= tRCD/(1000/fSYS_MHz) + 1;
+localparam	nREF	= (tREF/(2**ROW_WIDTH)/100)/(1000/fSYS_MHz);
+localparam	nRFC	= tRFC/(1000/fSYS_MHz) + 1;
+localparam	nRP		= tRP/(1000/fSYS_MHz) + 1;
+localparam	nRTP	= CL-1'b1;
+localparam	nRTW	= CL+tIORT;
+
+//						 CRCW
+//						  AA
+//						 SSSE
+localparam	c_NOP	= 4'b1111;
+localparam	c_ACT	= 4'b0011;
+localparam	c_RD	= 4'b0101;
+localparam	c_WR	= 4'b0100;
+localparam	c_BT	= 4'b0110;
+localparam	c_PRE	= 4'b0010;
+localparam	c_REF	= 4'b0001;
+localparam	c_MRS	= 4'b0000;
+
+localparam	BA_MSB	= BA_WIDTH+	ROW_WIDTH+	COL_WIDTH-	1;
+localparam	BA_LSB	= 			ROW_WIDTH+	COL_WIDTH;
+localparam	ROW_MSB	= 			ROW_WIDTH+	COL_WIDTH-	1;
+localparam	ROW_LSB	= 						COL_WIDTH;
+localparam	COL_MSB	=						COL_WIDTH-	1;
+localparam	COL_LSB	= 0;
+
+// M2-M0
+localparam	BL1	= 3'b000;
+localparam	BL2	= 3'b001;
+localparam	BL4	= 3'b010;
+localparam	BL8	= 3'b011;
+localparam	BLP	= 3'b111;
+// M3
+localparam	SEQ	= 1'b0;
+localparam	INT	= 1'b1;
+// M6-M4
+localparam	CL1	= 3'b001;
+localparam	CL2	= 3'b010;
+localparam	CL3	= 3'b011;
+// M8-M7
+localparam	STD	= 2'b00;
+// M9
+localparam	PBL	= 1'b0;
+localparam	SLA	= 1'b1;
+
+localparam	BURST_LENGTH	= (BL == 1)? BL1 :
+								(BL == 2)? BL2 :
+								  (BL == 4)? BL4 :	
+								    (BL == 8)? BL8 : BL1;	
+localparam	BURST_TYPE		= SEQ;
+localparam	CAS_LATENCY		= CL;
+localparam	OP_MODE			= PBL;
+
+localparam	s_POWER_UP	= 4'b0000;
+localparam	s_INIT_CKE	= 4'b0001;
+localparam	s_INIT_PRE	= 4'b0010;
+localparam	s_INIT_REF0	= 4'b0011;
+localparam	s_INIT_REF1	= 4'b0100;
+localparam	s_INIT_MRS	= 4'b0101;
+localparam	s_IDLE		= 4'b0110;
+localparam	s_ACT		= 4'b0111;
+localparam	s_PRE		= 4'b1000;
+localparam	s_REF		= 4'b1001;
+reg		[3:0]r_sdr_state_1P;
+
+localparam	PRE_ALL		= 1'b1;
+localparam	PRE_SINGLE	= 1'b0;
+
+localparam	CYC_A	= 0;
+localparam	CYC_B	= 1;
+localparam	CYC_C	= 2;
+localparam	CYC_D	= 3;
+
+`ifdef RTL_SIM
+    localparam	RD_PIPE	= (DATA_RATE == 1 && DDIO_TYPE == "HARD") ? CL+tIORT+2 :	
+	                    (DATA_RATE == 1 && DDIO_TYPE == "SOFT") ? CL+tIORT+2 : CL+tIORT+3;
+`else
+    localparam	RD_PIPE	= (DATA_RATE == 1 && DDIO_TYPE == "HARD") ? CL+tIORT+2 :	
+	                    CL+tIORT+3;
+`endif	                    
+	                    
+(* syn_preserve = "TRUE" *)reg		[DLY_CNT_A_WIDTH-1:0]r_dly_cnt_a_1P;
+(* syn_preserve = "TRUE" *)reg		[DLY_CNT_B_WIDTH-1:0]r_dly_cnt_b_1P;
+(* syn_preserve = "TRUE" *)reg		[DLY_CNT_C_WIDTH-1:0]r_dly_cnt_c_1P;
+(* syn_preserve = "TRUE" *)reg		[DLY_CNT_D_WIDTH-1:0]r_dly_cnt_d_1P;
+reg		r_sdr_init_done_1P;
+reg		r_tRAS_done_1P;
+reg		[REF_LATENCY-1:0]r_tRAS_MAX_done_1P;
+reg		r_tRCD_done_1P;
+reg		r_tRTP_done_1P;
+reg		r_tRTW_done_1P;
+reg		r_tWR_done_1P;
+reg		r_tRC_done_1P;
+
+reg		r_wr_ack_1P;
+reg		[RD_PIPE:0]r_rd_ack_P;
+
+reg		[ROW_WIDTH:0]r_act_row_1P[0:3];
+reg		[BA_WIDTH+ROW_WIDTH-1:0]r_act_addr_1P;
+
+reg		r_tRAS_MAX_1P;
+reg		r_tRAS_MAX_2P;
+
+reg     r_pre_allbank;
+
+reg		r_oscclk_1P;
+reg		[REF_LATENCY-1:0]r_ref_req_1P;
+reg	    [6:0]	         r_sysclk_cnt_100_1P;
+reg		[DATA_RATE							-1:0]	r_sdr_cke_1P;
+reg		[DATA_RATE	*4						-1:0]	r_sdr_cmd_1P;
+reg		[DATA_RATE	*BA_WIDTH				-1:0]	r_sdr_ba_1P;
+reg		[DATA_RATE	*ROW_WIDTH				-1:0]	r_sdr_addr_1P;
+reg		[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	r_sdr_dq_1P;
+reg		[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	r_sdr_dqoe_1P;
+reg		[DATA_RATE	*DQ_GROUP				-1:0]	r_sdr_dm_1P;
+
+reg		[DATA_RATE	*4						-1:0]	r_sdr_cmd_2P;
+reg		[DATA_RATE	*BA_WIDTH				-1:0]	r_sdr_ba_2P;
+reg		[DATA_RATE	*ROW_WIDTH				-1:0]	r_sdr_addr_2P;
+reg		[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	r_sdr_dqoe_2P;
+
+reg		[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	r_sdr_dqin_1P;
+
+integer	c, b;
+
+wire	w_oscclk;
+wire	w_tRAS_MAX;
+wire	[BA_WIDTH-1:0]w_BA;
+wire	[ROW_WIDTH-1:0]w_ROW;
+wire	w_AFLAG;
+wire	[ROW_WIDTH-1:0]w_AROW;
+wire	w_pre_req;
+
+assign	w_BA	= i_addr[BA_MSB:BA_LSB];
+assign	w_ROW	= i_addr[ROW_MSB:ROW_LSB];
+assign	w_AFLAG	= r_act_row_1P[w_BA][ROW_WIDTH];
+assign	w_AROW	= r_act_row_1P[w_BA][ROW_WIDTH-1:0];
+
+initial
+begin
+	$display("RD_PIPE = %d\n", RD_PIPE);
+	$display("nPWRUP = %d\n", nPWRUP);
+	$display("nRAS = %d\n", nRAS);
+	$display("nRC = %d\n", nRC);
+	$display("nREF = %d\n", nREF);
+	$display("nRCD = %d\n", nRCD);
+	$display("nRFC = %d\n", nRFC);
+	$display("nRP = %d\n", nRP);
+end
+
+genvar k;
+generate
+
+    always@(posedge i_arst or posedge i_sysclk)
+    begin
+    	if (i_arst)
+    		r_sysclk_cnt_100_1P	<= {7{1'b0}};
+    	else
+    	begin
+    		if (r_sysclk_cnt_100_1P == 7'd98) begin
+    		    r_sysclk_cnt_100_1P	<= {7{1'b0}};
+    		end
+    		else if (r_dly_cnt_d_1P == nREF-1) begin
+    		    r_sysclk_cnt_100_1P	<= r_sysclk_cnt_100_1P+7'd1;
+    		end
+    		
+    	end
+    end
+	
+	if (CHECK_ACT_BA == 4)
+		assign	w_pre_req	= (~w_AFLAG) || (w_AROW != w_ROW);
+	else
+		assign	w_pre_req	= r_act_addr_1P != {w_BA, w_ROW};
+	
+	for (k=0; k<REF_LATENCY-1; k=k+1)
+	begin: REF_LATENCY_MAP
+		always@(posedge i_arst or posedge i_sysclk)
+		begin
+			if (i_arst)
+			begin
+				r_ref_req_1P[k+1]	<= 1'b0;
+			end
+			else if (r_sdr_state_1P == s_REF && r_dly_cnt_a_1P == nRFC)
+			begin
+				r_ref_req_1P[k+1]	<= 1'b0;
+			end
+			else
+			begin
+				r_ref_req_1P[k+1]	<= r_ref_req_1P[k];
+			end
+		end
+		
+		always@(posedge i_arst or posedge i_sysclk)
+		begin
+			if (i_arst)
+			begin
+				r_tRAS_MAX_done_1P[k+1]	<= 1'b0;
+			end
+			else
+			begin
+				r_tRAS_MAX_done_1P[k+1]	<= r_tRAS_MAX_done_1P[k];
+			end
+		end
+	end
+endgenerate
+
+always@(posedge i_arst or posedge i_sysclk)
+begin
+	if (i_arst)
+	begin
+		r_sdr_state_1P		<= s_POWER_UP;
+		
+		r_sdr_cke_1P		<= {DATA_RATE							{1'b0}};
+		r_sdr_cmd_1P		<= {DATA_RATE							{c_NOP}};
+		r_sdr_ba_1P			<= {DATA_RATE	*BA_WIDTH				{1'b0}};
+		r_sdr_addr_1P		<= {DATA_RATE	*ROW_WIDTH				{1'b0}};
+		r_sdr_dq_1P			<= {DATA_RATE	*DQ_GROUP	*DQ_WIDTH	{1'b0}};
+		r_sdr_dqoe_1P		<= {DATA_RATE	*DQ_GROUP	*DQ_WIDTH	{1'b0}};
+		r_sdr_dm_1P			<= {DATA_RATE	*DQ_GROUP				{1'b1}};
+		r_act_row_1P[0]		<= {ROW_WIDTH+1{1'b0}};
+		r_act_row_1P[1]		<= {ROW_WIDTH+1{1'b0}};
+		r_act_row_1P[2]		<= {ROW_WIDTH+1{1'b0}};
+		r_act_row_1P[3]		<= {ROW_WIDTH+1{1'b0}};
+		r_act_addr_1P		<= {BA_WIDTH+ROW_WIDTH{1'b0}};
+		
+		r_sdr_cmd_2P		<= {DATA_RATE							{c_NOP}};
+		r_sdr_ba_2P			<= {DATA_RATE	*BA_WIDTH				{1'b0}};
+		r_sdr_addr_2P		<= {DATA_RATE	*ROW_WIDTH				{1'b0}};
+		r_sdr_dqoe_2P		<= {DATA_RATE	*DQ_GROUP	*DQ_WIDTH	{1'b0}};
+		
+		r_dly_cnt_a_1P		<= {DLY_CNT_A_WIDTH{1'b0}};
+		r_dly_cnt_b_1P		<= {DLY_CNT_B_WIDTH{1'b0}};
+		r_dly_cnt_c_1P		<= {DLY_CNT_C_WIDTH{1'b0}};
+		r_dly_cnt_d_1P      <= {DLY_CNT_D_WIDTH{1'b0}};
+		r_sdr_init_done_1P	<= 1'b0;
+		r_wr_ack_1P			<= 1'b0;
+		r_rd_ack_P[0]		<= 1'b0;
+
+		r_oscclk_1P			<= 1'b0;
+		r_ref_req_1P[0]		<= 1'b0;
+		r_tRAS_done_1P		<= 1'b0;
+		r_tRAS_MAX_done_1P[0]	<= 1'b0;
+		r_tRCD_done_1P		<= 1'b0;
+		r_tRTP_done_1P		<= 1'b0;
+		r_tRTW_done_1P		<= 1'b0;
+		r_tWR_done_1P		<= 1'b0;
+		r_tRC_done_1P		<= 1'b0;
+		
+		r_sdr_dqin_1P		<= {DQ_GROUP*DQ_WIDTH{1'b0}};
+		r_pre_allbank       <= 1'b0;
+	end
+	else if (i_pll_locked)
+	begin
+		r_sdr_cmd_1P		<= {DATA_RATE							{c_NOP}};
+		r_sdr_ba_1P			<= {DATA_RATE	*BA_WIDTH				{1'b0}};
+		r_sdr_addr_1P		<= {DATA_RATE	*ROW_WIDTH				{1'b0}};
+		r_sdr_dq_1P			<= {DATA_RATE	*DQ_GROUP	*DQ_WIDTH	{1'b0}};
+		r_sdr_dqoe_1P		<= {DATA_RATE	*DQ_GROUP	*DQ_WIDTH	{1'b0}};
+		r_sdr_dm_1P			<= {DATA_RATE	*DQ_GROUP				{1'b0}};
+		r_sdr_cmd_2P		<= r_sdr_cmd_1P;
+		r_sdr_ba_2P			<= r_sdr_ba_1P;
+		r_sdr_addr_2P		<= r_sdr_addr_1P;
+		r_sdr_dqoe_2P		<= r_sdr_dqoe_1P;
+		
+		r_wr_ack_1P			<= 1'b0;
+		r_rd_ack_P[0]		<= 1'b0;
+		
+		r_sdr_dqin_1P		<= i_sdr_DATA;
+		
+		r_dly_cnt_a_1P		<= r_dly_cnt_a_1P+1'b1;
+		r_dly_cnt_b_1P		<= r_dly_cnt_b_1P+1'b1;
+		r_dly_cnt_c_1P		<= r_dly_cnt_c_1P+1'b1;
+		
+		if (r_dly_cnt_d_1P == nREF-1)
+		    r_dly_cnt_d_1P      <= {DLY_CNT_D_WIDTH{1'b0}};
+		else if (r_sdr_state_1P != s_POWER_UP)
+		    r_dly_cnt_d_1P      <= r_dly_cnt_d_1P+1'b1;
+
+		if (r_dly_cnt_b_1P == nRAS-1'b1)
+			r_tRAS_done_1P	<= 1'b1;
+
+		if (r_sysclk_cnt_100_1P == 7'd98)
+			r_ref_req_1P[0]	<= 1'b1; 
+			
+		if (r_dly_cnt_b_1P == nRCD-1)
+			r_tRCD_done_1P	<= 1'b1;
+		
+		if (r_dly_cnt_b_1P == nRTP-1)
+			r_tRTP_done_1P	<= 1'b1;
+		
+		if (r_dly_cnt_b_1P == nRTW-1)
+			r_tRTW_done_1P	<= 1'b1;
+		
+		if (r_dly_cnt_b_1P == tWR-1)
+			r_tWR_done_1P	<= 1'b1;
+		
+		if (r_dly_cnt_b_1P == nRC-1)
+			r_tRC_done_1P	<= 1'b1;
+			
+        if (r_dly_cnt_c_1P == nRAS_MAX && r_sdr_state_1P != s_POWER_UP) 
+            r_tRAS_MAX_done_1P[0]  <= 1'b1;
+		
+		case (r_sdr_state_1P)
+			s_POWER_UP:
+			begin
+				if (r_dly_cnt_c_1P == nPWRUP)  // count power up sequence
+				begin
+					r_sdr_state_1P	<= s_INIT_CKE;
+					
+					r_sdr_cke_1P	<= {DATA_RATE{1'b1}};
+					r_dly_cnt_c_1P	<= {DLY_CNT_C_WIDTH{1'b0}};
+				end
+			end
+			
+			s_INIT_CKE:
+			begin
+				r_sdr_state_1P			<= s_INIT_PRE;
+				
+				r_sdr_cmd_1P[CYC_A+:4]	<= c_PRE;
+				r_sdr_addr_1P[CYC_A+10]	<= PRE_ALL;
+				
+				r_dly_cnt_a_1P			<= {DLY_CNT_A_WIDTH{1'b0}};
+			end
+			
+			s_INIT_PRE:
+			begin
+				if (r_dly_cnt_a_1P == nRP)
+				begin
+					r_sdr_state_1P			<= s_INIT_REF0;
+					
+					r_sdr_cmd_1P[CYC_A+:4]	<= c_REF;
+					
+					r_dly_cnt_a_1P			<= {DLY_CNT_A_WIDTH{1'b0}};
+				end
+			end
+			
+			s_INIT_REF0:
+			begin
+				if (r_dly_cnt_a_1P == nRFC)
+				begin
+					r_sdr_state_1P			<= s_INIT_REF1;
+					
+					r_sdr_cmd_1P[CYC_A+:4]	<= c_REF;
+					
+					r_dly_cnt_a_1P			<= {DLY_CNT_A_WIDTH{1'b0}};
+				end
+			end
+			
+			s_INIT_REF1:
+			begin
+				if (r_dly_cnt_a_1P == nRFC)
+				begin
+					r_sdr_state_1P					<= s_INIT_MRS;
+					
+					r_sdr_cmd_1P[CYC_A+:4]			<= c_MRS;
+					r_sdr_addr_1P[CYC_A+:ROW_WIDTH]	<= {{ROW_WIDTH-10{1'b0}},
+														OP_MODE, CAS_LATENCY,
+														BURST_TYPE, BURST_LENGTH};
+					
+					r_dly_cnt_a_1P					<= {DLY_CNT_A_WIDTH{1'b0}};
+				end
+			end
+			
+			s_INIT_MRS:
+			begin
+				if (r_dly_cnt_a_1P == tMRD-1'b1)
+				begin
+					r_sdr_state_1P		<= s_IDLE;
+					r_sdr_dm_1P			<= {DATA_RATE*DQ_GROUP{1'b0}};
+					r_sdr_init_done_1P	<= 1'b1;
+					r_tRCD_done_1P		<= 1'b0;
+					r_tRTP_done_1P		<= 1'b0;
+					r_tWR_done_1P		<= 1'b0;
+					r_tRC_done_1P		<= 1'b0;
+				end
+			end
+			
+			s_IDLE:
+			begin
+				if (r_ref_req_1P[REF_LATENCY-1])
+				begin
+					if (CHECK_ACT_BA == 4 && (
+						r_act_row_1P[0][ROW_WIDTH] || r_act_row_1P[1][ROW_WIDTH] ||
+						r_act_row_1P[2][ROW_WIDTH] || r_act_row_1P[3][ROW_WIDTH ]))
+					begin
+						r_sdr_state_1P				<= s_PRE;
+						
+						r_sdr_cmd_1P[CYC_A+:4]		<= c_PRE;
+						r_sdr_addr_1P[CYC_A+10]		<= PRE_ALL;
+						r_act_row_1P[0][ROW_WIDTH]	<= 1'b0;
+						r_act_row_1P[1][ROW_WIDTH]	<= 1'b0;
+						r_act_row_1P[2][ROW_WIDTH]	<= 1'b0;
+						r_act_row_1P[3][ROW_WIDTH]	<= 1'b0;
+						
+						r_dly_cnt_a_1P				<= {DLY_CNT_A_WIDTH{1'b0}};
+					end
+					else
+					begin
+						r_sdr_state_1P			<= s_REF;
+						
+						r_sdr_cmd_1P[CYC_A+:4]	<= c_REF;
+						
+						r_dly_cnt_a_1P			<= {DLY_CNT_A_WIDTH{1'b0}};
+					end
+				end
+				else if (i_we || i_re)
+				begin
+					r_sdr_state_1P		<= s_ACT;
+					
+					r_sdr_cmd_1P[CYC_A+:4]			<= c_ACT;
+					r_sdr_ba_1P[CYC_A+:BA_WIDTH]	<= i_addr[BA_MSB:BA_LSB];
+					r_sdr_addr_1P[CYC_A+:ROW_WIDTH]	<= i_addr[ROW_MSB:ROW_LSB];
+					
+					if (CHECK_ACT_BA == 4)
+						r_act_row_1P[w_BA]	<= {1'b1, w_ROW};
+					r_act_addr_1P		<= {w_BA, w_ROW};
+
+					r_dly_cnt_b_1P		  <= {DLY_CNT_B_WIDTH{1'b0}};
+					r_dly_cnt_c_1P        <= {DLY_CNT_C_WIDTH{1'b0}};
+					r_tRAS_done_1P		  <= 1'b0;
+					r_tRCD_done_1P		  <= 1'b0;
+					r_tRC_done_1P		  <= 1'b0;
+					r_tRAS_MAX_done_1P[0] <= 1'b0;
+				end
+			end
+			
+			s_ACT:
+			begin
+				if (r_ref_req_1P[REF_LATENCY-1] || r_tRAS_MAX_done_1P[REF_LATENCY-1])
+				begin
+					if (r_tRAS_done_1P && r_tWR_done_1P && r_tRTP_done_1P)
+					begin
+						r_sdr_state_1P				<= s_PRE;
+						
+						r_sdr_cmd_1P[CYC_A+:4]		<= c_PRE;
+						r_sdr_addr_1P[CYC_A+10]		<= PRE_ALL;
+						r_sdr_ba_2P                 <= r_sdr_ba_2P;
+						r_sdr_addr_2P               <= r_sdr_addr_2P;  // do not assign r_sdr_addr_1P to r_sdr_addr_2P because r_sdr_addr_1P was zero in previous clock
+						r_pre_allbank               <= 1'b1;
+						if (CHECK_ACT_BA == 4)
+						begin
+							r_act_row_1P[0][ROW_WIDTH]	<= 1'b0;
+							r_act_row_1P[1][ROW_WIDTH]	<= 1'b0;
+							r_act_row_1P[2][ROW_WIDTH]	<= 1'b0;
+							r_act_row_1P[3][ROW_WIDTH]	<= 1'b0;
+						end
+						
+						r_dly_cnt_a_1P		<= {DLY_CNT_A_WIDTH{1'b0}};
+					end
+				end
+				else if (i_we || i_re)
+				begin
+					if (w_pre_req)
+					begin
+						if (r_tRC_done_1P && r_tRAS_done_1P &&
+							r_tWR_done_1P && r_tRTP_done_1P)
+						begin
+							r_sdr_state_1P					<= s_PRE;
+							
+							r_sdr_cmd_1P[CYC_A+:4]			<= c_PRE;
+							r_sdr_ba_1P[CYC_A+:BA_WIDTH]	<= i_addr[BA_MSB:BA_LSB];
+							r_sdr_addr_1P[CYC_A+10]			<= PRE_SINGLE;
+							if (CHECK_ACT_BA == 4)
+								r_act_row_1P[w_BA][ROW_WIDTH]	<= 1'b0;
+							
+							r_dly_cnt_a_1P					<= {DLY_CNT_A_WIDTH{1'b0}};
+						end
+					end
+					else if (r_tRCD_done_1P)
+					begin
+						if (i_we && r_tRTW_done_1P)
+						begin
+							if (DATA_RATE == 1)
+							begin
+								r_sdr_cmd_1P[CYC_A+:4]			<= c_WR;
+								r_sdr_ba_2P[CYC_A+:BA_WIDTH]	<= i_addr[BA_MSB:BA_LSB];
+								r_sdr_addr_2P[CYC_A+:COL_WIDTH]	<= i_addr[COL_MSB:COL_LSB];
+							end
+							else
+							begin
+								for (c=0; c<DATA_RATE; c=c+1)
+								begin
+									r_sdr_cmd_1P[c*4+:4]				<= c_WR;
+									r_sdr_ba_2P[c*BA_WIDTH+:BA_WIDTH]	<= i_addr[BA_MSB:BA_LSB];
+									r_sdr_addr_2P[c*ROW_WIDTH+log2(DATA_RATE)+:COL_WIDTH-log2(DATA_RATE)]	<= i_addr[COL_MSB:COL_LSB+log2(DATA_RATE)];
+									for (b=0; b<log2(DATA_RATE); b=b+1)
+									begin
+										r_sdr_addr_2P[c*ROW_WIDTH+b]	<= (c & 32'hFFFFFFFF) >> b;
+									end
+								end
+							end
+							
+							r_sdr_dq_1P		<= i_din;
+							r_sdr_dm_1P     <= i_dm;
+							r_sdr_dqoe_1P	<= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b1}};
+							
+							r_dly_cnt_b_1P	<= {DLY_CNT_B_WIDTH{1'b0}};
+							r_tWR_done_1P	<= 1'b0;
+							
+							r_wr_ack_1P		<= ~r_ref_req_1P[0];
+							
+							if (REF_LATENCY > 2) begin
+							    if (r_ref_req_1P[1] || r_tRAS_MAX_done_1P[1] || (i_last & r_wr_ack_1P))   //
+							    begin
+							    		r_sdr_cmd_1P			<= {DATA_RATE{c_NOP}};
+							    		r_sdr_dqoe_1P			<= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}};
+							    		r_wr_ack_1P				<= 1'b0;
+							    end
+							end
+							else begin
+							    if (r_ref_req_1P[REF_LATENCY-2] || r_tRAS_MAX_done_1P[REF_LATENCY-2] || (i_last & r_wr_ack_1P))
+							    begin
+							    		r_sdr_cmd_1P			<= {DATA_RATE{c_NOP}};
+							    		r_sdr_dqoe_1P			<= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}};
+							    		r_wr_ack_1P				<= 1'b0;
+							    end
+							end
+						
+						end
+						else if (~i_we && i_re)
+						begin
+							if (DATA_RATE == 1)
+							begin
+								r_sdr_cmd_1P	<= c_RD;
+								r_sdr_ba_2P		<= i_addr[BA_MSB:BA_LSB];
+								r_sdr_addr_2P	<= i_addr[COL_MSB:COL_LSB];
+							end
+							else
+							begin
+								for (c=0; c<DATA_RATE; c=c+1)
+								begin
+									r_sdr_cmd_1P[c*4+:4]				<= c_RD;
+									r_sdr_ba_2P[c*BA_WIDTH+:BA_WIDTH]	<= i_addr[BA_MSB:BA_LSB];
+									r_sdr_addr_2P[c*ROW_WIDTH+log2(DATA_RATE)+:COL_WIDTH-log2(DATA_RATE)]	<= i_addr[COL_MSB:COL_LSB+log2(DATA_RATE)];
+									for (b=0; b<log2(DATA_RATE); b=b+1)
+									begin
+										r_sdr_addr_2P[c*ROW_WIDTH+b]	<= (c & 32'hFFFFFFFF) >> b;
+									end
+								end
+							end
+							
+							r_dly_cnt_b_1P	<= {DLY_CNT_B_WIDTH{1'b0}};
+							r_tRTW_done_1P	<= 1'b0;
+							r_tRC_done_1P	<= 1'b0;
+							
+							r_rd_ack_P[0]	<= ~r_ref_req_1P[0];
+							
+							if (REF_LATENCY > 2) begin
+							    if (r_ref_req_1P[1] || r_tRAS_MAX_done_1P[1] || (i_last & r_rd_ack_P[0]))
+							    begin
+							    	if (r_rd_ack_P[0])
+							    	begin
+							    		r_sdr_cmd_1P			<= {DATA_RATE{c_NOP}};
+							    		r_sdr_dqoe_1P			<= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}};
+							    		r_rd_ack_P[0]			<= 1'b0;
+							    	end
+							    end
+							end
+							else begin
+							    if (r_ref_req_1P[REF_LATENCY-2] || r_tRAS_MAX_done_1P[REF_LATENCY-2] || (i_last & r_rd_ack_P[0]))
+							    begin
+							    	if (r_rd_ack_P[0])
+							    	begin
+							    		r_sdr_cmd_1P			<= {DATA_RATE{c_NOP}};
+							    		r_sdr_dqoe_1P			<= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}};
+							    		r_rd_ack_P[0]			<= 1'b0;
+							    	end
+							    end
+							end
+						end
+					end
+				end
+			end
+			
+			s_PRE:
+			begin
+				if (r_dly_cnt_a_1P == nRP-1'b1)
+				begin
+					if (r_ref_req_1P[REF_LATENCY-1])
+					begin
+						if (r_pre_allbank)  // check if the previous PRE is ALL_BANK or SINGLE_BANK
+						begin                   
+						    r_sdr_state_1P			<= s_REF;
+						    r_sdr_cmd_1P[CYC_A+:4]	<= c_REF;
+						    r_pre_allbank           <= 1'b0;
+						    r_dly_cnt_a_1P			<= {DLY_CNT_A_WIDTH{1'b0}};
+						end
+						else 
+						begin // if the previous PRE is SINGLE_BANK, issue PRE to ALL_BANK before trigger AUTO-refresh
+						    r_sdr_state_1P			<= s_PRE;
+						    r_sdr_cmd_1P[CYC_A+:4]	<= c_PRE;
+						    r_sdr_addr_1P[CYC_A+10] <= PRE_ALL;
+						    r_pre_allbank           <= 1'b1;
+						    if (CHECK_ACT_BA == 4)
+						    begin
+						    	r_act_row_1P[0][ROW_WIDTH]	<= 1'b0;
+						    	r_act_row_1P[1][ROW_WIDTH]	<= 1'b0;
+						    	r_act_row_1P[2][ROW_WIDTH]	<= 1'b0;
+						    	r_act_row_1P[3][ROW_WIDTH]	<= 1'b0;
+						    end
+						    r_dly_cnt_a_1P			<= {DLY_CNT_A_WIDTH{1'b0}};
+						end
+					end
+					else
+					begin
+						r_sdr_state_1P	<= s_IDLE;
+					end
+				end
+			end
+			
+			s_REF:
+			begin
+				if (r_dly_cnt_a_1P == nRFC)
+				begin
+					r_sdr_state_1P	<= s_IDLE;
+					r_ref_req_1P[0]	<= 1'b0;
+		            r_dly_cnt_d_1P  <= {DLY_CNT_D_WIDTH{1'b0}};
+				end
+			end
+		endcase
+	end
+end
+
+assign	o_sdr_state		= r_sdr_state_1P;
+assign	o_sdr_init_done	= r_sdr_init_done_1P;
+assign	o_wr_ack		= r_wr_ack_1P;
+genvar i;
+generate
+	for (i=1; i<=RD_PIPE; i=i+1)
+	begin: readback
+		always@(posedge i_arst or posedge i_sysclk)
+		begin
+			if (i_arst)
+				r_rd_ack_P[i]	<= 1'b0;
+			else
+				r_rd_ack_P[i]	<= r_rd_ack_P[i-1];
+		end
+	end
+endgenerate
+assign	o_rd_ack		= r_rd_ack_P[0];
+assign	o_ref_req		= r_ref_req_1P[0];
+assign	o_rd_valid		= r_rd_ack_P[RD_PIPE];
+assign	o_dout			= r_sdr_dqin_1P;
+
+assign	o_sdr_CKE		= r_sdr_cke_1P;
+genvar j;
+generate
+	for (j=0; j<DATA_RATE; j=j+1)
+	begin: cycle_mapping
+		assign	o_sdr_n_CS[j]	= r_sdr_cmd_2P[j*4+3];
+		assign	o_sdr_n_RAS[j]	= r_sdr_cmd_2P[j*4+2];
+		assign	o_sdr_n_CAS[j]	= r_sdr_cmd_2P[j*4+1];
+		assign	o_sdr_n_WE[j]	= r_sdr_cmd_2P[j*4+0];
+		
+		assign	o_dbg_n_CS[j]	= r_sdr_cmd_2P[j*4+3];
+		assign	o_dbg_n_RAS[j]	= r_sdr_cmd_2P[j*4+2];
+		assign	o_dbg_n_CAS[j]	= r_sdr_cmd_2P[j*4+1];
+		assign	o_dbg_n_WE[j]	= r_sdr_cmd_2P[j*4+0];
+	end
+endgenerate
+assign	o_sdr_BA		= r_sdr_ba_2P;
+assign	o_sdr_ADDR		= r_sdr_addr_2P;
+assign	o_sdr_DATA		= r_sdr_dq_1P;
+assign	o_sdr_DQM		= r_sdr_dm_1P;
+assign	o_sdr_DATA_oe	= r_sdr_dqoe_2P;
+
+assign	o_dbg_dly_cnt_b	= (DLY_CNT_B_WIDTH == 4) ? {2'b00, r_dly_cnt_b_1P} : r_dly_cnt_b_1P;
+assign	o_dbg_tRCD_done	= r_tRCD_done_1P;
+assign	o_dbg_tRTW_done	= r_tRTW_done_1P;
+assign	o_dbg_ref_req	= r_ref_req_1P[REF_LATENCY-2];
+assign	o_dbg_wr_ack	= r_wr_ack_1P;
+assign	o_dbg_rd_ack	= r_rd_ack_P[0];
+
+assign	o_dbg_BA		= r_sdr_ba_2P;
+assign	o_dbg_ADDR		= r_sdr_addr_2P;
+
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   `IP_MODULE_NAME(sdram_io_block).v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      sdram controller I/O alignment
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module `IP_MODULE_NAME(sdram_io_block)
+#(
+	parameter	DATA_RATE		= 2,		// Do not over write
+	parameter	BA_WIDTH		= 2,
+	parameter	ROW_WIDTH		= 13,
+	parameter	COL_WIDTH		= 10,
+	parameter	DQ_WIDTH		= 8,	// x4, x8
+	parameter	DQ_GROUP		= 2
+)
+(
+	input	i_arst,
+	input	i_sysclk,
+	input	i_sdrclk,
+	input	i_tACclk,
+	input	i_pll_locked,
+	
+	input	[DATA_RATE							-1:0]	i_sdr_CKE_core,
+	input	[DATA_RATE							-1:0]	i_sdr_n_CS_core,
+	input	[DATA_RATE							-1:0]	i_sdr_n_RAS_core,
+	input	[DATA_RATE							-1:0]	i_sdr_n_CAS_core,
+	input	[DATA_RATE							-1:0]	i_sdr_n_WE_core,
+	input	[DATA_RATE	*BA_WIDTH				-1:0]	i_sdr_BA_core,
+	input	[DATA_RATE	*ROW_WIDTH				-1:0]	i_sdr_ADDR_core,
+	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA_core,
+	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA_oe_core,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_core,
+	input	[DATA_RATE	*DQ_GROUP				-1:0]	i_sdr_DQM_core,
+	
+	output	[DATA_RATE							-1:0]	o_sdr_CKE_pad,
+	output	[DATA_RATE							-1:0]	o_sdr_n_CS_pad,
+	output	[DATA_RATE							-1:0]	o_sdr_n_RAS_pad,
+	output	[DATA_RATE							-1:0]	o_sdr_n_CAS_pad,
+	output	[DATA_RATE							-1:0]	o_sdr_n_WE_pad,
+	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_sdr_BA_pad,
+	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_sdr_ADDR_pad,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_pad,
+	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_oe_pad,
+	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA_pad,
+	output	[DATA_RATE	*DQ_GROUP				-1:0]	o_sdr_DQM_pad
+);
+
+localparam	BA_MSB	= BA_WIDTH+	ROW_WIDTH+	COL_WIDTH-	1;
+localparam	BA_LSB	= 			ROW_WIDTH+	COL_WIDTH;
+localparam	ROW_MSB	= 			ROW_WIDTH+	COL_WIDTH-	1;
+localparam	ROW_LSB	= 						COL_WIDTH;
+localparam	COL_MSB	=						COL_WIDTH-	1;
+localparam	COL_LSB	= 0;
+
+localparam	CYC_A	= 0;
+localparam	CYC_B	= 1;
+localparam	CYC_C	= 2;
+localparam	CYC_D	= 3;
+
+wire	[DATA_RATE*DQ_GROUP*DQ_WIDTH-1:0]w_sdr_DATA_core;
+reg		[DQ_GROUP*DQ_WIDTH-1:0]r_sdr_DATA_core_1P;
+reg		r_pll_locked_1P;
+
+genvar rate;
+
+initial
+begin
+	$display("Data Rate = %d\n", DATA_RATE);
+`ifdef RTL_SIM
+	$display("RTL_SIM\n");
+`endif
+end
+
+always@(posedge i_arst or posedge i_sysclk)
+begin
+	if (i_arst)
+	begin
+		r_pll_locked_1P	<= 1'b0;
+	end
+	else
+	begin
+		r_pll_locked_1P	<= i_pll_locked;
+	end
+end
+
+    `IP_MODULE_NAME(sync_ddio_group_out)
+    #(
+    	.DW(1),
+    	.INIT(1'b0),
+    	.SYNC("RISING")
+    )
+    inst_CKE
+    (
+    	.arst(i_arst),
+    	.d0(i_sdr_CKE_core[CYC_A]),
+    	.d1(i_sdr_CKE_core[CYC_B]),
+    	.c_x1(i_sysclk),
+    	.c_x2(i_sdrclk),
+    	.lock(r_pll_locked_1P),
+    	.c(),
+    	.q(o_sdr_CKE_pad[CYC_A])
+    );
+    
+    `IP_MODULE_NAME(sync_ddio_group_out)
+    #(
+    	.DW(1),
+    	.INIT(1'b0),
+    	.SYNC("RISING")
+    )
+    inst_CS
+    (
+    	.arst(i_arst),
+    	.d0(i_sdr_n_CS_core[CYC_A]),
+    	.d1(i_sdr_n_CS_core[CYC_B]),
+    	.c_x1(i_sysclk),
+    	.c_x2(i_sdrclk),
+    	.lock(r_pll_locked_1P),
+    	.c(),
+    	.q(o_sdr_n_CS_pad[CYC_A])
+    );
+    
+    `IP_MODULE_NAME(sync_ddio_group_out)
+    #(
+    	.DW(1),
+    	.INIT(1'b0),
+    	.SYNC("RISING")
+    )
+    inst_RAS
+    (
+    	.arst(i_arst),
+    	.d0(i_sdr_n_RAS_core[CYC_A]),
+    	.d1(i_sdr_n_RAS_core[CYC_B]),
+    	.c_x1(i_sysclk),
+    	.c_x2(i_sdrclk),
+    	.lock(r_pll_locked_1P),
+    	.c(),
+    	.q(o_sdr_n_RAS_pad[CYC_A])
+    );
+    
+    `IP_MODULE_NAME(sync_ddio_group_out)
+    #(
+    	.DW(1),
+    	.INIT(1'b0),
+    	.SYNC("RISING")
+    )
+    inst_CAS
+    (
+    	.arst(i_arst),
+    	.d0(i_sdr_n_CAS_core[CYC_A]),
+    	.d1(i_sdr_n_CAS_core[CYC_B]),
+    	.c_x1(i_sysclk),
+    	.c_x2(i_sdrclk),
+    	.lock(r_pll_locked_1P),
+    	.c(),
+    	.q(o_sdr_n_CAS_pad[CYC_A])
+    );
+    
+    `IP_MODULE_NAME(sync_ddio_group_out)
+    #(
+    	.DW(1),
+    	.INIT(1'b0),
+    	.SYNC("RISING")
+    )
+    inst_WE
+    (
+    	.arst(i_arst),
+    	.d0(i_sdr_n_WE_core[CYC_A]),
+    	.d1(i_sdr_n_WE_core[CYC_B]),
+    	.c_x1(i_sysclk),
+    	.c_x2(i_sdrclk),
+    	.lock(r_pll_locked_1P),
+    	.c(),
+    	.q(o_sdr_n_WE_pad[CYC_A])
+    );
+    
+    `IP_MODULE_NAME(sync_ddio_group_out)
+    #(
+    	.DW(BA_WIDTH),
+    	.INIT(1'b0),
+    	.SYNC("RISING")
+    )
+    inst_BA
+    (
+    	.arst(i_arst),
+    	.d0(i_sdr_BA_core[CYC_A*BA_WIDTH+:BA_WIDTH]),
+    	.d1(i_sdr_BA_core[CYC_B*BA_WIDTH+:BA_WIDTH]),
+    	.c_x1(i_sysclk),
+    	.c_x2(i_sdrclk),
+    	.lock(r_pll_locked_1P),
+    	.c(),
+    	.q(o_sdr_BA_pad[BA_WIDTH-1:0])
+    );
+    
+    `IP_MODULE_NAME(sync_ddio_group_out)
+    #(
+    	.DW(ROW_WIDTH),
+    	.INIT(1'b0),
+    	.SYNC("RISING")
+    )
+    inst_ADDR
+    (
+    	.arst(i_arst),
+    	.d0(i_sdr_ADDR_core[CYC_A*ROW_WIDTH+:ROW_WIDTH]), 
+    	.d1(i_sdr_ADDR_core[CYC_B*ROW_WIDTH+:ROW_WIDTH]),
+    	.c_x1(i_sysclk),
+    	.c_x2(i_sdrclk),
+    	.lock(r_pll_locked_1P),
+    	.c(),
+    	.q(o_sdr_ADDR_pad[ROW_WIDTH-1:0])
+    );
+    
+    `IP_MODULE_NAME(sync_ddio_group_out)
+    #(
+    	.DW(DQ_GROUP*DQ_WIDTH),
+    	.INIT(1'b0),
+    	.SYNC("RISING")
+    )
+    inst_DQ_OUT
+    (
+    	.arst(i_arst),
+    	.d0(i_sdr_DATA_core[CYC_A*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]),   
+    	.d1(i_sdr_DATA_core[CYC_B*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]),
+    	.c_x1(i_sysclk),
+    	.c_x2(i_sdrclk),
+    	.lock(r_pll_locked_1P),
+    	.c(),
+    	.q(o_sdr_DATA_pad[DQ_GROUP*DQ_WIDTH-1:0])
+    );
+    
+    `IP_MODULE_NAME(sync_ddio_group_out)
+    #(
+    	.DW(DQ_GROUP*DQ_WIDTH),
+    	.INIT(1'b0),
+    	.SYNC("RISING")
+    )
+    inst_DQ_oe
+    (
+    	.arst(i_arst),
+    	.d0(i_sdr_DATA_oe_core[CYC_A*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]),
+    	.d1(i_sdr_DATA_oe_core[CYC_B*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]),
+    	.c_x1(i_sysclk),
+    	.c_x2(i_sdrclk),
+    	.lock(r_pll_locked_1P),
+    	.c(),
+    	.q(o_sdr_DATA_oe_pad[DQ_GROUP*DQ_WIDTH-1:0])
+    );
+    
+    `IP_MODULE_NAME(sync_ddio_group_in)
+    #(
+    	.DW		(DQ_GROUP*DQ_WIDTH),
+    	.SYNC	("RISING")   
+    )
+    inst_DQ_IN
+    (
+    	.arst	(i_arst),
+    	.c_x1	(i_sysclk),
+    	.c_x2	(i_tACclk),
+    	.d		(i_sdr_DATA_pad[DQ_GROUP*DQ_WIDTH-1:0]),
+`ifdef RTL_SIM
+        .q0		(o_sdr_DATA_core[CYC_A*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]),	// simulation
+        .q1		(o_sdr_DATA_core[CYC_B*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH])	// simulation
+`else
+        .q0		(w_sdr_DATA_core[CYC_A*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]),
+        .q1		(w_sdr_DATA_core[CYC_B*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH])
+`endif
+    );
+    
+    `IP_MODULE_NAME(sync_ddio_group_out)
+    #(
+    	.DW(DQ_GROUP),
+    	.INIT(1'b0),
+    	.SYNC("RISING")
+    )
+    inst_DQM
+    (
+    	.arst(i_arst),
+    	.d0(i_sdr_DQM_core[CYC_A*DQ_GROUP+:DQ_GROUP]),
+    	.d1(i_sdr_DQM_core[CYC_B*DQ_GROUP+:DQ_GROUP]),
+    	.c_x1(i_sysclk),
+    	.c_x2(i_sdrclk),
+    	.lock(r_pll_locked_1P),
+    	.c(),
+    	.q(o_sdr_DQM_pad[DQ_GROUP-1:0])
+    );
+			
+`ifndef RTL_SIM
+    // on board
+    always@(posedge i_arst or posedge i_sysclk)
+    begin
+    	if (i_arst)
+    		r_sdr_DATA_core_1P	<= {DQ_GROUP*DQ_WIDTH{1'b0}};
+    	else
+    		r_sdr_DATA_core_1P	<= w_sdr_DATA_core[CYC_B*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH];
+    end
+    assign	o_sdr_DATA_core	= {	w_sdr_DATA_core[CYC_A*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH],
+    							r_sdr_DATA_core_1P};
+`endif
+	generate
+	    for (rate=1; rate<DATA_RATE; rate=rate+1)
+	    begin: cycle_mapping
+	    	assign	o_sdr_CKE_pad[rate]		= 1'b0;
+	    	assign	o_sdr_n_CS_pad[rate]	= 1'b0;
+	    	assign	o_sdr_n_RAS_pad[rate]	= 1'b0;
+	    	assign	o_sdr_n_CAS_pad[rate]	= 1'b0;
+	    	assign	o_sdr_n_WE_pad[rate]	= 1'b0;
+	    	assign	o_sdr_BA_pad[rate*BA_WIDTH+:BA_WIDTH]		= {BA_WIDTH{1'b0}};
+	    	assign	o_sdr_ADDR_pad[rate*ROW_WIDTH+:ROW_WIDTH]	= {ROW_WIDTH{1'b0}};
+	    	assign	o_sdr_DATA_pad[rate*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]		= {DQ_GROUP*DQ_WIDTH{1'b0}};
+	    	assign	o_sdr_DATA_oe_pad[rate*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]	= {DQ_GROUP*DQ_WIDTH{1'b0}};
+	    	assign	o_sdr_DQM_pad[rate*DQ_GROUP+:DQ_GROUP]		= {DQ_GROUP{1'b0}};
+	    end
+    endgenerate
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////
+
+	`define CLK_200    	
+
+	`define SYS_CLK_100     	
+
+	`define tPWRUP     	      200000
+
+	`define tRAS       	          44
+
+	`define tRAS_MAX   	      120000
+
+	`define tRC        	          66
+
+	`define tRCD       	          20
+
+	`define tREF       	    64000000
+
+	`define tRFC       	          66
+
+	`define tRP        	          20
+
+	`define tWR        	           2
+
+	`define tMRD       	           2
+
+	`define ba_width   	           2
+
+	`define row_width  	          13
+
+	`define col_width  	          10
+
+	`define dq_width   	           8
+
+	`define dq_group   	           2
+
+	`define fsys_mhz   	         100
+
+	`define fck_mhz    	         200
+
+	`define cl         	           3
+
+	`define bl         	           1
+
+	`define ddio_type  	 "SOFT"
+	
+	`define tIORT                  2
+	
+	`define SDRAM_MODE		"AXI4" //"Native"
+
+
+
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      simple dual port ram macro
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+module `IP_MODULE_NAME(sdram_simple_dual_port_ram)
+#(
+	parameter DATA_WIDTH	= 8,
+	parameter ADDR_WIDTH	= 9,
+	parameter OUTPUT_REG	= "TRUE",
+	parameter RAM_INIT_FILE	= ""
+)
+(
+	input [(DATA_WIDTH-1):0] wdata,
+	input [(ADDR_WIDTH-1):0] waddr, raddr,
+	input we, wclk, re, rclk,
+	output [(DATA_WIDTH-1):0] rdata
+);
+
+	localparam MEMORY_DEPTH = 2**ADDR_WIDTH;
+	localparam MAX_DATA = (1<<ADDR_WIDTH)-1;
+	
+	reg [DATA_WIDTH-1:0] ram[MEMORY_DEPTH-1:0];
+	reg [DATA_WIDTH-1:0] r_rdata_1P;
+	reg [DATA_WIDTH-1:0] r_rdata_2P;
+	
+	reg [DATA_WIDTH-1:0] i;
+	initial
+	begin
+	// By default the Efinix memory will initialize to 0
+		if (RAM_INIT_FILE != "")
+		begin
+			$readmemh(RAM_INIT_FILE, ram);
+		end
+		else
+		begin
+			for (i=0;i<=MEMORY_DEPTH-1;i=i+1)
+                ram[i] = i[DATA_WIDTH-1:0];
+		end
+	end
+	
+	always @ (posedge wclk)
+		if (we)
+		ram[waddr] <= wdata;
+	
+	always @ (posedge rclk)
+	begin
+		if (re)
+			r_rdata_1P <= ram[raddr];
+		r_rdata_2P <= r_rdata_1P;
+	end
+	
+	generate
+		if (OUTPUT_REG == "TRUE")
+			assign	rdata = r_rdata_2P;
+		else
+			assign	rdata = r_rdata_1P;
+	endgenerate
+
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   `IP_MODULE_NAME(sync_ddio_group_in).v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      soft DDIO input
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module `IP_MODULE_NAME(sync_ddio_group_in)
+#(
+	parameter	DW		= 1,
+	parameter	SYNC	= "RISING"
+)
+(
+	input	arst,
+	input	c_x1,
+	input	c_x2,
+	input	[DW-1:0]d,
+	output	[DW-1:0]q0,
+	output	[DW-1:0]q1
+);
+
+reg		[DW-1:0]r_d_x2_1P;
+reg		[DW-1:0]r_d_x2_2P;
+
+reg		[DW-1:0]r_d0_x1_2P;
+reg		[DW-1:0]r_d1_x1_2P;
+
+always@(posedge arst or posedge c_x2)
+begin
+	if (arst)
+	begin
+		r_d_x2_1P	<= {DW{1'b0}};
+		r_d_x2_2P	<= {DW{1'b0}};
+	end
+	else
+	begin
+		r_d_x2_1P	<= d;
+		r_d_x2_2P	<= r_d_x2_1P;
+	end
+end
+
+    always@(posedge arst or posedge c_x1)
+    begin
+    	if (arst)
+    	begin
+    		r_d0_x1_2P	<= {DW{1'b0}};
+    		r_d1_x1_2P	<= {DW{1'b0}};
+    	end
+    	else
+    	begin
+    		if (SYNC == "FALLING")
+    		begin
+    			r_d0_x1_2P	<= r_d_x2_1P;
+    			r_d1_x1_2P	<= r_d_x2_2P;
+    		end
+    		else
+    		begin
+    			r_d0_x1_2P	<= r_d_x2_2P;
+    			r_d1_x1_2P	<= r_d_x2_1P;
+    		end
+    	end
+    end
+
+assign	q0	= r_d0_x1_2P;
+assign	q1	= r_d1_x1_2P;
+
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   `IP_MODULE_NAME(sync_ddio_group_out).v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      soft DDIO output
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module `IP_MODULE_NAME(sync_ddio_group_out)
+#(
+	parameter	DW		= 1,
+	parameter	INIT	= 1'b0,
+	parameter	SYNC	= "RISING"
+)
+(
+	input	arst,
+	input	[DW-1:0]d0,
+	input	[DW-1:0]d1,
+	input	c_x1,
+	input	c_x2,
+	input	lock,
+	output	c,
+	output	[DW-1:0]q
+);
+
+reg		[DW-1:0]r_d0_x1_1P;
+reg		[DW-1:0]r_d1_x1_1P;
+
+reg		r_c_x2_1P;
+reg		r_s_x2_1P;
+reg		[DW-1:0]r_d_x2_2P;
+
+wire	w_c_rst;
+
+generate
+	if (SYNC == "FALLING")
+		assign	w_c_rst	= 1'b1;
+	else
+		assign	w_c_rst	= 1'b0;
+endgenerate
+
+always@(posedge arst or posedge c_x1)
+begin
+	if (arst)
+	begin
+		r_d0_x1_1P	<= {DW{INIT}};
+		r_d1_x1_1P	<= {DW{INIT}};
+	end
+	else if (lock)
+	begin
+		r_d0_x1_1P	<= d0;
+		r_d1_x1_1P	<= d1;
+	end
+end
+
+always@(posedge arst or posedge c_x2)
+begin
+	if (arst)
+	begin
+		r_c_x2_1P	<= w_c_rst;
+		r_s_x2_1P	<= 1'b0;
+		r_d_x2_2P	<= {DW{INIT}};
+	end
+	else if (lock)
+	begin
+		r_c_x2_1P	<= ~r_c_x2_1P;
+		r_s_x2_1P	<= ~r_s_x2_1P;
+		if (r_s_x2_1P)
+			r_d_x2_2P	<= r_d1_x1_1P;
+		else
+			r_d_x2_2P	<= r_d0_x1_1P;
+	end
+end
+
+assign	c	= r_c_x2_1P;
+assign	q	= r_d_x2_2P;
+
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////
+`undef IP_UUID
+`undef IP_NAME_CONCAT
+`undef IP_MODULE_NAME
diff --git a/hw/super6502_fpga/ip/sdram_controller/sdram_controller_define.vh b/hw/super6502_fpga/ip/sdram_controller/sdram_controller_define.vh
new file mode 100644
index 0000000..2f11d84
--- /dev/null
+++ b/hw/super6502_fpga/ip/sdram_controller/sdram_controller_define.vh
@@ -0,0 +1,80 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.1.150
+// IP Version: 5.0
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+localparam fSYS_MHz = 100;
+localparam fCK_MHz = 200;
+localparam tIORT_u = 2;
+localparam CL = 3;
+localparam BL = 1;
+localparam DDIO_TYPE = "SOFT";
+localparam DQ_WIDTH = 8;
+localparam DQ_GROUP = 2;
+localparam BA_WIDTH = 2;
+localparam ROW_WIDTH = 13;
+localparam COL_WIDTH = 9;
+localparam tPWRUP = 200000;
+localparam tRAS = 44;
+localparam tRAS_MAX = 120000;
+localparam tRC = 66;
+localparam tRCD = 20;
+localparam tREF = 64000000;
+localparam tRFC = 66;
+localparam tRP = 20;
+localparam tWR = 2;
+localparam tMRD = 2;
+localparam SDRAM_MODE = "AXI4";
+localparam DATA_RATE = 2;
+localparam AXI_AWADDR_WIDTH = 24;
+localparam AXI_WDATA_WIDTH = 32;
+localparam AXI_ARADDR_WIDTH = 24;
+localparam AXI_RDATA_WIDTH = 32;
+localparam AXI_AWID_WIDTH = 4;
+localparam AXI_AWUSER_WIDTH = 2;
+localparam AXI_WUSER_WIDTH = 2;
+localparam AXI_BID_WIDTH = 4;
+localparam AXI_BUSER_WIDTH = 2;
+localparam AXI_ARID_WIDTH = 4;
+localparam AXI_ARUSER_WIDTH = 3;
+localparam AXI_RUSER_WIDTH = 3;
diff --git a/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.v b/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.v
new file mode 100644
index 0000000..eb02b53
--- /dev/null
+++ b/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.v
@@ -0,0 +1,127 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+sdram_controller u_sdram_controller(
+.i_aresetn ( i_aresetn ),
+.i_AXI4_AWADDR ( i_AXI4_AWADDR ),
+.i_sysclk ( i_sysclk ),
+.i_sdrclk ( i_sdrclk ),
+.i_tACclk ( i_tACclk ),
+.i_pll_locked ( i_pll_locked ),
+.o_dbg_ref_req ( o_dbg_ref_req ),
+.o_dbg_wr_ack ( o_dbg_wr_ack ),
+.o_dbg_rd_ack ( o_dbg_rd_ack ),
+.o_dbg_n_CS ( o_dbg_n_CS ),
+.o_dbg_n_RAS ( o_dbg_n_RAS ),
+.o_dbg_n_CAS ( o_dbg_n_CAS ),
+.o_dbg_n_WE ( o_dbg_n_WE ),
+.o_dbg_BA ( o_dbg_BA ),
+.o_dbg_ADDR ( o_dbg_ADDR ),
+.o_dbg_DATA_out ( o_dbg_DATA_out ),
+.o_dbg_DATA_in ( o_dbg_DATA_in ),
+.o_pll_reset ( o_pll_reset ),
+.o_AXI4_AWREADY ( o_AXI4_AWREADY ),
+.i_AXI4_AWVALID ( i_AXI4_AWVALID ),
+.o_AXI4_WREADY ( o_AXI4_WREADY ),
+.i_AXI4_WDATA ( i_AXI4_WDATA ),
+.i_AXI4_WSTRB ( i_AXI4_WSTRB ),
+.i_AXI4_WLAST ( i_AXI4_WLAST ),
+.i_AXI4_WVALID ( i_AXI4_WVALID ),
+.o_AXI4_BVALID ( o_AXI4_BVALID ),
+.i_AXI4_BREADY ( i_AXI4_BREADY ),
+.o_AXI4_ARREADY ( o_AXI4_ARREADY ),
+.i_AXI4_ARADDR ( i_AXI4_ARADDR ),
+.i_AXI4_RREADY ( i_AXI4_RREADY ),
+.o_AXI4_RDATA ( o_AXI4_RDATA ),
+.o_AXI4_RLAST ( o_AXI4_RLAST ),
+.o_AXI4_RVALID ( o_AXI4_RVALID ),
+.i_AXI4_AWID ( i_AXI4_AWID ),
+.i_AXI4_AWSIZE ( i_AXI4_AWSIZE ),
+.i_AXI4_ARVALID ( i_AXI4_ARVALID ),
+.i_AXI4_ARID ( i_AXI4_ARID ),
+.i_AXI4_ARLEN ( i_AXI4_ARLEN ),
+.i_AXI4_ARSIZE ( i_AXI4_ARSIZE ),
+.i_AXI4_ARBURST ( i_AXI4_ARBURST ),
+.i_AXI4_AWLEN ( i_AXI4_AWLEN ),
+.o_AXI4_RID ( o_AXI4_RID ),
+.o_dbg_we ( o_dbg_we ),
+.o_dbg_last ( o_dbg_last ),
+.o_dbg_addr ( o_dbg_addr ),
+.o_dbg_din ( o_dbg_din ),
+.o_axi4_wrstate ( o_axi4_wrstate ),
+.o_fifo_wr ( o_fifo_wr ),
+.o_fifo_full ( o_fifo_full ),
+.o_fifo_empty ( o_fifo_empty ),
+.o_dbg_fifo_waddr ( o_dbg_fifo_waddr ),
+.o_dbg_fifo_re ( o_dbg_fifo_re ),
+.o_dbg_fifo_raddr ( o_dbg_fifo_raddr ),
+.o_dbg_fifo_we ( o_dbg_fifo_we ),
+.o_dbg_axi4_wlast ( o_dbg_axi4_wlast ),
+.o_shift_cnt ( o_shift_cnt ),
+.o_re_lock ( o_re_lock ),
+.o_axi4_rastate ( o_axi4_rastate ),
+.o_axi4_nwr ( o_axi4_nwr ),
+.o_axi4_arlen ( o_axi4_arlen ),
+.o_axi4_rdstate ( o_axi4_rdstate ),
+.o_sdr_rd_valid ( o_sdr_rd_valid ),
+.o_sdr_dout ( o_sdr_dout ),
+.o_dbg_re ( o_dbg_re ),
+.o_AXI4_BID ( o_AXI4_BID ),
+.i_addr ( i_addr ),
+.i_din ( i_din ),
+.i_dm ( i_dm ),
+.o_dout ( o_dout ),
+.o_sdr_state ( o_sdr_state ),
+.o_sdr_init_done ( o_sdr_init_done ),
+.o_wr_ack ( o_wr_ack ),
+.o_rd_ack ( o_rd_ack ),
+.o_ref_req ( o_ref_req ),
+.o_rd_valid ( o_rd_valid ),
+.o_sdr_CKE ( o_sdr_CKE ),
+.o_sdr_n_CS ( o_sdr_n_CS ),
+.o_sdr_n_RAS ( o_sdr_n_RAS ),
+.o_sdr_n_CAS ( o_sdr_n_CAS ),
+.o_sdr_n_WE ( o_sdr_n_WE ),
+.o_sdr_BA ( o_sdr_BA ),
+.o_sdr_ADDR ( o_sdr_ADDR ),
+.o_sdr_DATA ( o_sdr_DATA ),
+.o_sdr_DATA_oe ( o_sdr_DATA_oe ),
+.i_sdr_DATA ( i_sdr_DATA ),
+.o_sdr_DQM ( o_sdr_DQM )
+);
diff --git a/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd b/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd
new file mode 100644
index 0000000..5161b7d
--- /dev/null
+++ b/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd
@@ -0,0 +1,220 @@
+--------------------------------------------------------------------------------
+-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+--
+-- This   document  contains  proprietary information  which   is        
+-- protected by  copyright. All rights  are reserved.  This notice       
+-- refers to original work by Efinix, Inc. which may be derivitive       
+-- of other work distributed under license of the authors.  In the       
+-- case of derivative work, nothing in this notice overrides the         
+-- original author's license agreement.  Where applicable, the           
+-- original license agreement is included in it's original               
+-- unmodified form immediately below this header.                        
+--                                                                       
+-- WARRANTY DISCLAIMER.                                                  
+--     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+--     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+--     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+--     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+--     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+--     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+--     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+--                                                                       
+-- LIMITATION OF LIABILITY.                                              
+--     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+--     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+--     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+--     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+--     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+--     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+--     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+--     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+--     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+--     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+--     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+--     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+--     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+--     APPLY TO LICENSEE.                                                
+--
+--------------------------------------------------------------------------------
+------------- Begin Cut here for COMPONENT Declaration ------
+COMPONENT sdram_controller is
+PORT (
+i_aresetn : in std_logic;
+i_AXI4_AWADDR : in std_logic_vector(23 downto 0);
+i_sysclk : in std_logic;
+i_sdrclk : in std_logic;
+i_tACclk : in std_logic;
+i_pll_locked : in std_logic;
+o_dbg_ref_req : out std_logic;
+o_dbg_wr_ack : out std_logic;
+o_dbg_rd_ack : out std_logic;
+o_dbg_n_CS : out std_logic_vector(1 downto 0);
+o_dbg_n_RAS : out std_logic_vector(1 downto 0);
+o_dbg_n_CAS : out std_logic_vector(1 downto 0);
+o_dbg_n_WE : out std_logic_vector(1 downto 0);
+o_dbg_BA : out std_logic_vector(3 downto 0);
+o_dbg_ADDR : out std_logic_vector(25 downto 0);
+o_dbg_DATA_out : out std_logic_vector(31 downto 0);
+o_dbg_DATA_in : out std_logic_vector(31 downto 0);
+o_pll_reset : out std_logic;
+o_AXI4_AWREADY : out std_logic;
+i_AXI4_AWVALID : in std_logic;
+o_AXI4_WREADY : out std_logic;
+i_AXI4_WDATA : in std_logic_vector(31 downto 0);
+i_AXI4_WSTRB : in std_logic_vector(3 downto 0);
+i_AXI4_WLAST : in std_logic;
+i_AXI4_WVALID : in std_logic;
+o_AXI4_BVALID : out std_logic;
+i_AXI4_BREADY : in std_logic;
+o_AXI4_ARREADY : out std_logic;
+i_AXI4_ARADDR : in std_logic_vector(23 downto 0);
+i_AXI4_RREADY : in std_logic;
+o_AXI4_RDATA : out std_logic_vector(31 downto 0);
+o_AXI4_RLAST : out std_logic;
+o_AXI4_RVALID : out std_logic;
+i_AXI4_AWID : in std_logic_vector(3 downto 0);
+i_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
+i_AXI4_ARVALID : in std_logic;
+i_AXI4_ARID : in std_logic_vector(3 downto 0);
+i_AXI4_ARLEN : in std_logic_vector(7 downto 0);
+i_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
+i_AXI4_ARBURST : in std_logic_vector(1 downto 0);
+i_AXI4_AWLEN : in std_logic_vector(7 downto 0);
+o_AXI4_RID : out std_logic_vector(3 downto 0);
+o_dbg_we : out std_logic;
+o_dbg_last : out std_logic;
+o_dbg_addr : out std_logic_vector(23 downto 0);
+o_dbg_din : out std_logic_vector(31 downto 0);
+o_axi4_wrstate : out std_logic_vector(1 downto 0);
+o_fifo_wr : out std_logic;
+o_fifo_full : out std_logic;
+o_fifo_empty : out std_logic;
+o_dbg_fifo_waddr : out std_logic_vector(7 downto 0);
+o_dbg_fifo_re : out std_logic;
+o_dbg_fifo_raddr : out std_logic_vector(7 downto 0);
+o_dbg_fifo_we : out std_logic;
+o_dbg_axi4_wlast : out std_logic;
+o_shift_cnt : out std_logic_vector(6 downto 0);
+o_re_lock : out std_logic;
+o_axi4_rastate : out std_logic_vector(1 downto 0);
+o_axi4_nwr : out std_logic;
+o_axi4_arlen : out std_logic_vector(7 downto 0);
+o_axi4_rdstate : out std_logic_vector(1 downto 0);
+o_sdr_rd_valid : out std_logic;
+o_sdr_dout : out std_logic_vector(36 downto 0);
+o_dbg_re : out std_logic;
+o_AXI4_BID : out std_logic_vector(3 downto 0);
+i_addr : in std_logic_vector(23 downto 0);
+i_din : in std_logic_vector(31 downto 0);
+i_dm : in std_logic_vector(3 downto 0);
+o_dout : out std_logic_vector(31 downto 0);
+o_sdr_state : out std_logic_vector(3 downto 0);
+o_sdr_init_done : out std_logic;
+o_wr_ack : out std_logic;
+o_rd_ack : out std_logic;
+o_ref_req : out std_logic;
+o_rd_valid : out std_logic;
+o_sdr_CKE : out std_logic_vector(1 downto 0);
+o_sdr_n_CS : out std_logic_vector(1 downto 0);
+o_sdr_n_RAS : out std_logic_vector(1 downto 0);
+o_sdr_n_CAS : out std_logic_vector(1 downto 0);
+o_sdr_n_WE : out std_logic_vector(1 downto 0);
+o_sdr_BA : out std_logic_vector(3 downto 0);
+o_sdr_ADDR : out std_logic_vector(25 downto 0);
+o_sdr_DATA : out std_logic_vector(31 downto 0);
+o_sdr_DATA_oe : out std_logic_vector(31 downto 0);
+i_sdr_DATA : in std_logic_vector(31 downto 0);
+o_sdr_DQM : out std_logic_vector(3 downto 0));
+END COMPONENT;
+---------------------- End COMPONENT Declaration ------------
+
+------------- Begin Cut here for INSTANTIATION Template -----
+u_sdram_controller : sdram_controller
+PORT MAP (
+i_aresetn => i_aresetn,
+i_AXI4_AWADDR => i_AXI4_AWADDR,
+i_sysclk => i_sysclk,
+i_sdrclk => i_sdrclk,
+i_tACclk => i_tACclk,
+i_pll_locked => i_pll_locked,
+o_dbg_ref_req => o_dbg_ref_req,
+o_dbg_wr_ack => o_dbg_wr_ack,
+o_dbg_rd_ack => o_dbg_rd_ack,
+o_dbg_n_CS => o_dbg_n_CS,
+o_dbg_n_RAS => o_dbg_n_RAS,
+o_dbg_n_CAS => o_dbg_n_CAS,
+o_dbg_n_WE => o_dbg_n_WE,
+o_dbg_BA => o_dbg_BA,
+o_dbg_ADDR => o_dbg_ADDR,
+o_dbg_DATA_out => o_dbg_DATA_out,
+o_dbg_DATA_in => o_dbg_DATA_in,
+o_pll_reset => o_pll_reset,
+o_AXI4_AWREADY => o_AXI4_AWREADY,
+i_AXI4_AWVALID => i_AXI4_AWVALID,
+o_AXI4_WREADY => o_AXI4_WREADY,
+i_AXI4_WDATA => i_AXI4_WDATA,
+i_AXI4_WSTRB => i_AXI4_WSTRB,
+i_AXI4_WLAST => i_AXI4_WLAST,
+i_AXI4_WVALID => i_AXI4_WVALID,
+o_AXI4_BVALID => o_AXI4_BVALID,
+i_AXI4_BREADY => i_AXI4_BREADY,
+o_AXI4_ARREADY => o_AXI4_ARREADY,
+i_AXI4_ARADDR => i_AXI4_ARADDR,
+i_AXI4_RREADY => i_AXI4_RREADY,
+o_AXI4_RDATA => o_AXI4_RDATA,
+o_AXI4_RLAST => o_AXI4_RLAST,
+o_AXI4_RVALID => o_AXI4_RVALID,
+i_AXI4_AWID => i_AXI4_AWID,
+i_AXI4_AWSIZE => i_AXI4_AWSIZE,
+i_AXI4_ARVALID => i_AXI4_ARVALID,
+i_AXI4_ARID => i_AXI4_ARID,
+i_AXI4_ARLEN => i_AXI4_ARLEN,
+i_AXI4_ARSIZE => i_AXI4_ARSIZE,
+i_AXI4_ARBURST => i_AXI4_ARBURST,
+i_AXI4_AWLEN => i_AXI4_AWLEN,
+o_AXI4_RID => o_AXI4_RID,
+o_dbg_we => o_dbg_we,
+o_dbg_last => o_dbg_last,
+o_dbg_addr => o_dbg_addr,
+o_dbg_din => o_dbg_din,
+o_axi4_wrstate => o_axi4_wrstate,
+o_fifo_wr => o_fifo_wr,
+o_fifo_full => o_fifo_full,
+o_fifo_empty => o_fifo_empty,
+o_dbg_fifo_waddr => o_dbg_fifo_waddr,
+o_dbg_fifo_re => o_dbg_fifo_re,
+o_dbg_fifo_raddr => o_dbg_fifo_raddr,
+o_dbg_fifo_we => o_dbg_fifo_we,
+o_dbg_axi4_wlast => o_dbg_axi4_wlast,
+o_shift_cnt => o_shift_cnt,
+o_re_lock => o_re_lock,
+o_axi4_rastate => o_axi4_rastate,
+o_axi4_nwr => o_axi4_nwr,
+o_axi4_arlen => o_axi4_arlen,
+o_axi4_rdstate => o_axi4_rdstate,
+o_sdr_rd_valid => o_sdr_rd_valid,
+o_sdr_dout => o_sdr_dout,
+o_dbg_re => o_dbg_re,
+o_AXI4_BID => o_AXI4_BID,
+i_addr => i_addr,
+i_din => i_din,
+i_dm => i_dm,
+o_dout => o_dout,
+o_sdr_state => o_sdr_state,
+o_sdr_init_done => o_sdr_init_done,
+o_wr_ack => o_wr_ack,
+o_rd_ack => o_rd_ack,
+o_ref_req => o_ref_req,
+o_rd_valid => o_rd_valid,
+o_sdr_CKE => o_sdr_CKE,
+o_sdr_n_CS => o_sdr_n_CS,
+o_sdr_n_RAS => o_sdr_n_RAS,
+o_sdr_n_CAS => o_sdr_n_CAS,
+o_sdr_n_WE => o_sdr_n_WE,
+o_sdr_BA => o_sdr_BA,
+o_sdr_ADDR => o_sdr_ADDR,
+o_sdr_DATA => o_sdr_DATA,
+o_sdr_DATA_oe => o_sdr_DATA_oe,
+i_sdr_DATA => i_sdr_DATA,
+o_sdr_DQM => o_sdr_DQM);
+------------------------ End INSTANTIATION Template ---------
diff --git a/hw/super6502_fpga/ip/sdram_controller/settings.json b/hw/super6502_fpga/ip/sdram_controller/settings.json
new file mode 100644
index 0000000..a021290
--- /dev/null
+++ b/hw/super6502_fpga/ip/sdram_controller/settings.json
@@ -0,0 +1,44 @@
+{
+    "args": [
+        "-o",
+        "sdram_controller",
+        "--base_path",
+        "/home/byron/Projects/super6502/hw/super6502_fpga/ip",
+        "--vlnv",
+        {
+            "vendor": "efinixinc.com",
+            "library": "memory_controller",
+            "name": "efx_sdram_controller",
+            "version": "5.0"
+        }
+    ],
+    "conf": {
+        "fCK_MHz": "200",
+        "tIORT_u": "2",
+        "CL": "3",
+        "DDIO_TYPE": "\"SOFT\"",
+        "DQ_GROUP": "2",
+        "ROW_WIDTH": "13",
+        "COL_WIDTH": "9",
+        "tPWRUP": "200000",
+        "tRAS": "44",
+        "tRAS_MAX": "120000",
+        "tRC": "66",
+        "tRCD": "20",
+        "tREF": "64000000",
+        "tRFC": "66",
+        "tRP": "20",
+        "SDRAM_MODE": "\"AXI4\"",
+        "DATA_RATE": "2"
+    },
+    "output": {
+        "external_source_source": [
+            "/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.v",
+            "/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller.v",
+            "/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd",
+            "/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller_define.vh"
+        ]
+    },
+    "sw_version": "2023.1.150",
+    "generated_date": "2024-03-04T01:51:33.450281"
+}
\ No newline at end of file
diff --git a/hw/super6502_fpga/sources.list b/hw/super6502_fpga/sources.list
index e717faa..b9113d1 100644
--- a/hw/super6502_fpga/sources.list
+++ b/hw/super6502_fpga/sources.list
@@ -11,4 +11,4 @@ src/sub/rtl-common/src/rtl/axi4_lite_rom.sv
 src/sub/rtl-common/src/rtl/ff_cdc.sv
 src/sub/rtl-common/src/rtl/shallow_async_fifo.sv
 src/sub/rtl-common/src/rtl/sync_fifo.sv
-
+ip/sdram_controller/sdram_controller.v
diff --git a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv
index 62429b3..84cdee6 100644
--- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv
+++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv
@@ -12,6 +12,19 @@ module super6502_fpga(
     input                       i_pll_locked,
     output  logic               o_pll_reset,
 
+    output  logic               o_sdr_CKE,
+    output  logic               o_sdr_n_CS,
+    output  logic               o_sdr_n_WE,
+    output  logic               o_sdr_n_RAS,
+    output  logic               o_sdr_n_CAS,
+    output  logic   [1:0]       o_sdr_BA,
+    output  logic   [12:0]      o_sdr_ADDR,
+    input   logic   [15:0]      i_sdr_DATA,
+    output  logic   [15:0]      o_sdr_DATA,
+    output  logic   [15:0]      o_sdr_DATA_oe,
+    output  logic   [1:0]       o_sdr_DQM,
+
+
     input           [7:0]       i_cpu0_data_from_cpu,
     input                       i_cpu0_sync,
     input                       i_cpu0_rwb,
@@ -38,10 +51,21 @@ assign o_clk_phi2 = clk_cpu;
 
 assign o_cpu0_data_oe = {8{i_cpu0_rwb}};
 
+logic vio0_reset;
+assign vio0_reset = '1;
 
 logic master_reset;
+logic sdram_ready;
+logic [3:0] w_sdr_state;
+
+logic pre_reset;
+
+assign pre_reset = button_reset & vio0_reset;
+
+assign sdram_ready = |w_sdr_state;
+
+assign master_reset = pre_reset & sdram_ready;
 
-assign master_reset = button_reset;
 
 logic                       cpu0_AWVALID;
 logic                       cpu0_AWREADY;
@@ -98,6 +122,24 @@ logic                       rom_rready;
 logic [DATA_WIDTH-1:0]      rom_rdata;
 logic [1:0]                 rom_rresp;
 
+logic                       sdram_AWVALID;
+logic                       sdram_AWREADY;
+logic  [ADDR_WIDTH-1:0]     sdram_AWADDR;
+logic                       sdram_WVALID;
+logic                       sdram_WREADY;
+logic  [DATA_WIDTH-1:0]     sdram_WDATA;
+logic  [DATA_WIDTH/8-1:0]   sdram_WSTRB;
+logic                       sdram_BVALID;
+logic                       sdram_BREADY;
+logic  [1:0]                sdram_BRESP;
+logic                       sdram_ARVALID;
+logic                       sdram_ARREADY;
+logic  [ADDR_WIDTH-1:0]     sdram_ARADDR;
+logic                       sdram_RVALID;
+logic                       sdram_RREADY;
+logic  [DATA_WIDTH-1:0]     sdram_RDATA;
+logic  [1:0]                sdram_RRESP;
+
 
 cpu_wrapper u_cpu_wrapper_0(
     .i_clk_cpu  (clk_cpu),
@@ -145,7 +187,7 @@ cpu_wrapper u_cpu_wrapper_0(
 
 axi_crossbar #(
     .N_INITIATORS(1),
-    .N_TARGETS(2)
+    .N_TARGETS(3)
 ) u_crossbar (
     .clk(i_sysclk),
     .rst(~master_reset),
@@ -168,23 +210,24 @@ axi_crossbar #(
     .ini_bvalid     ({cpu0_BVALID   }),
     .ini_bready     ({cpu0_BREADY   }),
 
-    .tgt_araddr     ({ram_araddr,   rom_araddr      }),
-    .tgt_arvalid    ({ram_arvalid,  rom_arvalid     }),
-    .tgt_arready    ({ram_arready,  rom_arready     }),
-    .tgt_rdata      ({ram_rdata,    rom_rdata       }),
-    .tgt_rresp      ({ram_rresp,    rom_rresp       }),
-    .tgt_rvalid     ({ram_rvalid,   rom_rvalid      }),
-    .tgt_rready     ({ram_rready,   rom_rready      }),
-    .tgt_awaddr     ({ram_awaddr,   rom_awaddr      }),
-    .tgt_awvalid    ({ram_awvalid,  rom_awvalid     }),
-    .tgt_awready    ({ram_awready,  rom_awready     }),
-    .tgt_wdata      ({ram_wdata,    rom_wdata       }),
-    .tgt_wvalid     ({ram_wvalid,   rom_wvalid      }),
-    .tgt_wready     ({ram_wready,   rom_wready      }),
-    .tgt_wstrb      ({ram_wstrb,    rom_wstrb       }),
-    .tgt_bresp      ({ram_bresp,    rom_bresp       }),
-    .tgt_bvalid     ({ram_bvalid,   rom_bvalid      }),
-    .tgt_bready     ({ram_bready,   rom_bready      })
+    .tgt_araddr     ({ram_araddr,   rom_araddr,     sdram_ARADDR    }),
+    .tgt_arvalid    ({ram_arvalid,  rom_arvalid,    sdram_ARVALID   }),
+    .tgt_arready    ({ram_arready,  rom_arready,    sdram_ARREADY   }),
+    .tgt_rdata      ({ram_rdata,    rom_rdata,      sdram_RDATA     }),
+    .tgt_rresp      ({ram_rresp,    rom_rresp,      sdram_RRESP     }),
+    .tgt_rvalid     ({ram_rvalid,   rom_rvalid,     sdram_RVALID    }),
+    .tgt_rready     ({ram_rready,   rom_rready,     sdram_RREADY    }),
+    .tgt_awaddr     ({ram_awaddr,   rom_awaddr,     sdram_AWADDR    }),
+    .tgt_awvalid    ({ram_awvalid,  rom_awvalid,    sdram_AWVALID   }),
+    .tgt_awready    ({ram_awready,  rom_awready,    sdram_AWREADY   }),
+    .tgt_wdata      ({ram_wdata,    rom_wdata,      sdram_WDATA     }),
+    .tgt_wvalid     ({ram_wvalid,   rom_wvalid,     sdram_WVALID    }),
+    .tgt_wready     ({ram_wready,   rom_wready,     sdram_WREADY    }),
+    .tgt_wstrb      ({ram_wstrb,    rom_wstrb,      sdram_WSTRB     }),
+    .tgt_bresp      ({ram_bresp,    rom_bresp,      sdram_BRESP     }),
+    .tgt_bvalid     ({ram_bvalid,   rom_bvalid,     sdram_BVALID    }),
+    .tgt_bready     ({ram_bready,   rom_bready,     sdram_BREADY    })
+
 );
 
 axi4_lite_rom #(
@@ -252,6 +295,79 @@ axi4_lite_ram #(
     .i_WSTRB(ram_wstrb)
 );
 
+logic [1:0] w_sdr_CKE;
+logic [1:0] w_sdr_n_CS;
+logic [1:0] w_sdr_n_RAS;
+logic [1:0] w_sdr_n_CAS;
+logic [1:0] w_sdr_n_WE;
+logic [3:0] w_sdr_BA;
+logic [25:0] w_sdr_ADDR;
+logic [31:0] w_sdr_DATA;
+logic [31:0] w_sdr_DATA_oe;
+logic [3:0] w_sdr_DQM;
+
+assign o_sdr_CKE = w_sdr_CKE[0];    //Using SOFT ddio, ignore second cycle
+assign o_sdr_n_CS = w_sdr_n_CS[0];
+assign o_sdr_n_RAS = w_sdr_n_RAS[0];
+assign o_sdr_n_CAS = w_sdr_n_CAS[0];
+assign o_sdr_n_WE = w_sdr_n_WE[0];
+assign o_sdr_BA = w_sdr_BA[0+:2];
+assign o_sdr_ADDR = w_sdr_ADDR[0+:13];
+assign o_sdr_DATA = w_sdr_DATA[0+:16];
+assign o_sdr_DATA_oe = w_sdr_DATA_oe[0+:16];
+assign o_sdr_DQM = w_sdr_DQM[0+:2];
+
+sdram_controller u_sdram_controller(
+    .i_aresetn          (pre_reset),
+    .i_sysclk           (i_sysclk),
+    .i_sdrclk           (i_sdrclk),
+    .i_tACclk           (i_tACclk),
+    .o_pll_reset        (),
+    .i_pll_locked       ('1),
+
+    .o_sdr_state        (w_sdr_state),
+
+    .i_AXI4_AWVALID     (sdram_AWVALID),
+    .o_AXI4_AWREADY     (sdram_AWREADY),
+    .i_AXI4_AWADDR      (sdram_AWADDR[23:0]),
+    .i_AXI4_WVALID      (sdram_WVALID),
+    .o_AXI4_WREADY      (sdram_WREADY),
+    .i_AXI4_WDATA       (sdram_WDATA),
+    .i_AXI4_WSTRB       (sdram_WSTRB),
+    .o_AXI4_BVALID      (sdram_BVALID),
+    .i_AXI4_BREADY      (sdram_BREADY),
+    .i_AXI4_ARVALID     (sdram_ARVALID),
+    .o_AXI4_ARREADY     (sdram_ARREADY),
+    .i_AXI4_ARADDR      (sdram_ARADDR[23:0]),
+    .o_AXI4_RVALID      (sdram_RVALID),
+    .i_AXI4_RREADY      (sdram_RREADY),
+    .o_AXI4_RDATA       (sdram_RDATA),
+
+    .i_AXI4_WLAST       (sdram_WVALID),
+    .o_AXI4_RLAST       (),
+    .i_AXI4_AWID        ('0),
+    .i_AXI4_AWSIZE      ('0),
+    .i_AXI4_ARID        ('0),
+    .i_AXI4_ARLEN       ('0),
+    .i_AXI4_ARSIZE      ('0),
+    .i_AXI4_ARBURST     ('0),
+    .i_AXI4_AWLEN       ('0),
+    .o_AXI4_RID         (),
+    .o_AXI4_BID         (),
+
+    .o_sdr_CKE          (w_sdr_CKE),
+    .o_sdr_n_CS         (w_sdr_n_CS),
+    .o_sdr_n_RAS        (w_sdr_n_RAS),
+    .o_sdr_n_CAS        (w_sdr_n_CAS),
+    .o_sdr_n_WE         (w_sdr_n_WE),
+    .o_sdr_BA           (w_sdr_BA),
+    .o_sdr_ADDR         (w_sdr_ADDR),
+    .o_sdr_DATA         (w_sdr_DATA),
+    .o_sdr_DATA_oe      (w_sdr_DATA_oe),
+    .i_sdr_DATA         ({{16'b0}, {i_sdr_DATA}}),
+    .o_sdr_DQM          (w_sdr_DQM)
+);
+
 
 
 endmodule
\ No newline at end of file
diff --git a/hw/super6502_fpga/src/sim/Makefile b/hw/super6502_fpga/src/sim/Makefile
index 1dccbe3..5c25611 100644
--- a/hw/super6502_fpga/src/sim/Makefile
+++ b/hw/super6502_fpga/src/sim/Makefile
@@ -4,17 +4,21 @@ SIM_SRCS_LIST=sources.list
 SUPER6502_FPGA_SOURCES=$(foreach file, $(shell cat $(FPGA_SRCS_LIST)), ../../$(file))
 SIM_SOURCES=$(shell cat $(SIM_SRCS_LIST))
 
+INCLUDE=include/sdram_controller_define.vh
+
 TB_NAME=sim_top
 
 COPY_FILES=addr_map.mem init_hex.mem
 
+FLAGS=-DSIM -DRTL_SIM
+
 all: waves
 
 waves: $(TB_NAME)
 	./$(TB_NAME) -fst
 
 $(TB_NAME): $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) $(COPY_FILES)
-	iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
+	iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
 
 $(COPY_FILES): ../../$@
 	cp ../../$@ .
@@ -23,4 +27,4 @@ $(COPY_FILES): ../../$@
 clean:
 	rm -rf $(COPY_FILES)
 	rm -rf $(TB_NAME)
-	rm -rf sim_top.vcd
\ No newline at end of file
+	rm -rf sim_top.vcd
diff --git a/hw/super6502_fpga/src/sim/hvl/sim_top.sv b/hw/super6502_fpga/src/sim/hvl/sim_top.sv
index 0afa07f..c4c29c8 100644
--- a/hw/super6502_fpga/src/sim/hvl/sim_top.sv
+++ b/hw/super6502_fpga/src/sim/hvl/sim_top.sv
@@ -2,6 +2,8 @@
 
 module sim_top();
 
+`include "include/sdram_controller_define.vh"
+
 localparam ADDR_WIDTH = 32;
 localparam DATA_WIDTH = 32;
 
@@ -71,11 +73,48 @@ cpu_65c02 u_cpu0 (
     .SYNC   (w_cpu0_sync)
 );
 
+logic                                   w_sdr_CKE;
+logic                                   w_sdr_n_CS;
+logic                                   w_sdr_n_WE;
+logic                                   w_sdr_n_RAS;
+logic                                   w_sdr_n_CAS;
+logic   [BA_WIDTH				-1:0]   w_sdr_BA;
+logic   [ROW_WIDTH				-1:0]   w_sdr_ADDR;
+logic   [DQ_GROUP	*DQ_WIDTH	-1:0]   w_sdr_DATA;
+logic   [DQ_GROUP	*DQ_WIDTH	-1:0]   w_sdr_DATA_oe;
+logic   [DQ_GROUP				-1:0]   w_sdr_DQM;
+wire    [DQ_GROUP	*DQ_WIDTH	-1:0]   w_sdr_DQ;
+// ^ Has to be wire because of tristate/inout stuff
+
+genvar i, j;
+generate
+    for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
+    begin: DQ_map
+        assign	w_sdr_DQ[i]	=	(w_sdr_DATA_oe[i]) ? w_sdr_DATA[i] : 1'bz;
+    end
+
+    for (j=0; j<DQ_GROUP; j=j+1)
+    begin : mem_inst
+        generic_sdr inst_sdr
+        (
+            .Dq(w_sdr_DQ[((j+1)*(DQ_WIDTH))-1:((j)*DQ_WIDTH)]),
+            .Addr(w_sdr_ADDR[ROW_WIDTH-1:0]),
+            .Ba(w_sdr_BA[BA_WIDTH-1:0]),
+            .Clk(~clk_200),
+            .Cke(w_sdr_CKE),
+            .Cs_n(w_sdr_n_CS),
+            .Ras_n(w_sdr_n_RAS),
+            .Cas_n(w_sdr_n_CAS),
+            .We_n(w_sdr_n_WE),
+            .Dqm(w_sdr_DQM[j])
+        );
+    end
+endgenerate
 
 super6502_fpga u_dut (
     .i_sysclk               (clk_100),
     .i_sdrclk               (clk_200),
-    .i_tACclk               (clk_200),
+    .i_tACclk               (~clk_200),
     .clk_cpu                (clk_cpu),
 
     .button_reset           (button_reset),
@@ -87,7 +126,20 @@ super6502_fpga u_dut (
     .o_cpu0_rdy             (w_cpu0_rdy),
     .o_cpu0_irqb            (w_cpu0_irqb),
     .i_cpu0_rwb             (~w_cpu0_we),
-    .i_cpu0_sync            (w_cpu0_sync)
+    .i_cpu0_sync            (w_cpu0_sync),
+
+    .o_sdr_CKE              (w_sdr_CKE),
+    .o_sdr_n_CS             (w_sdr_n_CS),
+    .o_sdr_n_WE             (w_sdr_n_WE),
+    .o_sdr_n_RAS            (w_sdr_n_RAS),
+    .o_sdr_n_CAS            (w_sdr_n_CAS),
+    .o_sdr_BA               (w_sdr_BA),
+    .o_sdr_ADDR             (w_sdr_ADDR),
+    .i_sdr_DATA             (w_sdr_DQ),
+    .o_sdr_DATA             (w_sdr_DATA),
+    .o_sdr_DATA_oe          (w_sdr_DATA_oe),
+    .o_sdr_DQM              (w_sdr_DQM)
+
 );
 
 initial begin
diff --git a/hw/super6502_fpga/src/sim/include/sdram_controller_define.vh b/hw/super6502_fpga/src/sim/include/sdram_controller_define.vh
new file mode 100644
index 0000000..2f11d84
--- /dev/null
+++ b/hw/super6502_fpga/src/sim/include/sdram_controller_define.vh
@@ -0,0 +1,80 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.1.150
+// IP Version: 5.0
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+localparam fSYS_MHz = 100;
+localparam fCK_MHz = 200;
+localparam tIORT_u = 2;
+localparam CL = 3;
+localparam BL = 1;
+localparam DDIO_TYPE = "SOFT";
+localparam DQ_WIDTH = 8;
+localparam DQ_GROUP = 2;
+localparam BA_WIDTH = 2;
+localparam ROW_WIDTH = 13;
+localparam COL_WIDTH = 9;
+localparam tPWRUP = 200000;
+localparam tRAS = 44;
+localparam tRAS_MAX = 120000;
+localparam tRC = 66;
+localparam tRCD = 20;
+localparam tREF = 64000000;
+localparam tRFC = 66;
+localparam tRP = 20;
+localparam tWR = 2;
+localparam tMRD = 2;
+localparam SDRAM_MODE = "AXI4";
+localparam DATA_RATE = 2;
+localparam AXI_AWADDR_WIDTH = 24;
+localparam AXI_WDATA_WIDTH = 32;
+localparam AXI_ARADDR_WIDTH = 24;
+localparam AXI_RDATA_WIDTH = 32;
+localparam AXI_AWID_WIDTH = 4;
+localparam AXI_AWUSER_WIDTH = 2;
+localparam AXI_WUSER_WIDTH = 2;
+localparam AXI_BID_WIDTH = 4;
+localparam AXI_BUSER_WIDTH = 2;
+localparam AXI_ARID_WIDTH = 4;
+localparam AXI_ARUSER_WIDTH = 3;
+localparam AXI_RUSER_WIDTH = 3;
diff --git a/hw/super6502_fpga/src/sim/sources.list b/hw/super6502_fpga/src/sim/sources.list
index ae52ea2..fd86d41 100644
--- a/hw/super6502_fpga/src/sim/sources.list
+++ b/hw/super6502_fpga/src/sim/sources.list
@@ -1,3 +1,4 @@
 hvl/sim_top.sv
 sub/verilog-6502/ALU.v
-sub/verilog-6502/cpu_65c02.v
\ No newline at end of file
+sub/verilog-6502/cpu_65c02.v
+sub/sim_sdram/generic_sdr.v
\ No newline at end of file
diff --git a/hw/super6502_fpga/src/sim/sub/sim_sdram/generic_sdr.v b/hw/super6502_fpga/src/sim/sub/sim_sdram/generic_sdr.v
new file mode 100644
index 0000000..aaa53f7
--- /dev/null
+++ b/hw/super6502_fpga/src/sim/sub/sim_sdram/generic_sdr.v
@@ -0,0 +1,1145 @@
+/**************************************************************************
+*
+*    File Name:  sdr.v  
+*      Version:  2.2
+*         Date:  October 12th, 2010
+*        Model:  BUS Functional
+*    Simulator:  Model Technology
+*
+* Dependencies:  None
+*
+*        Email:  modelsupport@micron.com
+*      Company:  Micron Technology, Inc.
+*
+*  Description:  Micron SDRAM Verilog model
+*
+*   Limitation:  - Doesn't check for refresh timing
+*
+*         Note:  - Set simulator resolution to "ps" accuracy
+*                - Set Debug = 0 to disable $display messages
+*
+*   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
+*                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
+*                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
+*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
+*
+*                Copyright � 2001 Micron Semiconductor Products, Inc.
+*                All rights researved
+*
+* Rev  Author          Date        Changes
+* ---  --------------------------  ---------------------------------------
+* 2.3  SH              05/12/2016  - Update tAC, tHZ timing
+*      Micron Technology Inc.
+*
+* 2.2  SH              10/12/2010  - Combine all parts into sdr_parameters.vh
+*      Micron Technology Inc.
+*
+* 2.1  SH              06/06/2002  - Typo in bank multiplex
+*      Micron Technology Inc.
+*
+* 2.0  SH              04/30/2002  - Second release
+*      Micron Technology Inc.
+*
+**************************************************************************/
+
+`timescale 1ns / 1ps
+`define x8
+`define CLK_200
+`define SYS_CLK_100
+
+module generic_sdr (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
+	
+`include "include/sdram_controller_define.vh"
+
+parameter tCK              =     1000/fCK_MHz; // tCK    ns    Nominal Clock Cycle Time
+`ifdef CLK_200
+    parameter real tAC3             =     4.5; // tAC3   ns    Access time from CLK (pos edge) CL = 3
+    parameter real tAC2             =     4.5; // tAC2   ns    Access time from CLK (pos edge) CL = 2
+    parameter real tAC1             =     4.5; // tAC1   ns    Parameter definition for compilation - CL = 1 illegal for sg75
+`elsif CLK_166
+    parameter real tAC3             =     5.4; // tAC3   ns    Access time from CLK (pos edge) CL = 3
+    parameter real tAC2             =     5.4; // tAC2   ns    Access time from CLK (pos edge) CL = 2
+    parameter real tAC1             =     5.4; // tAC1   ns    Parameter definition for compilation - CL = 1 illegal for sg75
+`elsif CLK_133
+    parameter real tAC3             =     6.0; // tAC3   ns    Access time from CLK (pos edge) CL = 3
+    parameter real tAC2             =     6.0; // tAC2   ns    Access time from CLK (pos edge) CL = 2
+    parameter real tAC1             =     6.0; // tAC1   ns    Parameter definition for compilation - CL = 1 illegal for sg75
+`endif    
+    
+`ifdef CLK_200
+    parameter real tHZ3             =     4.5; // tHZ3   ns    Data Out High Z time - CL = 3
+    parameter real tHZ2             =     4.5; // tHZ2   ns    Data Out High Z time - CL = 2
+    parameter real tHZ1             =     4.5; // tHZ1   ns    Parameter definition for compilation - CL = 1 illegal for sg75
+`elsif CLK_166
+    parameter real tHZ3             =     5.4; // tHZ3   ns    Data Out High Z time - CL = 3
+    parameter real tHZ2             =     5.4; // tHZ2   ns    Data Out High Z time - CL = 2
+    parameter real tHZ1             =     5.4; // tHZ1   ns    Parameter definition for compilation - CL = 1 illegal for sg75
+`elsif CLK_133
+    parameter real tHZ3             =     6.0; // tHZ3   ns    Data Out High Z time - CL = 3
+    parameter real tHZ2             =     6.0; // tHZ2   ns    Data Out High Z time - CL = 2
+    parameter real tHZ1             =     6.0; // tHZ1   ns    Parameter definition for compilation - CL = 1 illegal for sg75
+`endif
+
+parameter tOH              =     2.7; // tOH    ns    Data Out Hold time
+parameter tRRD             =     2.0; // tRRD   tCK   Active bank a to Active bank b command time (2 * tCK)
+parameter tWRa             =     tCK; // tWR    ns    Write recovery time (auto-precharge mode - must add 1 CLK)
+parameter tWRm             =   2*tCK; // tWR    ns    Write recovery time	
+parameter ADDR_BITS        = ROW_WIDTH; // Set this parameter to control how many Address bits are used
+parameter ROW_BITS         = ROW_WIDTH; // Set this parameter to control how many Row bits are used
+parameter COL_BITS         = COL_WIDTH; // Set this parameter to control how many Column bits are used
+parameter DQ_BITS          = DQ_WIDTH; // Set this parameter to control how many Data bits are used
+parameter DM_BITS          = 1; // Set this parameter to control how many DM bits are used
+parameter BA_BITS          = BA_WIDTH; // Bank bits
+parameter mem_sizes        = 2**(ROW_BITS+COL_BITS) - 1;
+
+    input                         Clk;
+    input                         Cke;
+    input                         Cs_n;
+    input                         Ras_n;
+    input                         Cas_n;
+    input                         We_n;
+    input     [ADDR_BITS - 1 : 0] Addr;
+    input       [BA_BITS - 1 : 0] Ba;
+    inout       [DQ_BITS - 1 : 0] Dq;
+    input       [DM_BITS - 1 : 0] Dqm;
+
+    reg         [DQ_BITS - 1 : 0] Bank0 [0 : mem_sizes];
+    reg         [DQ_BITS - 1 : 0] Bank1 [0 : mem_sizes];
+    reg         [DQ_BITS - 1 : 0] Bank2 [0 : mem_sizes];
+    reg         [DQ_BITS - 1 : 0] Bank3 [0 : mem_sizes];
+
+    reg                   [1 : 0] Bank_addr [0 : 3];                // Bank Address Pipeline
+    reg        [COL_BITS - 1 : 0] Col_addr [0 : 3];                 // Column Address Pipeline
+    reg                   [3 : 0] Command [0 : 3];                  // Command Operation Pipeline
+    reg                   [1 : 0] Dqm_reg0, Dqm_reg1;               // DQM Operation Pipeline
+    reg       [ADDR_BITS - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
+
+    reg       [ADDR_BITS - 1 : 0] Mode_reg;
+    reg         [DQ_BITS - 1 : 0] Dq_reg, Dq_dqm;
+    reg        [COL_BITS - 1 : 0] Col_temp, Burst_counter;
+
+    reg                           Act_b0, Act_b1, Act_b2, Act_b3;   // Bank Activate
+    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;       // Bank Precharge
+
+    reg                   [1 : 0] Bank_precharge       [0 : 3];     // Precharge Command
+    reg                           A10_precharge        [0 : 3];     // Addr[10] = 1 (All banks)
+    reg                           Auto_precharge       [0 : 3];     // RW Auto Precharge (Bank)
+    reg                           Read_precharge       [0 : 3];     // R  Auto Precharge
+    reg                           Write_precharge      [0 : 3];     //  W Auto Precharge
+    reg                           RW_interrupt_read    [0 : 3];     // RW Interrupt Read with Auto Precharge
+    reg                           RW_interrupt_write   [0 : 3];     // RW Interrupt Write with Auto Precharge
+    reg                   [1 : 0] RW_interrupt_bank;                // RW Interrupt Bank
+    integer                       RW_interrupt_counter [0 : 3];     // RW Interrupt Counter
+    integer                       Count_precharge      [0 : 3];     // RW Auto Precharge Counter
+
+    reg                           Data_in_enable;
+    reg                           Data_out_enable;
+
+    reg                   [1 : 0] Bank, Prev_bank;
+    reg       [ADDR_BITS - 1 : 0] Row;
+    reg        [COL_BITS - 1 : 0] Col, Col_brst;
+
+    // Internal system clock
+    reg                           CkeZ, Sys_clk;
+
+    // Commands Decode
+    wire      Active_enable    = ~Cs_n & ~Ras_n &  Cas_n &  We_n;
+    wire      Aref_enable      = ~Cs_n & ~Ras_n & ~Cas_n &  We_n;
+    wire      Burst_term       = ~Cs_n &  Ras_n &  Cas_n & ~We_n;
+    wire      Mode_reg_enable  = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
+    wire      Prech_enable     = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;
+    wire      Read_enable      = ~Cs_n &  Ras_n & ~Cas_n &  We_n;
+    wire      Write_enable     = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;
+
+    // Burst Length Decode
+    wire      Burst_length_1   = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
+    wire      Burst_length_2   = ~Mode_reg[2] & ~Mode_reg[1] &  Mode_reg[0];
+    wire      Burst_length_4   = ~Mode_reg[2] &  Mode_reg[1] & ~Mode_reg[0];
+    wire      Burst_length_8   = ~Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
+    wire      Burst_length_f   =  Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
+
+    // CAS Latency Decode
+    wire [2 : 0] Cas_latency   =  {Mode_reg[6],  Mode_reg[5],   Mode_reg[4]};
+
+    // Write Burst Mode
+    wire      Write_burst_mode = Mode_reg[9];
+
+    wire      Debug            = 1'b0;                          // Debug messages : 1 = On
+    wire      Dq_chk           = Sys_clk & Data_in_enable;      // Check setup/hold time for DQ
+    
+    assign    Dq               = Dq_reg;                        // DQ buffer
+
+    // Commands Operation
+    `define   ACT       0
+    `define   NOP       1
+    `define   READ      2
+    `define   WRITE     3
+    `define   PRECH     4
+    `define   A_REF     5
+    `define   BST       6
+    `define   LMR       7
+
+    // These timing dynamically adjust based on CAS Latency
+    time  tAC, tHZ;
+
+    // Timing Check variable
+    time  MRD_chk;
+    time  WR_chkm [0 : 3];
+    time  RFC_chk, RRD_chk;
+    time  RC_chk0, RC_chk1, RC_chk2, RC_chk3;
+    time  RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
+    time  RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
+    time  RP_chk0, RP_chk1, RP_chk2, RP_chk3;
+
+    initial begin
+        Dq_reg = {DQ_BITS{1'bz}};
+        Data_in_enable = 0; Data_out_enable = 0;
+        Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
+        Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
+        WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0;
+        RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
+        RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
+        MRD_chk = 0; RFC_chk = 0; RRD_chk = 0;
+        RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
+        RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
+        RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
+        RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
+        $timeformat (-9, 1, " ns", 12);
+    end
+
+    // System clock generator
+    always begin
+        @ (posedge Clk) begin
+            Sys_clk = CkeZ;
+            CkeZ = Cke;
+        end
+        @ (negedge Clk) begin
+            Sys_clk = 1'b0;
+        end
+    end
+
+    // Adjust tAC, tHZ based on CAS Latency
+    always @ (Cas_latency) begin
+        case (Cas_latency)
+            1 : begin tAC = tAC1; tHZ = tHZ1; end
+            2 : begin tAC = tAC2; tHZ = tHZ2; end
+            3 : begin tAC = tAC3; tHZ = tHZ3; end
+        endcase
+    end
+
+    always @ (posedge Sys_clk) begin
+        // Internal Commamd Pipelined
+        Command[0] = Command[1];
+        Command[1] = Command[2];
+        Command[2] = Command[3];
+        Command[3] = `NOP;
+
+        Col_addr[0] = Col_addr[1];
+        Col_addr[1] = Col_addr[2];
+        Col_addr[2] = Col_addr[3];
+        Col_addr[3] = {COL_BITS{1'b0}};
+
+        Bank_addr[0] = Bank_addr[1];
+        Bank_addr[1] = Bank_addr[2];
+        Bank_addr[2] = Bank_addr[3];
+        Bank_addr[3] = 2'b0;
+
+        Bank_precharge[0] = Bank_precharge[1];
+        Bank_precharge[1] = Bank_precharge[2];
+        Bank_precharge[2] = Bank_precharge[3];
+        Bank_precharge[3] = 2'b0;
+
+        A10_precharge[0] = A10_precharge[1];
+        A10_precharge[1] = A10_precharge[2];
+        A10_precharge[2] = A10_precharge[3];
+        A10_precharge[3] = 1'b0;
+
+        // Dqm pipeline for Read
+        Dqm_reg0 = Dqm_reg1;
+        Dqm_reg1 = Dqm;
+
+        // Read or Write with Auto Precharge Counter
+        if (Auto_precharge[0] === 1'b1) begin
+            Count_precharge[0] = Count_precharge[0] + 1;
+        end
+        if (Auto_precharge[1] === 1'b1) begin
+            Count_precharge[1] = Count_precharge[1] + 1;
+        end
+        if (Auto_precharge[2] === 1'b1) begin
+            Count_precharge[2] = Count_precharge[2] + 1;
+        end
+        if (Auto_precharge[3] === 1'b1) begin
+            Count_precharge[3] = Count_precharge[3] + 1;
+        end
+
+        // Read or Write Interrupt Counter
+        if (RW_interrupt_write[0] === 1'b1) begin
+            RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;
+        end
+        if (RW_interrupt_write[1] === 1'b1) begin
+            RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;
+        end
+        if (RW_interrupt_write[2] === 1'b1) begin
+            RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;
+        end
+        if (RW_interrupt_write[3] === 1'b1) begin
+            RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;
+        end
+
+        // tMRD Counter
+        MRD_chk = MRD_chk + 1;
+
+        // Auto Refresh
+        if (Aref_enable === 1'b1) begin
+            if (Debug) begin
+                $display ("%m : at time %t AREF : Auto Refresh", $time);
+            end
+
+            // Auto Refresh to Auto Refresh
+            if ($time - RFC_chk < tRFC) begin
+                $display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $time);
+            end
+
+            // Precharge to Auto Refresh
+            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
+                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
+                $display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time);
+            end
+
+            // Precharge to Refresh
+            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
+                $display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
+            end
+
+            // Load Mode Register to Auto Refresh
+            if (MRD_chk < tMRD) begin
+                $display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time);
+            end
+
+            // Record Current tRFC time
+            RFC_chk = $time;
+        end
+        
+        // Load Mode Register
+        if (Mode_reg_enable === 1'b1) begin
+            // Register Mode
+            Mode_reg = Addr;
+
+            // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
+            if (Debug) begin
+                $display ("%m : at time %t LMR  : Load Mode Register", $time);
+                // CAS Latency
+                case (Addr[6 : 4])
+                    3'b010  : $display ("%m :                             CAS Latency      = 2");
+                    3'b011  : $display ("%m :                             CAS Latency      = 3");
+                    default : $display ("%m :                             CAS Latency      = Reserved");
+                endcase
+
+                // Burst Length
+                case (Addr[2 : 0])
+                    3'b000  : $display ("%m :                             Burst Length     = 1");
+                    3'b001  : $display ("%m :                             Burst Length     = 2");
+                    3'b010  : $display ("%m :                             Burst Length     = 4");
+                    3'b011  : $display ("%m :                             Burst Length     = 8");
+                    3'b111  : $display ("%m :                             Burst Length     = Full");
+                    default : $display ("%m :                             Burst Length     = Reserved");
+                endcase
+
+                // Burst Type
+                if (Addr[3] === 1'b0) begin
+                    $display ("%m :                             Burst Type       = Sequential");
+                end else if (Addr[3] === 1'b1) begin
+                    $display ("%m :                             Burst Type       = Interleaved");
+                end else begin
+                    $display ("%m :                             Burst Type       = Reserved");
+                end
+
+                // Write Burst Mode
+                if (Addr[9] === 1'b0) begin
+                    $display ("%m :                             Write Burst Mode = Programmed Burst Length");
+                end else if (Addr[9] === 1'b1) begin
+                    $display ("%m :                             Write Burst Mode = Single Location Access");
+                end else begin
+                    $display ("%m :                             Write Burst Mode = Reserved");
+                end
+            end
+
+            // Precharge to Load Mode Register
+            if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin
+                $display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
+            end
+
+            // Precharge to Load Mode Register
+            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
+                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
+                $display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time);
+            end
+
+            // Auto Refresh to Load Mode Register
+            if ($time - RFC_chk < tRFC) begin
+                $display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $time);
+            end
+
+            // Load Mode Register to Load Mode Register
+            if (MRD_chk < tMRD) begin
+                $display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time);
+            end
+
+            // Reset MRD Counter
+            MRD_chk = 0;
+        end
+        
+        // Active Block (Latch Bank Address and Row Address)
+        if (Active_enable === 1'b1) begin
+            // Activate an open bank can corrupt data
+            if ((Ba === 2'b00 && Act_b0 === 1'b1) || (Ba === 2'b01 && Act_b1 === 1'b1) ||
+                (Ba === 2'b10 && Act_b2 === 1'b1) || (Ba === 2'b11 && Act_b3 === 1'b1)) begin
+                $display ("%m : at time %t ERROR: Bank already activated -- data can be corrupted", $time);
+            end
+
+            // Activate Bank 0
+            if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
+                // Debug Message
+                if (Debug) begin
+                    $display ("%m : at time %t ACT  : Bank = 0 Row = %d", $time, Addr);
+                end
+
+                // ACTIVE to ACTIVE command period
+                if ($time - RC_chk0 < tRC) begin
+                    $display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time);
+                end
+
+                // Precharge to Activate Bank 0
+                if ($time - RP_chk0 < tRP) begin
+                    $display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time);
+                end
+
+                // Record variables
+                Act_b0 = 1'b1;
+                Pc_b0 = 1'b0;
+                B0_row_addr = Addr [ADDR_BITS - 1 : 0];
+                RAS_chk0 = $time;
+                RC_chk0 = $time;
+                RCD_chk0 = $time;
+            end
+
+            if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
+                // Debug Message
+                if (Debug) begin
+                    $display ("%m : at time %t ACT  : Bank = 1 Row = %d", $time, Addr);
+                end
+
+                // ACTIVE to ACTIVE command period
+                if ($time - RC_chk1 < tRC) begin
+                    $display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time);
+                end
+
+                // Precharge to Activate Bank 1
+                if ($time - RP_chk1 < tRP) begin
+                    $display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time);
+                end
+
+                // Record variables
+                Act_b1 = 1'b1;
+                Pc_b1 = 1'b0;
+                B1_row_addr = Addr [ADDR_BITS - 1 : 0];
+                RAS_chk1 = $time;
+                RC_chk1 = $time;
+                RCD_chk1 = $time;
+            end
+
+            if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
+                // Debug Message
+                if (Debug) begin
+                    $display ("%m : at time %t ACT  : Bank = 2 Row = %d", $time, Addr);
+                end
+
+                // ACTIVE to ACTIVE command period
+                if ($time - RC_chk2 < tRC) begin
+                    $display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time);
+                end
+
+                // Precharge to Activate Bank 2
+                if ($time - RP_chk2 < tRP) begin
+                    $display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time);
+                end
+
+                // Record variables
+                Act_b2 = 1'b1;
+                Pc_b2 = 1'b0;
+                B2_row_addr = Addr [ADDR_BITS - 1 : 0];
+                RAS_chk2 = $time;
+                RC_chk2 = $time;
+                RCD_chk2 = $time;
+            end
+
+            if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
+                // Debug Message
+                if (Debug) begin
+                    $display ("%m : at time %t ACT  : Bank = 3 Row = %d", $time, Addr);
+                end
+
+                // ACTIVE to ACTIVE command period
+                if ($time - RC_chk3 < tRC) begin
+                    $display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time);
+                end
+
+                // Precharge to Activate Bank 3
+                if ($time - RP_chk3 < tRP) begin
+                    $display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time);
+                end
+
+                // Record variables
+                Act_b3 = 1'b1;
+                Pc_b3 = 1'b0;
+                B3_row_addr = Addr [ADDR_BITS - 1 : 0];
+                RAS_chk3 = $time;
+                RC_chk3 = $time;
+                RCD_chk3 = $time;
+            end
+
+            // Active Bank A to Active Bank B
+            if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
+                $display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
+            end
+
+            // Auto Refresh to Activate
+            if ($time - RFC_chk < tRFC) begin
+                $display ("%m : at time %t ERROR: tRFC violation during Activate bank = %d", $time, Ba);
+            end
+
+            // Load Mode Register to Active
+            if (MRD_chk < tMRD ) begin
+                $display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
+            end
+
+            // Record variables for checking violation
+            RRD_chk = $time;
+            Prev_bank = Ba;
+        end
+        
+        // Precharge Block
+        if (Prech_enable == 1'b1) begin
+            // Load Mode Register to Precharge
+            if ($time - MRD_chk < tMRD) begin
+                $display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time);
+            end
+
+            // Precharge Bank 0
+            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
+                Act_b0 = 1'b0;
+                Pc_b0 = 1'b1;
+                RP_chk0 = $time;
+                
+                // Debug Message
+                if (Debug) begin
+                    $display ("%m : at time %t PRECHARGE  : Bank = 0", $time);
+                end
+
+                // Activate to Precharge
+                if ($time - RAS_chk0 < tRAS) begin
+                    $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
+                end
+
+                // tWR violation check for write
+                if ($time - WR_chkm[0] < tWRm) begin
+                    $display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
+                end
+            end
+
+            // Precharge Bank 1
+            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
+                Act_b1 = 1'b0;
+                Pc_b1 = 1'b1;
+                RP_chk1 = $time;
+                
+                // Debug Message
+                if (Debug) begin
+                    $display ("%m : at time %t PRECHARGE  : Bank = 1", $time);
+                end
+
+                // Activate to Precharge
+                if ($time - RAS_chk1 < tRAS) begin
+                    $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
+                end
+
+                // tWR violation check for write
+                if ($time - WR_chkm[1] < tWRm) begin
+                    $display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
+                end
+            end
+
+            // Precharge Bank 2
+            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
+                Act_b2 = 1'b0;
+                Pc_b2 = 1'b1;
+                RP_chk2 = $time;
+                
+                // Debug Message
+                if (Debug) begin
+                    $display ("%m : at time %t PRECHARGE  : Bank = 2", $time);
+                end
+
+                // Activate to Precharge
+                if ($time - RAS_chk2 < tRAS) begin
+                    $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
+                end
+
+                // tWR violation check for write
+                if ($time - WR_chkm[2] < tWRm) begin
+                    $display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
+                end
+            end
+
+            // Precharge Bank 3
+            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
+                Act_b3 = 1'b0;
+                Pc_b3 = 1'b1;
+                RP_chk3 = $time;
+                
+                // Debug Message
+                if (Debug) begin
+                    $display ("%m : at time %t PRECHARGE  : Bank = 3", $time);
+                end
+
+                // Activate to Precharge
+                if ($time - RAS_chk3 < tRAS) begin
+                    $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
+                end
+
+                // tWR violation check for write
+                if ($time - WR_chkm[3] < tWRm) begin
+                    $display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
+                end
+            end
+
+            // Precharge truncation with DQM set
+            if ((Data_in_enable == 1'b1) && ~(&Dqm)) begin
+                $display ("%m : at time %t ERROR: DQM not asserted during Precharge truncation", $time);
+            end
+
+            // Terminate a Write Immediately (if same bank or all banks)
+            if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin
+                Data_in_enable = 1'b0;
+            end
+
+            // Precharge Command Pipeline for Read
+            Command[Cas_latency - 1] = `PRECH;
+            Bank_precharge[Cas_latency - 1] = Ba;
+            A10_precharge[Cas_latency - 1] = Addr[10];
+        end
+        
+        // Burst terminate
+        if (Burst_term === 1'b1) begin
+            // Terminate a Write Immediately
+            if (Data_in_enable == 1'b1) begin
+                Data_in_enable = 1'b0;
+            end
+
+            // Terminate a Read Depend on CAS Latency
+            Command[Cas_latency - 1] = `BST;
+
+            // Display debug message
+            if (Debug) begin
+                $display ("%m : at time %t BST  : Burst Terminate",$time);
+            end
+        end
+        
+        // Read, Write, Column Latch
+        if (Read_enable === 1'b1) begin
+            // Check to see if bank is open (ACT)
+            if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
+                (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
+                $display("%m : at time %t ERROR: Bank is not Activated for Read", $time);
+            end
+
+            // Activate to Read or Write
+            if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
+                (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
+                (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
+                (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
+                $display("%m : at time %t ERROR: tRCD violation during Read", $time);
+            end
+
+            // CAS Latency pipeline
+            Command[Cas_latency - 1] = `READ;
+            Col_addr[Cas_latency - 1] = Addr;
+            Bank_addr[Cas_latency - 1] = Ba;
+
+            // Read interrupt Write (terminate Write immediately)
+            if (Data_in_enable == 1'b1) begin
+                Data_in_enable = 1'b0;
+
+                // Interrupting a Write with Autoprecharge
+                if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
+                    RW_interrupt_write[RW_interrupt_bank] = 1'b1;
+                    RW_interrupt_counter[RW_interrupt_bank] = 0;
+
+                    // Display debug message
+                    if (Debug) begin
+                        $display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $time);
+                    end
+                end
+            end
+
+            // Read with Auto Precharge
+            if (Addr[10] == 1'b1) begin
+                Auto_precharge[Ba] = 1'b1;
+                Count_precharge[Ba] = 0;
+                RW_interrupt_bank = Ba;
+                Read_precharge[Ba] = 1'b1;
+            end
+        end
+
+        // Write Command
+        if (Write_enable == 1'b1) begin
+            // Activate to Write
+            if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
+                (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
+                $display("%m : at time %t ERROR: Bank is not Activated for Write", $time);
+            end
+
+            // Activate to Read or Write
+            if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
+                (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
+                (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
+                (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
+                $display("%m : at time %t ERROR: tRCD violation during Read", $time);
+            end
+
+            // Latch Write command, Bank, and Column
+            Command[0] = `WRITE;
+            Col_addr[0] = Addr;
+            Bank_addr[0] = Ba;
+
+            // Write interrupt Write (terminate Write immediately)
+            if (Data_in_enable == 1'b1) begin
+                Data_in_enable = 1'b0;
+
+                // Interrupting a Write with Autoprecharge
+                if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
+                    RW_interrupt_write[RW_interrupt_bank] = 1'b1;
+
+                    // Display debug message
+                    if (Debug) begin
+                        $display ("%m : at time %t NOTE : Read Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
+                    end
+                end
+            end
+
+            // Write interrupt Read (terminate Read immediately)
+            if (Data_out_enable == 1'b1) begin
+                Data_out_enable = 1'b0;
+                
+                // Interrupting a Read with Autoprecharge
+                if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
+                    RW_interrupt_read[RW_interrupt_bank] = 1'b1;
+
+                    // Display debug message
+                    if (Debug) begin
+                        $display ("%m : at time %t NOTE : Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
+                    end
+                end
+            end
+
+            // Write with Auto Precharge
+            if (Addr[10] == 1'b1) begin
+                Auto_precharge[Ba] = 1'b1;
+                Count_precharge[Ba] = 0;
+                RW_interrupt_bank = Ba;
+                Write_precharge[Ba] = 1'b1;
+            end
+        end
+
+        /*
+            Write with Auto Precharge Calculation
+                The device start internal precharge when:
+                    1.  Meet minimum tRAS requirement
+                and 2.  tWR cycle(s) after last valid data
+                 or 3.  Interrupt by a Read or Write (with or without Auto Precharge)
+
+            Note: Model is starting the internal precharge 1 cycle after they meet all the
+                  requirement but tRP will be compensate for the time after the 1 cycle.
+        */
+        if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
+            if ((($time - RAS_chk0 >= tRAS) &&                                                          // Case 1
+               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) ||   // Case 2
+                 (Burst_length_2 == 1'b1                              && Count_precharge [0] >= 2) ||
+                 (Burst_length_4 == 1'b1                              && Count_precharge [0] >= 4) ||
+                 (Burst_length_8 == 1'b1                              && Count_precharge [0] >= 8))) ||
+                 (RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin                 // Case 3
+                    Auto_precharge[0] = 1'b0;
+                    Write_precharge[0] = 1'b0;
+                    RW_interrupt_write[0] = 1'b0;
+                    Pc_b0 = 1'b1;
+                    Act_b0 = 1'b0;
+                    RP_chk0 = $time + tWRa;
+                    if (Debug) begin
+                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
+                    end
+            end
+        end
+        if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
+            if ((($time - RAS_chk1 >= tRAS) &&                                                          // Case 1
+               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) ||   // Case 2
+                 (Burst_length_2 == 1'b1                              && Count_precharge [1] >= 2) ||
+                 (Burst_length_4 == 1'b1                              && Count_precharge [1] >= 4) ||
+                 (Burst_length_8 == 1'b1                              && Count_precharge [1] >= 8))) ||
+                 (RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin                 // Case 3
+                    Auto_precharge[1] = 1'b0;
+                    Write_precharge[1] = 1'b0;
+                    RW_interrupt_write[1] = 1'b0;
+                    Pc_b1 = 1'b1;
+                    Act_b1 = 1'b0;
+                    RP_chk1 = $time + tWRa;
+                    if (Debug) begin
+                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
+                    end
+            end
+        end
+        if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
+            if ((($time - RAS_chk2 >= tRAS) &&                                                          // Case 1
+               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) ||   // Case 2
+                 (Burst_length_2 == 1'b1                              && Count_precharge [2] >= 2) ||
+                 (Burst_length_4 == 1'b1                              && Count_precharge [2] >= 4) ||
+                 (Burst_length_8 == 1'b1                              && Count_precharge [2] >= 8))) ||
+                 (RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin                 // Case 3
+                    Auto_precharge[2] = 1'b0;
+                    Write_precharge[2] = 1'b0;
+                    RW_interrupt_write[2] = 1'b0;
+                    Pc_b2 = 1'b1;
+                    Act_b2 = 1'b0;
+                    RP_chk2 = $time + tWRa;
+                    if (Debug) begin
+                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
+                    end
+            end
+        end
+        if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
+            if ((($time - RAS_chk3 >= tRAS) &&                                                          // Case 1
+               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) ||   // Case 2
+                 (Burst_length_2 == 1'b1                              && Count_precharge [3] >= 2) ||
+                 (Burst_length_4 == 1'b1                              && Count_precharge [3] >= 4) ||
+                 (Burst_length_8 == 1'b1                              && Count_precharge [3] >= 8))) ||
+                 (RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin                 // Case 3
+                    Auto_precharge[3] = 1'b0;
+                    Write_precharge[3] = 1'b0;
+                    RW_interrupt_write[3] = 1'b0;
+                    Pc_b3 = 1'b1;
+                    Act_b3 = 1'b0;
+                    RP_chk3 = $time + tWRa;
+                    if (Debug) begin
+                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
+                    end
+            end
+        end
+
+        //  Read with Auto Precharge Calculation
+        //      The device start internal precharge:
+        //          1.  Meet minimum tRAS requirement
+        //      and 2.  CAS Latency - 1 cycles before last burst
+        //       or 3.  Interrupt by a Read or Write (with or without AutoPrecharge)
+        if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
+            if ((($time - RAS_chk0 >= tRAS) &&                                                      // Case 1
+                ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) ||                             // Case 2
+                 (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
+                 (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
+                 (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
+                 (RW_interrupt_read[0] == 1'b1)) begin                                              // Case 3
+                    Pc_b0 = 1'b1;
+                    Act_b0 = 1'b0;
+                    RP_chk0 = $time;
+                    Auto_precharge[0] = 1'b0;
+                    Read_precharge[0] = 1'b0;
+                    RW_interrupt_read[0] = 1'b0;
+                    if (Debug) begin
+                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
+                    end
+            end
+        end
+        if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
+            if ((($time - RAS_chk1 >= tRAS) &&
+                ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || 
+                 (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
+                 (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
+                 (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
+                 (RW_interrupt_read[1] == 1'b1)) begin
+                    Pc_b1 = 1'b1;
+                    Act_b1 = 1'b0;
+                    RP_chk1 = $time;
+                    Auto_precharge[1] = 1'b0;
+                    Read_precharge[1] = 1'b0;
+                    RW_interrupt_read[1] = 1'b0;
+                    if (Debug) begin
+                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
+                    end
+            end
+        end
+        if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
+            if ((($time - RAS_chk2 >= tRAS) &&
+                ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || 
+                 (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
+                 (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
+                 (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
+                 (RW_interrupt_read[2] == 1'b1)) begin
+                    Pc_b2 = 1'b1;
+                    Act_b2 = 1'b0;
+                    RP_chk2 = $time;
+                    Auto_precharge[2] = 1'b0;
+                    Read_precharge[2] = 1'b0;
+                    RW_interrupt_read[2] = 1'b0;
+                    if (Debug) begin
+                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
+                    end
+            end
+        end
+        if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
+            if ((($time - RAS_chk3 >= tRAS) &&
+                ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || 
+                 (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
+                 (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
+                 (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
+                 (RW_interrupt_read[3] == 1'b1)) begin
+                    Pc_b3 = 1'b1;
+                    Act_b3 = 1'b0;
+                    RP_chk3 = $time;
+                    Auto_precharge[3] = 1'b0;
+                    Read_precharge[3] = 1'b0;
+                    RW_interrupt_read[3] = 1'b0;
+                    if (Debug) begin
+                        $display("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
+                    end
+            end
+        end
+
+        // Internal Precharge or Bst
+        if (Command[0] == `PRECH) begin                         // Precharge terminate a read with same bank or all banks
+            if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
+                if (Data_out_enable == 1'b1) begin
+                    Data_out_enable = 1'b0;
+                end
+            end
+        end else if (Command[0] == `BST) begin                  // BST terminate a read to current bank
+            if (Data_out_enable == 1'b1) begin
+                Data_out_enable = 1'b0;
+            end
+        end
+
+        if (Data_out_enable == 1'b0) begin
+            Dq_reg <= #tOH {DQ_BITS{1'bz}};
+        end
+
+        // Detect Read or Write command
+        if (Command[0] == `READ) begin
+            Bank = Bank_addr[0];
+            Col = Col_addr[0];
+            Col_brst = Col_addr[0];
+            case (Bank_addr[0])
+                2'b00 : Row = B0_row_addr;
+                2'b01 : Row = B1_row_addr;
+                2'b10 : Row = B2_row_addr;
+                2'b11 : Row = B3_row_addr;
+            endcase
+            Burst_counter = 0;
+            Data_in_enable = 1'b0;
+            Data_out_enable = 1'b1;
+        end else if (Command[0] == `WRITE) begin
+            Bank = Bank_addr[0];
+            Col = Col_addr[0];
+            Col_brst = Col_addr[0];
+            case (Bank_addr[0])
+                2'b00 : Row = B0_row_addr;
+                2'b01 : Row = B1_row_addr;
+                2'b10 : Row = B2_row_addr;
+                2'b11 : Row = B3_row_addr;
+            endcase
+            Burst_counter = 0;
+            Data_in_enable = 1'b1;
+            Data_out_enable = 1'b0;
+        end
+
+        // DQ buffer (Driver/Receiver)
+        if (Data_in_enable == 1'b1) begin                                   // Writing Data to Memory
+            // Array buffer
+            case (Bank)
+                2'b00 : Dq_dqm = Bank0 [{Row, Col}];
+                2'b01 : Dq_dqm = Bank1 [{Row, Col}];
+                2'b10 : Dq_dqm = Bank2 [{Row, Col}];
+                2'b11 : Dq_dqm = Bank3 [{Row, Col}];
+            endcase
+
+            // Dqm operation
+`ifdef x4
+            if (Dqm[0] == 1'b0) begin
+                Dq_dqm [ 3 : 0] = Dq [ 3 : 0];
+            end
+`elsif x8
+            if (Dqm[0] == 1'b0) begin
+                Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
+            end
+`elsif x16
+            if (Dqm[0] == 1'b0) begin
+                Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
+            end
+            if (Dqm[1] == 1'b0) begin
+                Dq_dqm [15 : 8] = Dq [15 : 8];
+            end
+`endif
+
+            // Write to memory
+            case (Bank)
+                2'b00 : Bank0 [{Row, Col}] = Dq_dqm;
+                2'b01 : Bank1 [{Row, Col}] = Dq_dqm;
+                2'b10 : Bank2 [{Row, Col}] = Dq_dqm;
+                2'b11 : Bank3 [{Row, Col}] = Dq_dqm;
+            endcase
+
+            // Display debug message
+            if (Dqm !== 2'b11) begin
+                // Record tWR for manual precharge
+                WR_chkm [Bank] = $time;
+
+                if (Debug) begin
+                    $display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %h", $time, Bank, Row, Col, Dq_dqm);
+                end
+            end else begin
+                if (Debug) begin
+                    $display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
+                end
+            end
+
+            // Advance burst counter subroutine
+            #tHZ Burst_decode;
+
+        end else if (Data_out_enable == 1'b1) begin                         // Reading Data from Memory
+            // Array buffer
+            case (Bank)
+                2'b00 : Dq_dqm = Bank0[{Row, Col}];
+                2'b01 : Dq_dqm = Bank1[{Row, Col}];
+                2'b10 : Dq_dqm = Bank2[{Row, Col}];
+                2'b11 : Dq_dqm = Bank3[{Row, Col}];
+            endcase
+
+            // Dqm operation
+`ifdef x4
+            if (Dqm_reg0 [0] == 1'b1) begin
+                Dq_dqm [ 3 : 0] = 4'bz;
+            end
+`elsif x8
+            if (Dqm_reg0 [0] == 1'b1) begin
+                Dq_dqm [ 7 : 0] = 8'bz;
+            end
+`elsif x16
+            if (Dqm_reg0 [0] == 1'b1) begin
+                Dq_dqm [ 7 : 0] = 8'bz;
+            end
+            if (Dqm_reg0 [1] == 1'b1) begin
+                Dq_dqm [15 : 8] = 8'bz;
+            end
+`endif
+
+            // Display debug message
+            Dq_reg = #tAC Dq_dqm;
+            if (Debug) begin
+                $display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Dqm = %b, Data = %h", $time, Bank, Row, Col, Dqm_reg0, Dq_reg);
+            end
+
+            // Advance burst counter subroutine
+            Burst_decode;
+        end
+    end
+
+    // Burst counter decode
+    task Burst_decode;
+        begin
+            // Advance Burst Counter
+            Burst_counter = Burst_counter + 1;
+
+            // Burst Type
+            if (Mode_reg[3] == 1'b0) begin                                  // Sequential Burst
+                Col_temp = Col + 1;
+            end else if (Mode_reg[3] == 1'b1) begin                         // Interleaved Burst
+                Col_temp[2] =  Burst_counter[2] ^  Col_brst[2];
+                Col_temp[1] =  Burst_counter[1] ^  Col_brst[1];
+                Col_temp[0] =  Burst_counter[0] ^  Col_brst[0];
+            end
+
+            // Burst Length
+            if (Burst_length_2) begin                                       // Burst Length = 2
+                Col [0] = Col_temp [0];
+            end else if (Burst_length_4) begin                              // Burst Length = 4
+                Col [1 : 0] = Col_temp [1 : 0];
+            end else if (Burst_length_8) begin                              // Burst Length = 8
+                Col [2 : 0] = Col_temp [2 : 0];
+            end else begin                                                  // Burst Length = FULL
+                Col = Col_temp;
+            end
+
+            // Burst Read Single Write            
+            if (Write_burst_mode == 1'b1) begin
+                Data_in_enable = 1'b0;
+            end
+
+            // Data Counter
+            if (Burst_length_1 == 1'b1) begin
+                if (Burst_counter >= 1) begin
+                    Data_in_enable = 1'b0;
+                    Data_out_enable = 1'b0;
+                end
+            end else if (Burst_length_2 == 1'b1) begin
+                if (Burst_counter >= 2) begin
+                    Data_in_enable = 1'b0;
+                    Data_out_enable = 1'b0;
+                end
+            end else if (Burst_length_4 == 1'b1) begin
+                if (Burst_counter >= 4) begin
+                    Data_in_enable = 1'b0;
+                    Data_out_enable = 1'b0;
+                end
+            end else if (Burst_length_8 == 1'b1) begin
+                if (Burst_counter >= 8) begin
+                    Data_in_enable = 1'b0;
+                    Data_out_enable = 1'b0;
+                end
+            end
+        end
+    endtask
+
+    // Timing Parameters for -75 (133 MHz @ CL3)
+    specify
+        specparam
+            tAH  =  0.8,                                        // Addr, Ba Hold Time
+            tAS  =  1.5,                                        // Addr, Ba Setup Time
+    `ifdef CLK_166
+            tCK3 =  6,
+    `elsif CLK_133
+            tCK3 =  7.5,
+    `elsif CLK_100
+            tCK3 =  10,
+    `elsif CLK_200
+            tCK3 =  5,   
+    `endif
+            tCH  =  2.5,                                        // Clock High-Level Width
+            tCL  =  2.5,                                        // Clock Low-Level Width
+            tCKH =  0.8,                                        // CKE Hold  Time
+            tCKS =  1.5,                                        // CKE Setup Time
+            tCMH =  0.8,                                        // CS#, RAS#, CAS#, WE#, DQM# Hold  Time
+            tCMS =  1.5,                                        // CS#, RAS#, CAS#, WE#, DQM# Setup Time
+            tDH  =  0.8,                                        // Data-in Hold Time
+            tDS  =  1.5;                                        // Data-in Setup Time
+        $width    (posedge Clk,           tCH);
+        $width    (negedge Clk,           tCL);
+        $period   (negedge Clk,           tCK3);
+        $period   (posedge Clk,           tCK3);
+        $setuphold(posedge Clk,    Cke,   tCKS, tCKH);
+        $setuphold(posedge Clk,    Cs_n,  tCMS, tCMH);
+        $setuphold(posedge Clk,    Cas_n, tCMS, tCMH);
+        $setuphold(posedge Clk,    Ras_n, tCMS, tCMH);
+        $setuphold(posedge Clk,    We_n,  tCMS, tCMH);
+        $setuphold(posedge Clk,    Addr,  tAS,  tAH);
+        $setuphold(posedge Clk,    Ba,    tAS,  tAH);
+        $setuphold(posedge Clk,    Dqm,   tCMS, tCMH);
+        $setuphold(posedge Dq_chk, Dq,    tDS,  tDH);
+    endspecify
+
+endmodule
diff --git a/hw/super6502_fpga/super6502_fpga.peri.xml b/hw/super6502_fpga/super6502_fpga.peri.xml
index a664a30..2141ac8 100644
--- a/hw/super6502_fpga/super6502_fpga.peri.xml
+++ b/hw/super6502_fpga/super6502_fpga.peri.xml
@@ -133,9 +133,164 @@
         <efxpt:gpio name="pll_in" gpio_def="GPIOR_157" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
             <efxpt:input_config name="pll_in" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
         </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[0]" gpio_def="GPIOR_92" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[0]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[0]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[10]" gpio_def="GPIOR_116" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[10]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[10]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[10]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[11]" gpio_def="GPIOR_108" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[11]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[11]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[11]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[12]" gpio_def="GPIOR_112" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[12]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[12]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[12]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[13]" gpio_def="GPIOR_106" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[13]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[13]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[13]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[14]" gpio_def="GPIOR_98" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[14]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[14]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[14]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[15]" gpio_def="GPIOR_94" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[15]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[15]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[15]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[1]" gpio_def="GPIOR_90" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[1]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[1]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[2]" gpio_def="GPIOR_97" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[2]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[2]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[2]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[3]" gpio_def="GPIOR_95" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[3]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[3]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[3]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[4]" gpio_def="GPIOR_93" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[4]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[4]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[4]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[5]" gpio_def="GPIOR_83" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[5]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[5]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[5]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[6]" gpio_def="GPIOR_84" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[6]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[6]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[6]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[7]" gpio_def="GPIOR_82" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[7]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[7]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[7]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[8]" gpio_def="GPIOR_136" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[8]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[8]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[8]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="io_sdr_DATA[9]" gpio_def="GPIOR_119" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="i_sdr_DATA[9]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="o_sdr_DATA[9]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="o_sdr_DATA_oe[9]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[0]" gpio_def="GPIOR_85" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[10]" gpio_def="GPIOR_89" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[10]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[11]" gpio_def="GPIOR_143" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[11]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[12]" gpio_def="GPIOR_144" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[12]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[1]" gpio_def="GPIOR_87" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[2]" gpio_def="GPIOR_86" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[2]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[3]" gpio_def="GPIOR_88" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[3]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[4]" gpio_def="GPIOR_133" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[4]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[5]" gpio_def="GPIOR_135" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[5]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[6]" gpio_def="GPIOR_131" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[6]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[7]" gpio_def="GPIOR_148" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[7]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[8]" gpio_def="GPIOR_138" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[8]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_ADDR[9]" gpio_def="GPIOR_147" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_ADDR[9]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_BA[0]" gpio_def="GPIOR_102" mode="output" bus_name="o_sdr_BA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_BA[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_BA[1]" gpio_def="GPIOR_99" mode="output" bus_name="o_sdr_BA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_BA[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_CK" gpio_def="GPIOR_146" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="i_sdrclk" is_clock_inverted="true" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_CKE" gpio_def="GPIOR_145" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_CKE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_DQM[0]" gpio_def="GPIOR_80" mode="output" bus_name="o_sdr_DQM" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_DQM[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_DQM[1]" gpio_def="GPIOR_132" mode="output" bus_name="o_sdr_DQM" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_DQM[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_n_CAS" gpio_def="GPIOR_139" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_n_CAS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="2"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_n_CS" gpio_def="GPIOR_103" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_n_CS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_n_RAS" gpio_def="GPIOR_91" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_n_RAS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+        <efxpt:gpio name="o_sdr_n_WE" gpio_def="GPIOR_141" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="o_sdr_n_WE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        </efxpt:gpio>
+
         <efxpt:global_unused_config state="input with weak pullup"/>
         <efxpt:bus name="cpu_data" mode="inout" msb="7" lsb="0"/>
         <efxpt:bus name="cpu_addr" mode="input" msb="15" lsb="0"/>
+        <efxpt:bus name="io_sdr_DATA" mode="inout" msb="15" lsb="0"/>
+        <efxpt:bus name="o_sdr_ADDR" mode="output" msb="12" lsb="0"/>
+        <efxpt:bus name="o_sdr_BA" mode="output" msb="1" lsb="0"/>
+        <efxpt:bus name="o_sdr_DQM" mode="output" msb="1" lsb="0"/>
+
     </efxpt:gpio_info>
     <efxpt:pll_info>
         <efxpt:pll name="pll_cpu_clk" pll_def="PLL_TR1" ref_clock_name="i_sysclk" ref_clock_freq="100.0000" multiplier="16" pre_divider="2" post_divider="4" reset_name="pll_cpu_reset" locked_name="pll_cpu_locked" is_ipfrz="false" is_bypass_lock="true">
diff --git a/hw/super6502_fpga/super6502_fpga.xml b/hw/super6502_fpga/super6502_fpga.xml
index 7d569ac..1dcda00 100644
--- a/hw/super6502_fpga/super6502_fpga.xml
+++ b/hw/super6502_fpga/super6502_fpga.xml
@@ -1,4 +1,4 @@
-<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 03 2024 17:03:26" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 03 2024 23:29:38" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion" />
         <efx:device name="T20F256" />
@@ -24,7 +24,11 @@
     </efx:constraint_info>
     <efx:sim_info />
     <efx:misc_info />
-    <efx:ip_info />
+    <efx:ip_info>
+        <efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json">
+            <efx:ip_src_file name="sdram_controller.v" />
+        </efx:ip>
+    </efx:ip_info>
     <efx:synthesis tool_name="efx_map">
         <efx:param name="work_dir" value="work_syn" value_type="e_string" />
         <efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
@@ -51,6 +55,7 @@
         <efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
         <efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
         <efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
+        <efx:param name="include" value="ip/sdram_controller" value_type="e_string" />
     </efx:synthesis>
     <efx:place_and_route tool_name="efx_pnr">
         <efx:param name="work_dir" value="work_pnr" value_type="e_string" />
diff --git a/sw/test_code/loop_test/main.s b/sw/test_code/loop_test/main.s
index 60aebb7..fbd3b02 100644
--- a/sw/test_code/loop_test/main.s
+++ b/sw/test_code/loop_test/main.s
@@ -6,8 +6,7 @@
 .addr      _init       ; Reset vector
 .addr      _irq_int    ; IRQ/BRK vector
 
-.zeropage
-tmp: .res 1
+SDRAM= $200
 
 .code
 
@@ -17,8 +16,8 @@ _irq_int:
 _init:
         lda #$00
 @start:
-        sta tmp
-        cmp tmp
+        sta SDRAM
+        cmp SDRAM
         bne @end
         ina
         bra @start