diff --git a/hw/efinix_fpga/addr_decode.sv b/hw/efinix_fpga/addr_decode.sv index a2d49f7..a6f1121 100644 --- a/hw/efinix_fpga/addr_decode.sv +++ b/hw/efinix_fpga/addr_decode.sv @@ -3,10 +3,12 @@ module addr_decode input [15:0] i_addr, output o_rom_cs, - output o_leds_cs + output o_leds_cs, + output o_sdram_cs ); assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff; assign o_leds_cs = i_addr == 16'hefff; +assign o_sdram_cs = i_addr < 16'h8000; endmodule \ No newline at end of file diff --git a/hw/efinix_fpga/debug_profile.wizard.json b/hw/efinix_fpga/debug_profile.wizard.json index 7ef2626..c57f7ad 100644 --- a/hw/efinix_fpga/debug_profile.wizard.json +++ b/hw/efinix_fpga/debug_profile.wizard.json @@ -3,68 +3,223 @@ { "name": "la0", "type": "la", - "uuid": "7ac38c47d15d4906b7e4dfa4b8e0f620", + "uuid": "41ec466b652a438abc3095c20e7f0d30", "trigin_en": false, "trigout_en": false, "auto_inserted": true, "capture_control": false, - "data_depth": 1024, + "data_depth": 2048, "input_pipeline": 1, "probes": [ { - "name": "cpu_resb", + "name": "u_sdram_adapter/counter", + "width": 2, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/data", + "width": 8, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/i_addr", + "width": 25, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/i_arst", "width": 1, "probe_type": 1 }, { - "name": "cpu_addr", - "width": 16, - "probe_type": 2 - }, - { - "name": "button_reset", + "name": "u_sdram_adapter/i_cs", "width": 1, - "probe_type": 2 + "probe_type": 1 }, { - "name": "cpu_data_in", + "name": "u_sdram_adapter/i_data", "width": 8, - "probe_type": 2 + "probe_type": 1 }, { - "name": "cpu_rwb", - "width": 1, - "probe_type": 2 + "name": "u_sdram_adapter/next_counter", + "width": 2, + "probe_type": 1 }, { - "name": "cpu_sync", - "width": 1, - "probe_type": 2 + "name": "u_sdram_adapter/next_state", + "width": 2, + "probe_type": 1 }, { - "name": "cpu_data_out", + "name": "u_sdram_adapter/o_data", "width": 8, - "probe_type": 2 + "probe_type": 1 }, { - "name": "cpu_data_oe", + "name": "u_sdram_adapter/o_dbg_ADDR", + "width": 26, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_dbg_BA", + "width": 4, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_dbg_DATA_in", + "width": 32, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_dbg_DATA_out", + "width": 32, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_dbg_n_CAS", + "width": 2, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_dbg_n_CS", + "width": 2, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_dbg_n_RAS", + "width": 2, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_dbg_n_WE", + "width": 2, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_dbg_rd_ack", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_dbg_ref_req", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_dbg_tRTW_done", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_dbg_wr_ack", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_sdr_init_done", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_sdr_state", + "width": 4, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/state", + "width": 2, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_addr", + "width": 24, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_data_i", + "width": 32, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_data_o", + "width": 32, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_data_valid", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_last", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_rd_ack", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_rd_valid", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_read", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_write", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_wr_ack", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/_data", "width": 8, - "probe_type": 2 + "probe_type": 1 }, { - "name": "cpu_phi2", + "name": "u_sdram_adapter/i_cpuclk", "width": 1, - "probe_type": 2 + "probe_type": 1 }, { - "name": "w_rom_cs", + "name": "u_sdram_adapter/i_rwb", "width": 1, - "probe_type": 2 + "probe_type": 1 }, { - "name": "boot_rom/re", - "width": 1, - "probe_type": 2 + "name": "u_sdram_adapter/r_write_data", + "width": 32, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_dm", + "width": 4, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/r_dm", + "width": 4, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/r_addr", + "width": 24, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/addr_mux_out", + "width": 24, + "probe_type": 1 } ] } @@ -192,244 +347,2548 @@ }, { "name": "la0_clk", - "net": "clk_2", + "net": "i_sysclk", "path": [] }, { - "name": "la0_probe0", - "net": "cpu_resb", - "path": [] + "name": "la0_probe0[0]", + "net": "counter[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe0[1]", + "net": "counter[1]", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe1[0]", - "net": "cpu_addr[0]", - "path": [] + "net": "data[0]", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe1[1]", - "net": "cpu_addr[1]", - "path": [] + "net": "data[1]", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe1[2]", - "net": "cpu_addr[2]", - "path": [] + "net": "data[2]", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe1[3]", - "net": "cpu_addr[3]", - "path": [] + "net": "data[3]", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe1[4]", - "net": "cpu_addr[4]", - "path": [] + "net": "data[4]", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe1[5]", - "net": "cpu_addr[5]", - "path": [] + "net": "data[5]", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe1[6]", - "net": "cpu_addr[6]", - "path": [] + "net": "data[6]", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe1[7]", - "net": "cpu_addr[7]", - "path": [] + "net": "data[7]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe1[8]", - "net": "cpu_addr[8]", - "path": [] + "name": "la0_probe2[0]", + "net": "i_addr[0]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe1[9]", - "net": "cpu_addr[9]", - "path": [] + "name": "la0_probe2[1]", + "net": "i_addr[1]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe1[10]", - "net": "cpu_addr[10]", - "path": [] + "name": "la0_probe2[2]", + "net": "i_addr[2]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe1[11]", - "net": "cpu_addr[11]", - "path": [] + "name": "la0_probe2[3]", + "net": "i_addr[3]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe1[12]", - "net": "cpu_addr[12]", - "path": [] + "name": "la0_probe2[4]", + "net": "i_addr[4]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe1[13]", - "net": "cpu_addr[13]", - "path": [] + "name": "la0_probe2[5]", + "net": "i_addr[5]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe1[14]", - "net": "cpu_addr[14]", - "path": [] + "name": "la0_probe2[6]", + "net": "i_addr[6]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe1[15]", - "net": "cpu_addr[15]", - "path": [] + "name": "la0_probe2[7]", + "net": "i_addr[7]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe2", - "net": "button_reset", - "path": [] + "name": "la0_probe2[8]", + "net": "i_addr[8]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe3[0]", - "net": "cpu_data_in[0]", - "path": [] + "name": "la0_probe2[9]", + "net": "i_addr[9]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe3[1]", - "net": "cpu_data_in[1]", - "path": [] + "name": "la0_probe2[10]", + "net": "i_addr[10]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe3[2]", - "net": "cpu_data_in[2]", - "path": [] + "name": "la0_probe2[11]", + "net": "i_addr[11]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe3[3]", - "net": "cpu_data_in[3]", - "path": [] + "name": "la0_probe2[12]", + "net": "i_addr[12]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe3[4]", - "net": "cpu_data_in[4]", - "path": [] + "name": "la0_probe2[13]", + "net": "i_addr[13]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe3[5]", - "net": "cpu_data_in[5]", - "path": [] + "name": "la0_probe2[14]", + "net": "i_addr[14]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe3[6]", - "net": "cpu_data_in[6]", - "path": [] + "name": "la0_probe2[15]", + "net": "i_addr[15]", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe3[7]", - "net": "cpu_data_in[7]", - "path": [] + "name": "la0_probe2[16]", + "net": "i_addr[16]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe2[17]", + "net": "i_addr[17]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe2[18]", + "net": "i_addr[18]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe2[19]", + "net": "i_addr[19]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe2[20]", + "net": "i_addr[20]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe2[21]", + "net": "i_addr[21]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe2[22]", + "net": "i_addr[22]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe2[23]", + "net": "i_addr[23]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe2[24]", + "net": "i_addr[24]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe3", + "net": "i_arst", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe4", - "net": "cpu_rwb", - "path": [] + "net": "i_cs", + "path": [ + "u_sdram_adapter" + ] }, { - "name": "la0_probe5", - "net": "cpu_sync", - "path": [] + "name": "la0_probe5[0]", + "net": "i_data[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe5[1]", + "net": "i_data[1]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe5[2]", + "net": "i_data[2]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe5[3]", + "net": "i_data[3]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe5[4]", + "net": "i_data[4]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe5[5]", + "net": "i_data[5]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe5[6]", + "net": "i_data[6]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe5[7]", + "net": "i_data[7]", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe6[0]", - "net": "cpu_data_out[0]", - "path": [] + "net": "next_counter[0]", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe6[1]", - "net": "cpu_data_out[1]", - "path": [] - }, - { - "name": "la0_probe6[2]", - "net": "cpu_data_out[2]", - "path": [] - }, - { - "name": "la0_probe6[3]", - "net": "cpu_data_out[3]", - "path": [] - }, - { - "name": "la0_probe6[4]", - "net": "cpu_data_out[4]", - "path": [] - }, - { - "name": "la0_probe6[5]", - "net": "cpu_data_out[5]", - "path": [] - }, - { - "name": "la0_probe6[6]", - "net": "cpu_data_out[6]", - "path": [] - }, - { - "name": "la0_probe6[7]", - "net": "cpu_data_out[7]", - "path": [] + "net": "next_counter[1]", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe7[0]", - "net": "cpu_data_oe[0]", - "path": [] + "net": "next_state[0]", + "path": [ + "u_sdram_adapter" + ] }, { "name": "la0_probe7[1]", - "net": "cpu_data_oe[1]", - "path": [] - }, - { - "name": "la0_probe7[2]", - "net": "cpu_data_oe[2]", - "path": [] - }, - { - "name": "la0_probe7[3]", - "net": "cpu_data_oe[3]", - "path": [] - }, - { - "name": "la0_probe7[4]", - "net": "cpu_data_oe[4]", - "path": [] - }, - { - "name": "la0_probe7[5]", - "net": "cpu_data_oe[5]", - "path": [] - }, - { - "name": "la0_probe7[6]", - "net": "cpu_data_oe[6]", - "path": [] - }, - { - "name": "la0_probe7[7]", - "net": "cpu_data_oe[7]", - "path": [] - }, - { - "name": "la0_probe8", - "net": "cpu_phi2", - "path": [] - }, - { - "name": "la0_probe9", - "net": "w_rom_cs", - "path": [] - }, - { - "name": "la0_probe10", - "net": "re", + "net": "next_state[1]", "path": [ - "boot_rom" + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe8[0]", + "net": "o_data[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe8[1]", + "net": "o_data[1]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe8[2]", + "net": "o_data[2]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe8[3]", + "net": "o_data[3]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe8[4]", + "net": "o_data[4]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe8[5]", + "net": "o_data[5]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe8[6]", + "net": "o_data[6]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe8[7]", + "net": "o_data[7]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[0]", + "net": "o_dbg_ADDR[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[1]", + "net": "o_dbg_ADDR[1]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[2]", + "net": "o_dbg_ADDR[2]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[3]", + "net": "o_dbg_ADDR[3]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[4]", + "net": "o_dbg_ADDR[4]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[5]", + "net": "o_dbg_ADDR[5]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[6]", + "net": "o_dbg_ADDR[6]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[7]", + "net": "o_dbg_ADDR[7]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[8]", + "net": "o_dbg_ADDR[8]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[9]", + "net": "o_dbg_ADDR[9]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[10]", + "net": "o_dbg_ADDR[10]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[11]", + "net": "o_dbg_ADDR[11]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[12]", + "net": "o_dbg_ADDR[12]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[13]", + "net": "o_dbg_ADDR[13]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[14]", + "net": "o_dbg_ADDR[14]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[15]", + "net": "o_dbg_ADDR[15]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[16]", + "net": "o_dbg_ADDR[16]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[17]", + "net": "o_dbg_ADDR[17]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[18]", + "net": "o_dbg_ADDR[18]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[19]", + "net": "o_dbg_ADDR[19]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[20]", + "net": "o_dbg_ADDR[20]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[21]", + "net": "o_dbg_ADDR[21]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[22]", + "net": "o_dbg_ADDR[22]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[23]", + "net": "o_dbg_ADDR[23]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[24]", + "net": "o_dbg_ADDR[24]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe9[25]", + "net": "o_dbg_ADDR[25]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe10[0]", + "net": "o_dbg_BA[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe10[1]", + "net": "o_dbg_BA[1]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe10[2]", + "net": "o_dbg_BA[2]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe10[3]", + "net": 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"name": "la0_probe41[18]", + "net": "addr_mux_out[18]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe41[19]", + "net": "addr_mux_out[19]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe41[20]", + "net": "addr_mux_out[20]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe41[21]", + "net": "addr_mux_out[21]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe41[22]", + "net": "addr_mux_out[22]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe41[23]", + "net": "addr_mux_out[23]", + "path": [ + "u_sdram_adapter" ] } ] @@ -444,106 +2903,480 @@ ], "session": { "wizard": { - "data_depth": 1024, + "data_depth": 2048, "capture_control": false, "selected_nets": [ { - "name": "cpu_resb", - "width": 1, - "clk_domain": "clk_2", + "name": "counter", + "width": 2, + "clk_domain": "i_sysclk", "selected_probe_type": "DATA AND TRIGGER", "child": [], - "path": [] - }, - { - "name": "cpu_addr", - "width": 16, - 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"u_sdram_adapter" + ] + }, + { + "name": "o_dbg_ref_req", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "o_dbg_tRTW_done", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "o_dbg_wr_ack", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "o_sdr_init_done", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "o_sdr_state", + "width": 4, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ], + "net_idx_left": 3, + "net_idx_right": 0 + }, + { + "name": "state", + "width": 2, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ], + "net_idx_left": 1, + "net_idx_right": 0 + }, + { + "name": "w_addr", + "width": 24, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ], + "net_idx_left": 23, + "net_idx_right": 0 + }, + { + "name": "w_data_i", + "width": 32, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ], + "net_idx_left": 31, + "net_idx_right": 0 + }, + { + "name": "w_data_o", + "width": 32, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ], + "net_idx_left": 31, + "net_idx_right": 0 + }, + { + "name": "w_data_valid", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "w_last", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "w_rd_ack", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "w_rd_valid", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "w_read", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "w_write", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "w_wr_ack", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "_data", + "width": 8, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ], + "net_idx_left": 7, + "net_idx_right": 0 + }, + { + "name": "i_cpuclk", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "i_rwb", + "width": 1, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "r_write_data", + "width": 32, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ], + "net_idx_left": 31, + "net_idx_right": 0 + }, + { + "name": "w_dm", + "width": 4, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ], + "net_idx_left": 3, + "net_idx_right": 0 + }, + { + "name": "r_dm", + "width": 4, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ], + "net_idx_left": 3, + "net_idx_right": 0 + }, + { + "name": "r_addr", + "width": 24, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ], + "net_idx_left": 23, + "net_idx_right": 0 + }, + { + "name": "addr_mux_out", + "width": 24, + "clk_domain": "i_sysclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "u_sdram_adapter" + ], + "net_idx_left": 23, + "net_idx_right": 0 } ], "top_module": "super6502", diff --git a/hw/efinix_fpga/ip/bram/bram_ini.vh b/hw/efinix_fpga/ip/bram/bram_ini.vh index a3729fa..f8f4a62 100644 --- a/hw/efinix_fpga/ip/bram/bram_ini.vh +++ b/hw/efinix_fpga/ip/bram/bram_ini.vh @@ -4,10 +4,10 @@ input integer index;//Mode type input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved case (index) 0: bram_ini_table= -(val_== 0)?256'h00000000000000000fe00080000fa000d00003a000ef000ff0008d000ff000a9: -(val_== 1)?256'h0000000000000000000000000000000000000000000000000000000000000000: -(val_== 2)?256'h0000000000000000000000000000000000000000000000000000000000000000: -(val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_== 0)?256'h00ea000ea000ea000ea00010000040008d0003a00010000000008d000ff000a9: +(val_== 1)?256'h01000004000cd0001000000000ad000ea000ea000ea000ea000ea000ea000ea0: +(val_== 2)?256'hff0008d000f0000a9000f900080000ef000ff0008d00001000a900007000f000: +(val_== 3)?256'h0000000000000000000000000000000000000000000000000f900080000ef000: (val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000: (val_== 5)?256'h0000000000000000000000000000000000000000000000000000000000000000: (val_== 6)?256'h0000000000000000000000000000000000000000000000000000000000000000: diff --git a/hw/efinix_fpga/ip/bram/init_hex.mem b/hw/efinix_fpga/ip/bram/init_hex.mem index 6b920db..806985c 100644 --- a/hw/efinix_fpga/ip/bram/init_hex.mem +++ b/hw/efinix_fpga/ip/bram/init_hex.mem @@ -1,45 +1,45 @@ -a9 -ff -8d -ff -ef -3a -d0 -fa +A9 +FF +8D +00 +10 +3A +8D +04 +10 +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +AD +00 +10 +CD +04 +10 +F0 +07 +A9 +01 +8D +FF +EF 80 -fe -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 +F9 +A9 +F0 +8D +FF +EF +80 +F9 00 00 00 diff --git a/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v b/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v new file mode 100644 index 0000000..290e4d6 --- /dev/null +++ b/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v @@ -0,0 +1,4261 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2022.1.226 +// IP Version: 1.6 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _1a076fc510c34dc9a60c0ede33930d9f +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module sdram_controller ( +input i_we, +input i_sysclk, +input i_arst, +input i_sdrclk, +input i_tACclk, +input i_pll_locked, +input i_re, +input i_last, +output o_dbg_tRTW_done, +output o_dbg_ref_req, +output o_dbg_wr_ack, +output o_dbg_rd_ack, +output [1:0] o_dbg_n_CS, +output [1:0] o_dbg_n_RAS, +output [1:0] o_dbg_n_CAS, +output [1:0] o_dbg_n_WE, +output [3:0] o_dbg_BA, +output [25:0] o_dbg_ADDR, +output [31:0] o_dbg_DATA_out, +output [31:0] o_dbg_DATA_in, +input [23:0] i_addr, +input [31:0] i_din, +input [3:0] i_dm, +output [31:0] o_dout, +output [3:0] o_sdr_state, +output o_sdr_init_done, +output o_wr_ack, +output o_rd_ack, +output o_ref_req, +output o_rd_valid, +output [1:0] o_sdr_CKE, +output [1:0] o_sdr_n_CS, +output [1:0] o_sdr_n_RAS, +output [1:0] o_sdr_n_CAS, +output [1:0] o_sdr_n_WE, +output [3:0] o_sdr_BA, +output [25:0] o_sdr_ADDR, +output [31:0] o_sdr_DATA, +output [31:0] o_sdr_DATA_oe, +input [31:0] i_sdr_DATA, +output [3:0] o_sdr_DQM, +output [5:0] o_dbg_dly_cnt_b, +output o_dbg_tRCD_done +); +`IP_MODULE_NAME(efx_sdram_controller) #( +.fSYS_MHz (100), +.fCK_MHz (200), +.tIORT_u (2), +.BL (1), +.DDIO_TYPE ("SOFT"), +.DQ_WIDTH (8), +.DQ_GROUP (2), +.BA_WIDTH (2), +.ROW_WIDTH (13), +.COL_WIDTH (9), +.tPWRUP (200000), +.tRAS (44), +.tRC (66), +.tRCD (20), +.tREF (64000000), +.tWR (2), +.tMRD (2), +.tRFC (66), +.tRAS_MAX (120000), +.DATA_RATE (2), +.AXI_ARADDR_WIDTH (24), +.SDRAM_MODE ("Native"), +.AXI_BUSER_WIDTH (2), +.AXI_BID_WIDTH (4), +.AXI_AWUSER_WIDTH (2), +.AXI_AWID_WIDTH (4), +.AXI_AWADDR_WIDTH (24), +.AXI_RDATA_WIDTH (32), +.AXI_WUSER_WIDTH (2), +.AXI_WDATA_WIDTH (32), +.AXI_RUSER_WIDTH (3), +.AXI_ARUSER_WIDTH (3), +.AXI_ARID_WIDTH (4), +.tRP (20), +.CL (3) +) u_efx_sdram_controller( +.i_we ( i_we ), +.i_sysclk ( i_sysclk ), +.i_arst ( i_arst ), +.i_sdrclk ( i_sdrclk ), +.i_tACclk ( i_tACclk ), +.i_pll_locked ( i_pll_locked ), +.i_re ( i_re ), +.i_last ( i_last ), +.o_dbg_tRTW_done ( o_dbg_tRTW_done ), +.o_dbg_ref_req ( o_dbg_ref_req ), +.o_dbg_wr_ack ( o_dbg_wr_ack ), +.o_dbg_rd_ack ( o_dbg_rd_ack ), +.o_dbg_n_CS ( o_dbg_n_CS ), +.o_dbg_n_RAS ( o_dbg_n_RAS ), +.o_dbg_n_CAS ( o_dbg_n_CAS ), +.o_dbg_n_WE ( o_dbg_n_WE ), +.o_dbg_BA ( o_dbg_BA ), +.o_dbg_ADDR ( o_dbg_ADDR ), +.o_dbg_DATA_out ( o_dbg_DATA_out ), +.o_dbg_DATA_in ( o_dbg_DATA_in ), +.i_addr ( i_addr ), +.i_din ( i_din ), +.i_dm ( i_dm ), +.o_dout ( o_dout ), +.o_sdr_state ( o_sdr_state ), +.o_sdr_init_done ( o_sdr_init_done ), +.o_wr_ack ( o_wr_ack ), +.o_rd_ack ( o_rd_ack ), +.o_ref_req ( o_ref_req ), +.o_rd_valid ( o_rd_valid ), +.o_sdr_CKE ( o_sdr_CKE ), +.o_sdr_n_CS ( o_sdr_n_CS ), +.o_sdr_n_RAS ( o_sdr_n_RAS ), +.o_sdr_n_CAS ( o_sdr_n_CAS ), +.o_sdr_n_WE ( o_sdr_n_WE ), +.o_sdr_BA ( o_sdr_BA ), +.o_sdr_ADDR ( o_sdr_ADDR ), +.o_sdr_DATA ( o_sdr_DATA ), +.o_sdr_DATA_oe ( o_sdr_DATA_oe ), +.i_sdr_DATA ( i_sdr_DATA ), +.o_sdr_DQM ( o_sdr_DQM ), +.o_dbg_dly_cnt_b ( o_dbg_dly_cnt_b ), +.o_dbg_tRCD_done ( o_dbg_tRCD_done ) +); + +endmodule + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / `IP_MODULE_NAME(axi4_sdram_controller).v +// / / .' / +// __/ /.' / Description: +// __ \ / sdram contronller top with AXI4 interface +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// Support ONLY AXI 32-bit data to SDRAM total DQ x16 half rate +// +// ******************************* +///////////////////////////////////////////////////////////////////////////// +// AxSIZE +`define BYTES_TX_1 3'b000 +`define BYTES_TX_2 3'b001 +`define BYTES_TX_4 3'b010 +`define BYTES_TX_8 3'b011 +`define BYTES_TX_16 3'b100 +`define BYTES_TX_32 3'b101 +`define BYTES_TX_64 3'b110 +`define BYTES_TX_128 3'b111 +`define OKAY 2'b00 + +module `IP_MODULE_NAME(axi4_sdram_controller) +#( + parameter AXI_AWADDR_WIDTH = 32, + parameter AXI_WDATA_WIDTH = 32, + parameter AXI_ARADDR_WIDTH = 32, + parameter AXI_RDATA_WIDTH = 32, + + parameter fSYS_MHz = 100, + parameter fCK_MHz = 100, + parameter DDIO_TYPE = "SOFT", + parameter tPWRUP = 100, // 100 us + parameter tRAS = 44, // 44 ns + parameter tRAS_MAX = 120, // 120 us + parameter tRC = 66, // 66 ns + parameter tRCD = 20, // 20 ns + parameter tREF = 64, // 64 ms + parameter tRFC = 66, // 66 ns + parameter tRP = 20, // 20 ns + parameter tWR = 2, // 1 CK+7.5 ns + parameter tMRD = 2, // 2 CK + parameter CL = 3, // 3 CK + parameter BL = 1, + parameter DATA_RATE = 1, + parameter tIORT_u = 2, + parameter BA_WIDTH = 2, + parameter ROW_WIDTH = 10, + parameter COL_WIDTH = 10, + parameter DQ_WIDTH = 8, // x4, x8 + parameter DQ_GROUP = 8, + // x4 x8 x16 x32 + // DQ_WIDTH 4 8 8 8 + // DQ_GROUP 1 1 2 4 + // AXI not support DQ_WIDTH = 4 DQ_GROUP = 1 + + //----- parameter not configurable by user---- + parameter AXI_AWID_WIDTH = 4, + parameter AXI_AWUSER_WIDTH = 2, + parameter AXI_WUSER_WIDTH = 2, + parameter AXI_BID_WIDTH = 4, + parameter AXI_BUSER_WIDTH = 2, + parameter AXI_ARID_WIDTH = 4, + parameter AXI_ARUSER_WIDTH = 2, + parameter AXI_RUSER_WIDTH = 2 +) +( + input i_aresetn, + input i_sysclk, + input i_sdrclk, + input i_tACclk, + input i_pll_locked, + output o_pll_reset, + + // Compulsory + output o_AXI4_AWREADY, + input [AXI_AWADDR_WIDTH-1:0]i_AXI4_AWADDR, + input [2:0]i_AXI4_AWPROT, // Dummy + input i_AXI4_AWVALID, + + output o_AXI4_WREADY, + input [AXI_WDATA_WIDTH/8-1:0]i_AXI4_WSTRB, + input [AXI_WDATA_WIDTH-1:0]i_AXI4_WDATA, + input i_AXI4_WLAST, + input i_AXI4_WVALID, + + output o_AXI4_BVALID, + input i_AXI4_BREADY, + + output o_AXI4_ARREADY, + input [AXI_ARADDR_WIDTH-1:0]i_AXI4_ARADDR, + input [2:0]i_AXI4_ARPROT, // Dummy + input i_AXI4_ARVALID, + + input i_AXI4_RREADY, + output [AXI_RDATA_WIDTH-1:0]o_AXI4_RDATA, + output o_AXI4_RLAST, + output o_AXI4_RVALID, + + // Optional + input [AXI_AWID_WIDTH-1:0]i_AXI4_AWID, + input [3:0]i_AXI4_AWREGION, // Dummy + input [7:0]i_AXI4_AWLEN, // Dummy + input [2:0]i_AXI4_AWSIZE, + input [1:0]i_AXI4_AWBURST, // Dummy + input i_AXI4_AWLOCK, // Dummy + input [3:0]i_AXI4_AWCACHE, // Dummy + input [3:0]i_AXI4_AWQOS, // Dummy + input [AXI_AWUSER_WIDTH-1:0]i_AXI4_AWUSER, // Dummy + + input [AXI_WUSER_WIDTH-1:0]i_AXI4_WUSER, // Dummy + + output [AXI_BID_WIDTH-1:0]o_AXI4_BID, + output [1:0]o_AXI4_BRESP, // Dummy + output [AXI_BUSER_WIDTH-1:0]o_AXI4_BUSER, // Dummy + + input [AXI_ARID_WIDTH-1:0]i_AXI4_ARID, + input [3:0]i_AXI4_ARREGION, // Dummy + input [7:0]i_AXI4_ARLEN, + input [2:0]i_AXI4_ARSIZE, + input [1:0]i_AXI4_ARBURST, // Dummy + input i_AXI4_ARLOCK, // Dummy + input [3:0]i_AXI4_ARCACHE, // Dummy + input [3:0]i_AXI4_ARQOS, // Dummy + input [AXI_ARUSER_WIDTH-1:0]i_AXI4_ARUSER, // Dummy + + output [AXI_ARID_WIDTH-1:0]o_AXI4_RID, + output [1:0]o_AXI4_RRESP, // Dummy + output [AXI_RUSER_WIDTH-1:0]o_AXI4_RUSER, // Dummy + + output [DATA_RATE -1:0] o_sdr_CKE, + output [DATA_RATE -1:0] o_sdr_n_CS, + output [DATA_RATE -1:0] o_sdr_n_RAS, + output [DATA_RATE -1:0] o_sdr_n_CAS, + output [DATA_RATE -1:0] o_sdr_n_WE, + output [DATA_RATE *BA_WIDTH -1:0] o_sdr_BA, + output [DATA_RATE *ROW_WIDTH -1:0] o_sdr_ADDR, + output [DATA_RATE *DQ_GROUP *DQ_WIDTH -1:0] o_sdr_DATA, + output [DATA_RATE *DQ_GROUP *DQ_WIDTH -1:0] o_sdr_DATA_oe, + input [DATA_RATE *DQ_GROUP *DQ_WIDTH -1:0] i_sdr_DATA, + output [DATA_RATE *DQ_GROUP -1:0] o_sdr_DQM, + + // Debug port + output [3:0]o_sdr_state, + output o_dbg_we, + output o_dbg_re, + output o_dbg_last, + output [BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0]o_dbg_addr, + output [AXI_WDATA_WIDTH-1:0]o_dbg_din, + output o_dbg_wr_ack, + output o_dbg_rd_ack, + output o_sdr_rd_valid, + output o_dbg_ref_req, + output [DATA_RATE*DQ_GROUP*DQ_WIDTH+AXI_ARID_WIDTH:0]o_sdr_dout, + output [1:0]o_axi4_wrstate, + output o_dbg_axi4_wlast, + output [1:0]o_axi4_rastate, + output [1:0]o_axi4_rdstate, + output o_axi4_nwr, + output o_re_lock, + output [6:0]o_shift_cnt, + output [7:0]o_axi4_arlen, + output o_fifo_wr, + output o_fifo_full, + output o_fifo_empty, + output o_dbg_fifo_we, + output [7:0]o_dbg_fifo_waddr, + output o_dbg_fifo_re, + output [7:0]o_dbg_fifo_raddr, + + output [DATA_RATE -1:0] o_dbg_n_CS, + output [DATA_RATE -1:0] o_dbg_n_RAS, + output [DATA_RATE -1:0] o_dbg_n_CAS, + output [DATA_RATE -1:0] o_dbg_n_WE, + output [DATA_RATE *BA_WIDTH -1:0] o_dbg_BA, + output [DATA_RATE *ROW_WIDTH -1:0] o_dbg_ADDR, + output [DATA_RATE *DQ_GROUP *DQ_WIDTH -1:0] o_dbg_DATA_out, + output [DATA_RATE *DQ_GROUP *DQ_WIDTH -1:0] o_dbg_DATA_in +); + +function integer log2; + input integer val; + integer i; + begin + log2 = 0; + for (i=0; 2**i= AXI_BID_WIDTH) + r_AXI4_BID_1P <= i_AXI4_AWID[AXI_BID_WIDTH-1:0]; + else + r_AXI4_BID_1P <= {{AXI_BID_WIDTH-AXI_AWID_WIDTH{1'b0}}, i_AXI4_AWID}; + + r_we_1P <= 1'b1; + // TODO AXI different width support + if (SDR_BWIDTH > AXI_WDATA_WIDTH) + begin + r_addr_1P[0+:BA_WIDTH+ROW_WIDTH+COL_WIDTH-(0-SDR_BWIDTH/AXI_WDATA_WIDTH+1)] <= i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0-SDR_BWIDTH/AXI_WDATA_WIDTH+1]; + $display("foo_gt\n"); + end + else if (SDR_BWIDTH == AXI_WDATA_WIDTH) + begin + r_addr_1P <= {i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:COL_WIDTH], {(DATA_RATE-1){1'b0}}, i_AXI4_AWADDR[COL_WIDTH-1:DATA_RATE-1]}; + //r_addr_1P <= {{(DATA_RATE-1){1'b0}},i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:DATA_RATE-1]}; + $display("foo_eq\n"); + end + + if (SDR_BWIDTH > AXI_WDATA_WIDTH) + begin + //r_AXI4_WREADY_c <= 1'b1; + r_size_1P <= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1; + r_shift_cnt_1P <= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1; + $display("SDR_BWIDTH %d > AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH); + end + else if (SDR_BWIDTH == AXI_WDATA_WIDTH) + begin + if (i_AXI4_WLAST) + begin + r_din_1P <= i_AXI4_WDATA; + r_dm_1P <= i_AXI4_WSTRB ^ {(AXI_WDATA_WIDTH/8){1'b1}}; //bitwise XOR to inver the bit + r_last_1P <= 1'b1; + end + r_size_1P <= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1; + r_shift_cnt_1P <= {7{1'b0}}; + $display("SDR_BWIDTH %d = AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH); + end + else + begin + //r_AXI4_WREADY_c <= 1'b1; + r_size_1P <= AXI_WDATA_WIDTH/SDR_BWIDTH-1'b1; + r_shift_cnt_1P <= AXI_WDATA_WIDTH/SDR_BWIDTH-1'b1; + $display("SDR_BWIDTH %d < AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH); + end + end + end + + s_WR_SHIFT: + begin + if (SDR_BWIDTH > AXI_WDATA_WIDTH) + begin + if (r_shift_cnt_1P != 7'd0) + begin + if (r_AXI4_WREADY_c) + r_shift_cnt_1P <= r_shift_cnt_1P-1'b1; + end + else + begin + r_shift_cnt_1P <= r_size_1P; + end + end + else if (SDR_BWIDTH == AXI_WDATA_WIDTH) + begin + if (r_AXI4_WREADY_2P) + r_addr_1P <= r_addr_1P+c_addr_increment; + + if (r_AXI4_WREADY_c) + begin + r_din_1P <= i_AXI4_WDATA; + r_dm_1P <= i_AXI4_WSTRB ^ {(AXI_WDATA_WIDTH/8){1'b1}}; //bitwise XOR to inver the bit; + end + + if (~r_AXI4_WREADY_c & r_AXI4_WREADY_2P & i_AXI4_WLAST) + begin + r_din_1P <= i_AXI4_WDATA; + r_dm_1P <= i_AXI4_WSTRB ^ {(AXI_WDATA_WIDTH/8){1'b1}}; //bitwise XOR to inver the bit; + end + end + + if (w_wr_ack) + begin + /*if (SDR_BWIDTH < AXI_WDATA_WIDTH) + begin + if (r_size_1P != `BYTES_TX_1) + r_addr_1P <= r_addr_1P+c_addr_increment; + else if (~r_wr_ack_1P) + r_addr_1P <= r_addr_1P+c_addr_increment; + else if (r_AXI4_WREADY_2P) + r_addr_1P <= r_addr_1P+c_addr_increment; + + r_shift_cnt_1P <= r_shift_cnt_1P-1'b1; + if (r_AXI4_WLAST_1P && r_shift_cnt_1P == 7'd1) + r_last_1P <= 1'b1; + end + else if (SDR_BWIDTH == AXI_WDATA_WIDTH) + begin + r_AXI4_WREADY_c <= 1'b1; + end + else + begin + r_AXI4_WREADY_c <= 1'b1; + + if (r_AXI4_WREADY_c) + r_addr_1P <= r_addr_1P+1'b1; + + if (r_shift_cnt_1P == 7'd1) + begin + if (i_AXI4_WLAST || r_AXI4_WLAST_1P) + begin + r_axi4_wrstate_1P <= s_WR_RESP; + r_AXI4_WREADY_c <= 1'b0; + r_AXI4_WLAST_1P <= 1'b0; + r_AXI4_BVALID_1P <= 1'b1; + + r_last_1P <= 1'b1; + end + end + end*/ + + if (r_shift_cnt_1P == 7'd0) + begin + //r_AXI4_WREADY_c <= 1'b1; + + r_AXI4_WLAST_1P <= i_AXI4_WLAST; + r_shift_cnt_1P <= r_size_1P; + + if (i_AXI4_WLAST && r_size_1P == {7{1'b0}} && r_AXI4_AWLEN_1P) + begin + r_axi4_wrstate_1P <= s_WR_RESP; + //r_AXI4_WREADY_c <= ~r_AXI4_WREADY_c; + r_AXI4_WLAST_1P <= 1'b0; + r_AXI4_BVALID_1P <= 1'b1; + + r_we_1P <= 1'b1; + r_last_1P <= 1'b1; + end + else if (r_AXI4_WLAST_1P) + begin + r_axi4_wrstate_1P <= s_WR_RESP; + //r_AXI4_WREADY_c <= ~r_AXI4_WREADY_c; + r_AXI4_WLAST_1P <= 1'b0; + r_AXI4_BVALID_1P <= 1'b1; + + r_we_1P <= 1'b0; + r_last_1P <= 1'b0; + end + end + end + end + + s_WR_RESP: + begin + r_we_1P <= 1'b0; + r_last_1P <= 1'b0; + + if (i_AXI4_BREADY) + begin + r_axi4_wrstate_1P <= s_IDLE; + r_AXI4_BVALID_1P <= 1'b0; + end + end + endcase + + case (r_axi4_rastate_1P) + s_INIT: + begin + if (w_sdr_init_done) + r_axi4_rastate_1P <= s_IDLE; + end + + s_IDLE: + begin + if (i_AXI4_ARVALID && r_axi4_nwr_1P + && ~r_we_1P && ~w_afull && ~r_AXI4_RVALID_1P) + begin + r_axi4_rastate_1P <= s_RD_ADDR; + r_AXI4_ARREADY_1P <= 1'b1; + r_AXI4_RID_1P <= i_AXI4_ARID; + + r_re_1P <= 1'b1; + r_re_lock_1P <= 1'b1; + if (i_AXI4_ARLEN == 8'd0 && (SDR_BWIDTH == AXI_RDATA_WIDTH)) + r_last_1P <= 1'b1; + + // TODO AXI different width support + if (SDR_BWIDTH > AXI_RDATA_WIDTH) + begin + r_addr_1P[0+:BA_WIDTH+ROW_WIDTH+COL_WIDTH-(0-SDR_BWIDTH/AXI_RDATA_WIDTH+1)] <= i_AXI4_ARADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0-SDR_BWIDTH/AXI_RDATA_WIDTH+1]; + end + else if (SDR_BWIDTH == AXI_RDATA_WIDTH) + begin + r_addr_1P <= {i_AXI4_ARADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:COL_WIDTH], {(DATA_RATE-1){1'b0}}, i_AXI4_ARADDR[COL_WIDTH-1:DATA_RATE-1]}; + //r_addr_1P <= {{(DATA_RATE-1){1'b0}},i_AXI4_ARADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:DATA_RATE-1]}; + end + + if (SDR_BWIDTH > AXI_WDATA_WIDTH) + begin + r_size_1P <= SDR_BWIDTH/AXI_RDATA_WIDTH-1'b1; + r_shift_cnt_1P <= SDR_BWIDTH/AXI_RDATA_WIDTH-1'b1; + r_addr_cnt_1P <= SDR_BWIDTH/AXI_RDATA_WIDTH-1'b1; + end + else if (SDR_BWIDTH == AXI_WDATA_WIDTH) + begin + r_AXI4_ARLEN_1P <= i_AXI4_ARLEN; + r_size_1P <= 7'd0; + r_shift_cnt_1P <= 7'd0; + r_addr_cnt_1P <= 7'd0; + r_arlen_cnt_1P <= i_AXI4_ARLEN; + end + else + begin + r_AXI4_ARLEN_1P <= i_AXI4_ARLEN; + r_size_1P <= AXI_RDATA_WIDTH/SDR_BWIDTH-1'b1; + r_shift_cnt_1P <= AXI_RDATA_WIDTH/SDR_BWIDTH-1'b1; + r_addr_cnt_1P <= AXI_RDATA_WIDTH/SDR_BWIDTH-1'b1; + r_arlen_cnt_1P <= i_AXI4_ARLEN; + end + end + end + + s_RD_ADDR: + begin + if (~w_afull) + r_re_1P <= 1'b1; + + if (w_rd_ack) + begin + if (w_afull) + r_re_1P <= 1'b0; + if (SDR_BWIDTH < AXI_WDATA_WIDTH) + r_addr_1P <= r_addr_1P+c_addr_increment; + else if (SDR_BWIDTH == AXI_WDATA_WIDTH) + r_addr_1P <= r_addr_1P+c_addr_increment; + else + r_addr_1P <= r_addr_1P+1'b1; + + r_addr_cnt_1P <= r_addr_cnt_1P-1'b1; + if (r_addr_cnt_1P == 7'd0) + begin + r_addr_cnt_1P <= r_size_1P; + r_arlen_cnt_1P <= r_arlen_cnt_1P-1'b1; + end + + if (r_arlen_cnt_1P == 8'd1 && (SDR_BWIDTH == AXI_RDATA_WIDTH)) + r_last_1P <= 1'b1; + + if (r_arlen_cnt_1P == 8'd0) + begin + if (r_addr_cnt_1P == 8'd1) + r_last_1P <= 1'b1; + + if (r_addr_cnt_1P == 8'd0) + begin + r_axi4_rastate_1P <= s_IDLE; + + r_re_1P <= 1'b0; + r_last_1P <= 1'b0; + r_re_lock_1P <= 1'b0; + end + end + end + end + endcase + + if (w_rd_valid) + begin + if (SDR_BWIDTH >= AXI_RDATA_WIDTH) + begin + r_dout_1P[DOUT_WIDTH-1:0] <= w_dout; + end + + r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH-1:DOUT_WIDTH] <= r_AXI4_RID[CL+tIORT+1]; + + r_shift_cnt_1P <= r_shift_cnt_1P-1'b1; + + if (r_shift_cnt_1P == 7'd0) + begin + r_fifo_wr_1P <= 1'b1; + + if (arlen_cnt == r_AXI4_ARLEN_1P) begin + arlen_cnt <= {9{1'b0}}; + end + else begin + arlen_cnt <= arlen_cnt+1'b1; + end + + if (arlen_cnt == r_AXI4_ARLEN_1P) + r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH] <= 1'b1; + else + r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH] <= 1'b0; + r_shift_cnt_1P <= r_size_1P; + end + end + + case (r_axi4_rdstate_1P) + s_INIT: + begin + if (w_sdr_init_done) + r_axi4_rdstate_1P <= s_IDLE; + end + + s_IDLE: + begin + if (~w_empty & r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH]) + begin + r_axi4_rdstate_1P <= s_RD_SHIFT; + r_fifo_rd_1P <= 1'b1; + r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH] <= 1'b0; + end + end + + s_RD_SHIFT: + begin + r_AXI4_RVALID_1P <= 1'b1; + + if (i_AXI4_RREADY) + begin + if (w_empty) + begin + r_axi4_rdstate_1P <= s_IDLE; + r_AXI4_RVALID_1P <= 1'b0; + end + + if (rd_last) + begin + r_axi4_rdstate_1P <= s_IDLE; + r_AXI4_RVALID_1P <= 1'b0; + end + end + end + endcase + end +end + +genvar i; +generate + for (i=0; i 1) begin + `IP_MODULE_NAME(sdram_io_block) + #( + .DATA_RATE (DATA_RATE), + .BA_WIDTH (BA_WIDTH), + .ROW_WIDTH (ROW_WIDTH), + .COL_WIDTH (COL_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .DQ_GROUP (DQ_GROUP) + ) + inst_sdram_io_block + ( + .i_arst (i_arst), + .i_sysclk (i_sysclk), + .i_sdrclk (i_sdrclk), + .i_tACclk (i_tACclk), + .i_pll_locked (i_pll_locked), + + .i_sdr_CKE_core (w_sdr_CKE), + .i_sdr_n_CS_core (w_sdr_n_CS), + .i_sdr_n_RAS_core (w_sdr_n_RAS), + .i_sdr_n_CAS_core (w_sdr_n_CAS), + .i_sdr_n_WE_core (w_sdr_n_WE), + .i_sdr_BA_core (w_sdr_BA), + .i_sdr_ADDR_core (w_sdr_ADDR), + .i_sdr_DATA_core (w_sdr_DATA_out), + .i_sdr_DATA_oe_core (w_sdr_DATA_oe), + .o_sdr_DATA_core (w_sdr_DATA_in), + .i_sdr_DQM_core (w_sdr_DQM), + + .o_sdr_CKE_pad (o_sdr_CKE), + .o_sdr_n_CS_pad (o_sdr_n_CS), + .o_sdr_n_RAS_pad (o_sdr_n_RAS), + .o_sdr_n_CAS_pad (o_sdr_n_CAS), + .o_sdr_n_WE_pad (o_sdr_n_WE), + .o_sdr_BA_pad (o_sdr_BA), + .o_sdr_ADDR_pad (o_sdr_ADDR), + .o_sdr_DATA_pad (o_sdr_DATA), + .o_sdr_DATA_oe_pad (o_sdr_DATA_oe), + .i_sdr_DATA_pad (i_sdr_DATA), + .o_sdr_DQM_pad (o_sdr_DQM) + ); +end +else begin + reg [DATA_RATE *DQ_GROUP *DQ_WIDTH -1:0]r_sdr_DATA_in_tACclk_1P; + + always@(posedge i_arst or posedge i_tACclk) + begin + if (i_arst) + r_sdr_DATA_in_tACclk_1P <= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}}; + else + r_sdr_DATA_in_tACclk_1P <= i_sdr_DATA; + end + + assign w_sdr_DATA_in = r_sdr_DATA_in_tACclk_1P; + assign o_sdr_CKE = w_sdr_CKE; + assign o_sdr_n_CS = w_sdr_n_CS; + assign o_sdr_n_RAS = w_sdr_n_RAS; + assign o_sdr_n_CAS = w_sdr_n_CAS; + assign o_sdr_n_WE = w_sdr_n_WE; + assign o_sdr_BA = w_sdr_BA; + assign o_sdr_ADDR = w_sdr_ADDR; + assign o_sdr_DATA = w_sdr_DATA_out; + assign o_sdr_DATA_oe = w_sdr_DATA_oe; + assign o_sdr_DQM = w_sdr_DQM; +end +endgenerate + +assign o_dbg_DATA_out = w_sdr_DATA_out; +assign o_dbg_DATA_in = w_sdr_DATA_in; + +endmodule + +////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2019 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +///////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / `IP_MODULE_NAME(sdram_fsm).v +// / / .' / +// __/ /.' / Description: +// __ \ / sdram controller state machine +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(sdram_fsm) +#( + parameter fSYS_MHz = 100, + parameter fCK_MHz = 200, // MHz + parameter DLY_CNT_A_WIDTH = 6, + parameter DLY_CNT_B_WIDTH = 6, + parameter CHECK_ACT_BA = 4, + parameter REF_LATENCY = 2, // + + parameter tPWRUP = 200, // 100 us + parameter tRAS = 44, // 44 ns + parameter tRAS_MAX = 120000, // 120 us + parameter tRC = 66, // 66 ns + parameter tRCD = 20, // 20 ns + parameter tREF = 64, // 64 ms + parameter tRFC = 66, // 66 ns + parameter tRP = 20, // 20 ns + parameter tWR = 2, // 1 CK+7.5 ns + parameter tMRD = 2, // 2 CK + parameter CL = 3, // 3 CK + parameter BL = 1, + parameter tIORT = 2, + parameter DDIO_TYPE = "SOFT", + parameter DATA_RATE = 2, + parameter BA_WIDTH = 2, + parameter ROW_WIDTH = 13, + parameter COL_WIDTH = 10, + parameter DQ_WIDTH = 8, // x4, x8 + parameter DQ_GROUP = 4 + // x4 x8 x16 x32 + // DQ_WIDTH 4 8 8 8 + // DQ_GROUP 1 1 2 4 +) +( + input i_arst, + input i_sysclk, + input i_pll_locked, + + input i_we, + input i_re, + input i_last, + input [ (BA_WIDTH+ROW_WIDTH+COL_WIDTH) -1:0] i_addr, + input [DATA_RATE *DQ_GROUP *DQ_WIDTH -1:0] i_din, + input [(DATA_RATE *DQ_GROUP) -1:0] i_dm, + output [DATA_RATE *DQ_GROUP *DQ_WIDTH -1:0] o_dout, + output [3:0]o_sdr_state, + output o_sdr_init_done, + output o_wr_ack, + output o_rd_ack, + output o_ref_req, + output o_rd_valid, + + output [DATA_RATE -1:0] o_sdr_CKE, + output [DATA_RATE -1:0] o_sdr_n_CS, + output [DATA_RATE -1:0] o_sdr_n_RAS, + output [DATA_RATE -1:0] o_sdr_n_CAS, + output [DATA_RATE -1:0] o_sdr_n_WE, + output [DATA_RATE *BA_WIDTH -1:0] o_sdr_BA, + output [DATA_RATE *ROW_WIDTH -1:0] o_sdr_ADDR, + output [DATA_RATE *DQ_GROUP *DQ_WIDTH -1:0] o_sdr_DATA, + output [DATA_RATE *DQ_GROUP *DQ_WIDTH -1:0] o_sdr_DATA_oe, + input [DATA_RATE *DQ_GROUP *DQ_WIDTH -1:0] i_sdr_DATA, + output [DATA_RATE *DQ_GROUP -1:0] o_sdr_DQM, + + output [5:0]o_dbg_dly_cnt_b, + output o_dbg_tRCD_done, + output o_dbg_tRTW_done, + output o_dbg_ref_req, + output o_dbg_wr_ack, + output o_dbg_rd_ack, + output [DATA_RATE -1:0] o_dbg_n_CS, + output [DATA_RATE -1:0] o_dbg_n_RAS, + output [DATA_RATE -1:0] o_dbg_n_CAS, + output [DATA_RATE -1:0] o_dbg_n_WE, + output [DATA_RATE *BA_WIDTH -1:0] o_dbg_BA, + output [DATA_RATE *ROW_WIDTH -1:0] o_dbg_ADDR +); + +function integer log2; + input integer val; + integer i; + begin + log2 = 0; + for (i=0; 2**i> b; + end + end + end + + r_sdr_dq_1P <= i_din; + r_sdr_dm_1P <= i_dm; + r_sdr_dqoe_1P <= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b1}}; + + r_dly_cnt_b_1P <= {DLY_CNT_B_WIDTH{1'b0}}; + r_tWR_done_1P <= 1'b0; + + r_wr_ack_1P <= ~r_ref_req_1P[0]; + + if (REF_LATENCY > 2) begin + if (r_ref_req_1P[1] || r_tRAS_MAX_done_1P[1] || (i_last & r_wr_ack_1P)) // + begin + r_sdr_cmd_1P <= {DATA_RATE{c_NOP}}; + r_sdr_dqoe_1P <= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}}; + r_wr_ack_1P <= 1'b0; + end + end + else begin + if (r_ref_req_1P[REF_LATENCY-2] || r_tRAS_MAX_done_1P[REF_LATENCY-2] || (i_last & r_wr_ack_1P)) + begin + r_sdr_cmd_1P <= {DATA_RATE{c_NOP}}; + r_sdr_dqoe_1P <= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}}; + r_wr_ack_1P <= 1'b0; + end + end + + end + else if (~i_we && i_re) + begin + if (DATA_RATE == 1) + begin + r_sdr_cmd_1P <= c_RD; + r_sdr_ba_2P <= i_addr[BA_MSB:BA_LSB]; + r_sdr_addr_2P <= i_addr[COL_MSB:COL_LSB]; + end + else + begin + for (c=0; c> b; + end + end + end + + r_dly_cnt_b_1P <= {DLY_CNT_B_WIDTH{1'b0}}; + r_tRTW_done_1P <= 1'b0; + r_tRC_done_1P <= 1'b0; + + r_rd_ack_P[0] <= ~r_ref_req_1P[0]; + + if (REF_LATENCY > 2) begin + if (r_ref_req_1P[1] || r_tRAS_MAX_done_1P[1] || (i_last & r_rd_ack_P[0])) + begin + if (r_rd_ack_P[0]) + begin + r_sdr_cmd_1P <= {DATA_RATE{c_NOP}}; + r_sdr_dqoe_1P <= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}}; + r_rd_ack_P[0] <= 1'b0; + end + end + end + else begin + if (r_ref_req_1P[REF_LATENCY-2] || r_tRAS_MAX_done_1P[REF_LATENCY-2] || (i_last & r_rd_ack_P[0])) + begin + if (r_rd_ack_P[0]) + begin + r_sdr_cmd_1P <= {DATA_RATE{c_NOP}}; + r_sdr_dqoe_1P <= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}}; + r_rd_ack_P[0] <= 1'b0; + end + end + end + end + end + end + end + + s_PRE: + begin + if (r_dly_cnt_a_1P == nRP-1'b1) + begin + if (r_ref_req_1P[REF_LATENCY-1]) + begin + if (r_pre_allbank) // check if the previous PRE is ALL_BANK or SINGLE_BANK + begin + r_sdr_state_1P <= s_REF; + r_sdr_cmd_1P[CYC_A+:4] <= c_REF; + r_pre_allbank <= 1'b0; + r_dly_cnt_a_1P <= {DLY_CNT_A_WIDTH{1'b0}}; + end + else + begin // if the previous PRE is SINGLE_BANK, issue PRE to ALL_BANK before trigger AUTO-refresh + r_sdr_state_1P <= s_PRE; + r_sdr_cmd_1P[CYC_A+:4] <= c_PRE; + r_sdr_addr_1P[CYC_A+10] <= PRE_ALL; + r_pre_allbank <= 1'b1; + if (CHECK_ACT_BA == 4) + begin + r_act_row_1P[0][ROW_WIDTH] <= 1'b0; + r_act_row_1P[1][ROW_WIDTH] <= 1'b0; + r_act_row_1P[2][ROW_WIDTH] <= 1'b0; + r_act_row_1P[3][ROW_WIDTH] <= 1'b0; + end + r_dly_cnt_a_1P <= {DLY_CNT_A_WIDTH{1'b0}}; + end + end + else + begin + r_sdr_state_1P <= s_IDLE; + end + end + end + + s_REF: + begin + if (r_dly_cnt_a_1P == nRFC) + begin + r_sdr_state_1P <= s_IDLE; + r_ref_req_1P[0] <= 1'b0; + r_dly_cnt_d_1P <= {DLY_CNT_D_WIDTH{1'b0}}; + end + end + endcase + end +end + +assign o_sdr_state = r_sdr_state_1P; +assign o_sdr_init_done = r_sdr_init_done_1P; +assign o_wr_ack = r_wr_ack_1P; +genvar i; +generate + for (i=1; i<=RD_PIPE; i=i+1) + begin: readback + always@(posedge i_arst or posedge i_sysclk) + begin + if (i_arst) + r_rd_ack_P[i] <= 1'b0; + else + r_rd_ack_P[i] <= r_rd_ack_P[i-1]; + end + end +endgenerate +assign o_rd_ack = r_rd_ack_P[0]; +assign o_ref_req = r_ref_req_1P[0]; +assign o_rd_valid = r_rd_ack_P[RD_PIPE]; +assign o_dout = r_sdr_dqin_1P; + +assign o_sdr_CKE = r_sdr_cke_1P; +genvar j; +generate + for (j=0; j i_we, +i_sysclk => i_sysclk, +i_arst => i_arst, +i_sdrclk => i_sdrclk, +i_tACclk => i_tACclk, +i_pll_locked => i_pll_locked, +i_re => i_re, +i_last => i_last, +o_dbg_tRTW_done => o_dbg_tRTW_done, +o_dbg_ref_req => o_dbg_ref_req, +o_dbg_wr_ack => o_dbg_wr_ack, +o_dbg_rd_ack => o_dbg_rd_ack, +o_dbg_n_CS => o_dbg_n_CS, +o_dbg_n_RAS => o_dbg_n_RAS, +o_dbg_n_CAS => o_dbg_n_CAS, +o_dbg_n_WE => o_dbg_n_WE, +o_dbg_BA => o_dbg_BA, +o_dbg_ADDR => o_dbg_ADDR, +o_dbg_DATA_out => o_dbg_DATA_out, +o_dbg_DATA_in => o_dbg_DATA_in, +i_addr => i_addr, +i_din => i_din, +i_dm => i_dm, +o_dout => o_dout, +o_sdr_state => o_sdr_state, +o_sdr_init_done => o_sdr_init_done, +o_wr_ack => o_wr_ack, +o_rd_ack => o_rd_ack, +o_ref_req => o_ref_req, +o_rd_valid => o_rd_valid, +o_sdr_CKE => o_sdr_CKE, +o_sdr_n_CS => o_sdr_n_CS, +o_sdr_n_RAS => o_sdr_n_RAS, +o_sdr_n_CAS => o_sdr_n_CAS, +o_sdr_n_WE => o_sdr_n_WE, +o_sdr_BA => o_sdr_BA, +o_sdr_ADDR => o_sdr_ADDR, +o_sdr_DATA => o_sdr_DATA, +o_sdr_DATA_oe => o_sdr_DATA_oe, +i_sdr_DATA => i_sdr_DATA, +o_sdr_DQM => o_sdr_DQM, +o_dbg_dly_cnt_b => o_dbg_dly_cnt_b, +o_dbg_tRCD_done => o_dbg_tRCD_done); +------------------------ End INSTANTIATION Template --------- diff --git a/hw/efinix_fpga/ip/sdram_controller/settings.json b/hw/efinix_fpga/ip/sdram_controller/settings.json new file mode 100644 index 0000000..e43a50e --- /dev/null +++ b/hw/efinix_fpga/ip/sdram_controller/settings.json @@ -0,0 +1,44 @@ +{ + "args": [ + "-o", + "sdram_controller", + "--base_path", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory_controller", + "name": "efx_sdram_controller", + "version": "1.6" + } + ], + "conf": { + "fCK_MHz": "200", + "tIORT_u": "2", + "CL": "3", + "DDIO_TYPE": "0", + "DQ_GROUP": "2", + "ROW_WIDTH": "13", + "COL_WIDTH": "9", + "tPWRUP": "200000", + "tRAS": "44", + "tRAS_MAX": "120000", + "tRC": "66", + "tRCD": "20", + "tREF": "64000000", + "tRFC ": "66", + "tRP": "20", + "SDRAM_MODE": "0", + "DATA_RATE": "2" + }, + "output": { + "external_source": [ + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd" + ] + }, + "sw_version": "2022.1.226", + "generated_date": "2022-12-22T03:56:49.168890" +} \ No newline at end of file diff --git a/hw/efinix_fpga/sdram_adapter.sv b/hw/efinix_fpga/sdram_adapter.sv new file mode 100644 index 0000000..450953f --- /dev/null +++ b/hw/efinix_fpga/sdram_adapter.sv @@ -0,0 +1,273 @@ +module sdram_adapter( + input logic i_cpuclk, + input logic i_arst, // Async Reset + input logic i_sysclk, // Controller Clock (100MHz) + input logic i_sdrclk, // t_su and t_wd clock (200MHz) + input logic i_tACclk, // t_ac clock (200MHz) + + input logic i_cs, // Chip select + input logic i_rwb, // Read/Write. Write is low + input logic [24:0] i_addr, // Input address. Byte addressed + + input logic [7:0] i_data, // Input Data + output logic [7:0] o_data, // Output data + + output o_sdr_init_done, + + output o_sdr_CKE, + output o_sdr_n_CS, + output o_sdr_n_RAS, + output o_sdr_n_CAS, + output o_sdr_n_WE, + output [1:0] o_sdr_BA, + output [12:0] o_sdr_ADDR, + output [15:0] o_sdr_DATA, + output [15:0] o_sdr_DATA_oe, + input [15:0] i_sdr_DATA, + output [1:0] o_sdr_DQM +); + +logic [1:0] w_sdr_CKE; +logic [1:0] w_sdr_n_CS; +logic [1:0] w_sdr_n_RAS; +logic [1:0] w_sdr_n_CAS; +logic [1:0] w_sdr_n_WE; +logic [3:0] w_sdr_BA; +logic [25:0] w_sdr_ADDR; +logic [31:0] w_sdr_DATA; +logic [31:0] w_sdr_DATA_oe; +logic [3:0] w_sdr_DQM; + +assign o_sdr_CKE = w_sdr_CKE[0]; //Using SOFT ddio, ignore second cycle +assign o_sdr_n_CS = w_sdr_n_CS[0]; +assign o_sdr_n_RAS = w_sdr_n_RAS[0]; +assign o_sdr_n_CAS = w_sdr_n_CAS[0]; +assign o_sdr_n_WE = w_sdr_n_WE[0]; +assign o_sdr_BA = w_sdr_BA[0+:2]; +assign o_sdr_ADDR = w_sdr_ADDR[0+:13]; +assign o_sdr_DATA = w_sdr_DATA[0+:16]; +assign o_sdr_DATA_oe = w_sdr_DATA_oe[0+:16]; +assign o_sdr_DQM = w_sdr_DQM[0+:2]; + +// What should happen when the cpu writes something? +// 1. Address should already be calculated from the memory mapper, don't need to worry about it +// 2. Data byte position needs to be determined. Each write is 32 bits, so the dm bits need to +// be set and the byte shifted to the correct position +// 3. write enable and last should be set high. Only ever do bursts of 1. +// 4. Sample wr_ack and when it goes high, release write_enable and last + +// What should happen when the cpu reads something? +// 1. Address should already be calculated from the memory mapper, don't need to worry about it +// 2. read_enable and last should be set high. Only ever to bursts of 1. +// 3. Sample rd_ack and when it goes high, release read_enable and last +// 4. Sample read_valid signal. When it is high, grab the data on the on the bus. +// The returned data will be 16 bit, so you need to extract the correct byte. (or will it be 32?) + +// when writing, the write data is only valid on a falling edge. +// Really all of this should be done on falling edges. +// But basically if we are in access, and cpuclk goes low, go back to wait. +// If something actually happened, we would be in one of the read/write states. + +enum bit [1:0] {ACCESS, READ_WAIT, WRITE_WAIT, WAIT} state, next_state; + +logic w_read, w_write, w_last; +logic [23:0] w_addr, r_addr; +logic [31:0] w_data_i, w_data_o; +logic [3:0] w_dm, r_dm; + +logic w_wr_ack, w_rd_ack, w_rd_valid; + +logic [7:0] data, _data; +logic w_data_valid; + +logic [31:0] r_write_data; + +logic [1:0] counter, next_counter; + +always @(posedge i_sysclk) begin + if (i_arst) begin + state <= WAIT; + counter <= '0; + end else begin + state <= next_state; + counter <= next_counter; + r_write_data <= w_data_i; + r_addr <= w_addr; + r_dm <= w_dm; + end + + if (w_data_valid) + o_data <= _data; +end + +//because of timing issues, We really need to trigger +//the write on the falling edge of phi2. There is a 2ns +//delay between the rising edge of phi2 and data valid +//Since the address is valid on the previous falling edge, +//Reads can occur on the rising edge I guess. + + +//so basically cpu clock goes high when cs goes high we go into a priming state +//where we wait until cs goes low. when cpu clock is low, do the actual write. + +//in terms of the existing state, the access state needs to only do something +//if selected AND cpu_clock is low. If cpu clock is high, we should be in wait, +//and after the read/write is complete we should also go back to wait. + +//actually that may only apply to writes, since reads should occur at the rising +//edge of i_cpuclk + +//Starts out in state 0 with cpuclk low and cs high. +//Then, cpuclk goes high. This is now a valid time to read +//After this, cpuclk goes low again, this is now a valid time to write. +//so basically if cpuclk goes low when cs is low, go to wait state + +//what I am thinking is basically 2 states like before. wait and access. +//we go to access when cpuclk is high and cs is high. +//we can read as soon as we want if rwn is high. +//BUT if rwb is low then we have to wait untl cpuclk goes low again. + + +always_comb begin + next_state = state; + next_counter = counter; + + w_addr = '0; + w_dm = '0; + w_read = '0; + w_write = '0; + w_last = '0; + w_data_i = '0; + w_data_valid = '0; + _data = 0; + + unique case (state) + WAIT: begin + if (i_cs & i_cpuclk) + next_state = ACCESS; + end + + ACCESS: begin + // only do something if selected + if (i_cs) begin + w_addr = {{i_addr[24:2]}, {1'b0}};; // divide by 2, set last bit to 0 + + if (i_rwb) begin //read + w_read = '1; + w_last = '1; + // dm is not needed for reads? + if (w_rd_ack) next_state = READ_WAIT; + end else begin //write + //w_data_i = i_data << (8*i_addr[1:0]); + w_data_i = {4{i_data}}; //does anything get through? + w_dm = ~(4'b1 << i_addr[1:0]); + if (~i_cpuclk) begin + w_write = '1; + w_last = '1; + next_state = WRITE_WAIT; + end + end + end + end + + WRITE_WAIT: begin + // stay in this state until write is acknowledged. + w_write = '1; + w_last = '1; + w_data_i = r_write_data; + w_dm = r_dm; + w_addr = r_addr; + if (w_wr_ack) next_state = WAIT; + end + + READ_WAIT: begin + if (w_rd_valid) begin + w_data_valid = '1; + _data = w_data_o[8*i_addr[1:0]+:8]; + end + + // you must wait until the next cycle! + if (~i_cpuclk) begin + next_state = WAIT; + end + end + + endcase +end + +//this seems scuffed +logic [23:0] addr_mux_out; +always_comb begin + if (state == ACCESS) begin + addr_mux_out = w_addr; + end else begin + addr_mux_out = r_addr; + end +end + +logic o_dbg_tRTW_done; +logic o_dbg_ref_req; +logic o_dbg_wr_ack; +logic o_dbg_rd_ack; +logic [1:0] o_dbg_n_CS; +logic [1:0] o_dbg_n_RAS; +logic [1:0] o_dbg_n_CAS; +logic [1:0] o_dbg_n_WE; +logic [3:0] o_dbg_BA; +logic [25:0] o_dbg_ADDR; +logic [31:0] o_dbg_DATA_out; +logic [31:0] o_dbg_DATA_in; +logic o_sdr_init_done; +logic [3:0] o_sdr_state; + + +sdram_controller u_sdram_controller( + .i_arst(i_arst), //Positive Controller Reset + .i_sysclk(i_sysclk), //Controller Clock (100MHz) + .i_sdrclk(i_sdrclk), //t_su and t_ac clock. Double sysclk (200MHz) + .i_tACclk(i_tACclk), //t_ac clock. Also double sysclk, but different pll for tuning + .i_pll_locked(1'b1), //There exists a pll locked output from the pll, not sure why they don't use it. + + .i_we(w_write), //Write enable. Can only be de-asserted if i_last is asserted and o_wr_ack is sampled high. + .i_re(w_read), //Read enable. Can only be de-asserted if i_last is asserted and o_rd_ack is sampled high. + .i_last(w_last), //Set to high to indicate the last transfer of a burst write or read. + .i_addr(addr_mux_out), //SDRAM physical address B R C. For half rate, only even addresses. + .i_din(r_write_data), //Data to write to SDRAM. Twice normal width when running at half speed (hence the even addresses) + .i_dm('0), //dm (r_dm) + .o_dout(w_data_o), //Data read from SDRAM, doubled as above. + .o_sdr_init_done(o_sdr_init_done), //Indicates that the SDRAM initialization is done. + .o_wr_ack(w_wr_ack), //Write acknowledge, handshake with we + .o_rd_ack(w_rd_ack), //Read acknowledge, handshake with re + .o_rd_valid(w_rd_valid),//Read valid. The data on o_dout is valid + + .o_sdr_CKE(w_sdr_CKE), + .o_sdr_n_CS(w_sdr_n_CS), + .o_sdr_n_RAS(w_sdr_n_RAS), + .o_sdr_n_CAS(w_sdr_n_CAS), + .o_sdr_n_WE(w_sdr_n_WE), + .o_sdr_BA(w_sdr_BA), + .o_sdr_ADDR(w_sdr_ADDR), + .o_sdr_DATA(w_sdr_DATA), + .o_sdr_DATA_oe(w_sdr_DATA_oe), + .i_sdr_DATA({{16'b0}, {i_sdr_DATA}}), + .o_sdr_DQM(w_sdr_DQM), + + //Does include debug signals. + + .o_sdr_state(o_sdr_state), + + .o_dbg_tRTW_done ( o_dbg_tRTW_done ), + .o_dbg_ref_req ( o_dbg_ref_req ), + .o_dbg_wr_ack ( o_dbg_wr_ack ), + .o_dbg_rd_ack ( o_dbg_rd_ack ), + .o_dbg_n_CS ( o_dbg_n_CS ), + .o_dbg_n_RAS ( o_dbg_n_RAS ), + .o_dbg_n_CAS ( o_dbg_n_CAS ), + .o_dbg_n_WE ( o_dbg_n_WE ), + .o_dbg_BA ( o_dbg_BA ), + .o_dbg_ADDR ( o_dbg_ADDR ), + .o_dbg_DATA_out ( o_dbg_DATA_out ), + .o_dbg_DATA_in ( o_dbg_DATA_in ) +); + +endmodule diff --git a/hw/efinix_fpga/super6502.peri.xml b/hw/efinix_fpga/super6502.peri.xml index 77a52a4..1cb5a6f 100644 --- a/hw/efinix_fpga/super6502.peri.xml +++ b/hw/efinix_fpga/super6502.peri.xml @@ -1,5 +1,5 @@ - + @@ -130,6 +130,86 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -154,6 +234,75 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -161,12 +310,22 @@ + + + + - - - - + + + + + + + + + + diff --git a/hw/efinix_fpga/super6502.pt.sdc b/hw/efinix_fpga/super6502.pt.sdc index d27a80e..a513cff 100644 --- a/hw/efinix_fpga/super6502.pt.sdc +++ b/hw/efinix_fpga/super6502.pt.sdc @@ -1,9 +1,9 @@ # Efinity Interface Designer SDC -# Version: 2021.2.323.4.6 -# Date: 2022-11-01 18:17 +# Version: 2022.1.226 +# Date: 2022-12-21 23:10 -# Copyright (C) 2017 - 2021 Efinix Inc. All rights reserved. +# Copyright (C) 2017 - 2022 Efinix Inc. All rights reserved. # Device: T20F256 # Project: super6502 @@ -11,49 +11,56 @@ # PLL Constraints ################# -create_clock -period 20.00 clk_50 -create_clock -period 500.00 clk_2 +create_clock -period 5.0000 i_sdrclk +create_clock -period 5.0000 i_tACclk +create_clock -period 10.0000 i_sysclk +create_clock -period 20.0000 clk_50 +create_clock -period 500.0000 clk_2 # GPIO Constraints #################### # set_input_delay -clock -max [get_ports {button_reset}] # set_input_delay -clock -min [get_ports {button_reset}] +# set_input_delay -clock -max [get_ports {cpu_addr[0]}] +# set_input_delay -clock -min [get_ports {cpu_addr[0]}] +# set_input_delay -clock -max [get_ports {cpu_addr[1]}] +# set_input_delay -clock -min [get_ports {cpu_addr[1]}] +# set_input_delay -clock -max [get_ports {cpu_addr[2]}] +# set_input_delay -clock -min [get_ports {cpu_addr[2]}] +# set_input_delay -clock -max [get_ports {cpu_addr[3]}] +# set_input_delay -clock -min [get_ports {cpu_addr[3]}] +# set_input_delay -clock -max [get_ports {cpu_addr[4]}] +# set_input_delay -clock -min [get_ports {cpu_addr[4]}] +# set_input_delay -clock -max [get_ports {cpu_addr[5]}] +# set_input_delay -clock -min [get_ports {cpu_addr[5]}] +# set_input_delay -clock -max [get_ports {cpu_addr[6]}] +# set_input_delay -clock -min [get_ports {cpu_addr[6]}] +# set_input_delay -clock -max [get_ports {cpu_addr[7]}] +# set_input_delay -clock -min [get_ports {cpu_addr[7]}] +# set_input_delay -clock -max [get_ports {cpu_addr[8]}] +# set_input_delay -clock -min [get_ports {cpu_addr[8]}] +# set_input_delay -clock -max [get_ports {cpu_addr[9]}] +# set_input_delay -clock -min [get_ports {cpu_addr[9]}] +# set_input_delay -clock -max [get_ports {cpu_addr[10]}] +# set_input_delay -clock -min [get_ports {cpu_addr[10]}] +# set_input_delay -clock -max [get_ports {cpu_addr[11]}] +# set_input_delay -clock -min [get_ports {cpu_addr[11]}] +# set_input_delay -clock -max [get_ports {cpu_addr[12]}] +# set_input_delay -clock -min [get_ports {cpu_addr[12]}] +# set_input_delay -clock -max [get_ports {cpu_addr[13]}] +# set_input_delay -clock -min [get_ports {cpu_addr[13]}] +# set_input_delay -clock -max [get_ports {cpu_addr[14]}] +# set_input_delay -clock -min [get_ports {cpu_addr[14]}] +# set_input_delay -clock -max [get_ports {cpu_addr[15]}] +# set_input_delay -clock -min [get_ports {cpu_addr[15]}] +# set_input_delay -clock -max [get_ports {cpu_rwb}] +# set_input_delay -clock -min [get_ports {cpu_rwb}] # set_input_delay -clock -max [get_ports {cpu_sync}] # set_input_delay -clock -min [get_ports {cpu_sync}] # set_input_delay -clock -max [get_ports {pll_in}] # set_input_delay -clock -min [get_ports {pll_in}] -# set_output_delay -clock -max [get_ports {cpu_addr[0]}] -# set_output_delay -clock -min [get_ports {cpu_addr[0]}] -# set_output_delay -clock -max [get_ports {cpu_addr[1]}] -# set_output_delay -clock -min [get_ports {cpu_addr[1]}] -# set_output_delay -clock -max [get_ports {cpu_addr[2]}] -# set_output_delay -clock -min [get_ports {cpu_addr[2]}] -# set_output_delay -clock -max [get_ports {cpu_addr[3]}] -# set_output_delay -clock -min [get_ports {cpu_addr[3]}] -# set_output_delay -clock -max [get_ports {cpu_addr[4]}] -# set_output_delay -clock -min [get_ports {cpu_addr[4]}] -# set_output_delay -clock -max [get_ports {cpu_addr[5]}] -# set_output_delay -clock -min [get_ports {cpu_addr[5]}] -# set_output_delay -clock -max [get_ports {cpu_addr[6]}] -# set_output_delay -clock -min [get_ports {cpu_addr[6]}] -# set_output_delay -clock -max [get_ports {cpu_addr[7]}] -# set_output_delay -clock -min [get_ports {cpu_addr[7]}] -# set_output_delay -clock -max [get_ports {cpu_addr[8]}] -# set_output_delay -clock -min [get_ports {cpu_addr[8]}] -# set_output_delay -clock -max [get_ports {cpu_addr[9]}] -# set_output_delay -clock -min [get_ports {cpu_addr[9]}] -# set_output_delay -clock -max [get_ports {cpu_addr[10]}] -# set_output_delay -clock -min [get_ports {cpu_addr[10]}] -# set_output_delay -clock -max [get_ports {cpu_addr[11]}] -# set_output_delay -clock -min [get_ports {cpu_addr[11]}] -# set_output_delay -clock -max [get_ports {cpu_addr[12]}] -# set_output_delay -clock -min [get_ports {cpu_addr[12]}] -# set_output_delay -clock -max [get_ports {cpu_addr[13]}] -# set_output_delay -clock -min [get_ports {cpu_addr[13]}] -# set_output_delay -clock -max [get_ports {cpu_addr[14]}] -# set_output_delay -clock -min [get_ports {cpu_addr[14]}] -# set_output_delay -clock -max [get_ports {cpu_addr[15]}] -# set_output_delay -clock -min [get_ports {cpu_addr[15]}] +# set_output_delay -clock -max [get_ports {cpu_phi2}] +# set_output_delay -clock -min [get_ports {cpu_phi2}] # set_output_delay -clock -max [get_ports {cpu_irqb}] # set_output_delay -clock -min [get_ports {cpu_irqb}] # set_output_delay -clock -max [get_ports {cpu_nmib}] @@ -62,8 +69,68 @@ create_clock -period 500.00 clk_2 # set_output_delay -clock -min [get_ports {cpu_rdy}] # set_output_delay -clock -max [get_ports {cpu_resb}] # set_output_delay -clock -min [get_ports {cpu_resb}] -# set_output_delay -clock -max [get_ports {cpu_rwb}] -# set_output_delay -clock -min [get_ports {cpu_rwb}] +# set_output_delay -clock -max [get_ports {leds[0]}] +# set_output_delay -clock -min [get_ports {leds[0]}] +# set_output_delay -clock -max [get_ports {leds[1]}] +# set_output_delay -clock -min [get_ports {leds[1]}] +# set_output_delay -clock -max [get_ports {leds[2]}] +# set_output_delay -clock -min [get_ports {leds[2]}] +# set_output_delay -clock -max [get_ports {leds[3]}] +# set_output_delay -clock -min [get_ports {leds[3]}] +# set_output_delay -clock -max [get_ports {leds[4]}] +# set_output_delay -clock -min [get_ports {leds[4]}] +# set_output_delay -clock -max [get_ports {leds[5]}] +# set_output_delay -clock -min [get_ports {leds[5]}] +# set_output_delay -clock -max [get_ports {leds[6]}] +# set_output_delay -clock -min [get_ports {leds[6]}] +# set_output_delay -clock -max [get_ports {leds[7]}] +# set_output_delay -clock -min [get_ports {leds[7]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[0]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[0]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[1]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[1]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[2]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[2]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[3]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[3]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[4]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[4]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[5]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[5]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[6]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[6]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[7]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[7]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[8]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[8]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[9]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[9]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[10]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[10]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[11]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[11]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[12]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[12]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_BA[0]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_BA[0]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_BA[1]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_BA[1]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_CK}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_CK}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_CKE}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_CKE}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DQM[0]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DQM[0]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DQM[1]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DQM[1]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_n_CAS}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_n_CAS}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_n_CS}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_n_CS}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_n_RAS}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_n_RAS}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_n_WE}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_n_WE}] # set_input_delay -clock -max [get_ports {cpu_data_in[0]}] # set_input_delay -clock -min [get_ports {cpu_data_in[0]}] # set_output_delay -clock -max [get_ports {cpu_data_out[0]}] @@ -112,3 +179,99 @@ create_clock -period 500.00 clk_2 # set_output_delay -clock -min [get_ports {cpu_data_out[7]}] # set_output_delay -clock -max [get_ports {cpu_data_oe[7]}] # set_output_delay -clock -min [get_ports {cpu_data_oe[7]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[0]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[0]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[0]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[0]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[0]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[0]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[1]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[1]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[1]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[1]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[1]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[1]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[2]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[2]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[2]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[2]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[2]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[2]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[3]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[3]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[3]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[3]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[3]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[3]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[4]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[4]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[4]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[4]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[4]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[4]}] +set_input_delay -clock i_sdrclk -max 5.768 [get_ports {i_sdr_DATA[5]}] +set_input_delay -clock i_sdrclk -min 2.884 [get_ports {i_sdr_DATA[5]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[5]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[5]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[5]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[5]}] +set_input_delay -clock i_sdrclk -max 5.568 [get_ports {i_sdr_DATA[6]}] +set_input_delay -clock i_sdrclk -min 2.784 [get_ports {i_sdr_DATA[6]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[6]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[6]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[6]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[6]}] +set_input_delay -clock i_sdrclk -max 5.768 [get_ports {i_sdr_DATA[7]}] +set_input_delay -clock i_sdrclk -min 2.884 [get_ports {i_sdr_DATA[7]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[7]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[7]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[7]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[7]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[8]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[8]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[8]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[8]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[8]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[8]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[9]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[9]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[9]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[9]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[9]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[9]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[10]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[10]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[10]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[10]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[10]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[10]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[11]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[11]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[11]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[11]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[11]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[11]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[12]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[12]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[12]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[12]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[12]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[12]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[13]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[13]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[13]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[13]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[13]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[13]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[14]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[14]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[14]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[14]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[14]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[14]}] +set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[15]}] +set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[15]}] +set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[15]}] +set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[15]}] +set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[15]}] +set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[15]}] diff --git a/hw/efinix_fpga/super6502.sv b/hw/efinix_fpga/super6502.sv index 4c88070..21c814a 100644 --- a/hw/efinix_fpga/super6502.sv +++ b/hw/efinix_fpga/super6502.sv @@ -1,27 +1,46 @@ module super6502 ( - input [7:0] cpu_data_in, - input cpu_sync, - input cpu_rwb, - input pll_in, - input button_reset, - input pll_cpu_locked, - input clk_50, - input clk_2, - input logic [15:0] cpu_addr, - output logic [7:0] cpu_data_out, - output logic [7:0] cpu_data_oe, - output logic cpu_irqb, - output logic cpu_nmib, - output logic cpu_rdy, - output logic cpu_resb, - output logic pll_cpu_reset, - output logic cpu_phi2, - - output logic [7:0] leds + input logic i_sysclk, // Controller Clock (100MHz) + input logic i_sdrclk, // t_su and t_wd clock (200MHz) + input logic i_tACclk, // t_ac clock (200MHz) + + input [7:0] cpu_data_in, + input cpu_sync, + input cpu_rwb, + input pll_in, + input button_reset, + input pll_cpu_locked, + input clk_50, + input clk_2, + input logic [15:0] cpu_addr, + output logic [7:0] cpu_data_out, + output logic [7:0] cpu_data_oe, + output logic cpu_irqb, + output logic cpu_nmib, + output logic cpu_rdy, + output logic cpu_resb, + output logic pll_cpu_reset, + output logic cpu_phi2, + + output logic [7:0] leds, + + output logic o_pll_reset, + output logic o_sdr_CKE, + output logic o_sdr_n_CS, + output logic o_sdr_n_WE, + output logic o_sdr_n_RAS, + output logic o_sdr_n_CAS, + output logic [1:0] o_sdr_BA, + output logic [12:0] o_sdr_ADDR, + input logic [15:0] i_sdr_DATA, + output logic [15:0] o_sdr_DATA, + output logic [15:0] o_sdr_DATA_oe, + output logic [1:0] o_sdr_DQM + ); assign pll_cpu_reset = '1; +assign o_pll_reset = '1; assign cpu_data_oe = {8{cpu_rwb}}; assign cpu_rdy = '1; @@ -30,12 +49,14 @@ assign cpu_nmib = '1; assign cpu_phi2 = clk_2; +logic w_sdr_init_done; + always @(posedge clk_2) begin if (button_reset == '0) begin cpu_resb <= '0; end else begin - if (cpu_resb == '0) begin + if (cpu_resb == '0 && w_sdr_init_done) begin cpu_resb <= '1; end end @@ -44,21 +65,26 @@ end logic w_rom_cs; logic w_leds_cs; +logic w_sdram_cs; addr_decode u_addr_decode( .i_addr(cpu_addr), .o_rom_cs(w_rom_cs), - .o_leds_cs(w_leds_cs) + .o_leds_cs(w_leds_cs), + .o_sdram_cs(w_sdram_cs) ); logic [7:0] w_rom_data_out; logic [7:0] w_leds_data_out; +logic [7:0] w_sdram_data_out; always_comb begin if (w_rom_cs) cpu_data_out = w_rom_data_out; else if (w_leds_cs) - cpu_data_out= w_leds_data_out; + cpu_data_out = w_leds_data_out; + else if (w_sdram_cs) + cpu_data_out = w_sdram_data_out; else cpu_data_out = 'x; end @@ -84,4 +110,34 @@ leds u_leds( .o_leds(leds) ); +sdram_adapter u_sdram_adapter( + .i_cpuclk(clk_2), + .i_arst(~button_reset), + .i_sysclk(i_sysclk), + .i_sdrclk(i_sdrclk), + .i_tACclk(i_tACclk), + + .i_cs(w_sdram_cs), + .i_rwb(cpu_rwb), + + .i_addr(cpu_addr), + .i_data(cpu_data_in), + .o_data(w_sdram_data_out), + + .o_sdr_init_done(w_sdr_init_done), + + .o_sdr_CKE(o_sdr_CKE), + .o_sdr_n_CS(o_sdr_n_CS), + .o_sdr_n_RAS(o_sdr_n_RAS), + .o_sdr_n_CAS(o_sdr_n_CAS), + .o_sdr_n_WE(o_sdr_n_WE), + .o_sdr_BA(o_sdr_BA), + .o_sdr_ADDR(o_sdr_ADDR), + .o_sdr_DATA(o_sdr_DATA), + .o_sdr_DATA_oe(o_sdr_DATA_oe), + .i_sdr_DATA(i_sdr_DATA), + .o_sdr_DQM(o_sdr_DQM) +); + + endmodule diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index 135366d..bd6ba4d 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,12 +1,12 @@ - + - + @@ -15,6 +15,7 @@ + @@ -23,7 +24,11 @@ - + + + + + @@ -47,6 +52,7 @@ + @@ -79,7 +85,7 @@ - +