From cfcf94a8757a0ac4e701342045f1879dcb44e5dd Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Mon, 14 Mar 2022 10:45:45 -0500 Subject: [PATCH] Integrate uart controller into top level module Adds new chip select for the UART, and a new entry in the data_out mux for the UART. --- hw/fpga/addr_decode.sv | 4 +++- hw/fpga/super6502.sv | 11 ++++++++--- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/fpga/addr_decode.sv b/hw/fpga/addr_decode.sv index 1b4dd5e..83f3c57 100644 --- a/hw/fpga/addr_decode.sv +++ b/hw/fpga/addr_decode.sv @@ -2,11 +2,13 @@ module addr_decode( input logic [15:0] addr, output logic ram_cs, output logic rom_cs, - output logic hex_cs + output logic hex_cs, + output logic uart_cs ); assign rom_cs = addr[15]; assign ram_cs = ~addr[15] && addr < 16'h7ff0; assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4; +assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6; endmodule diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv index 1411643..54bcf61 100644 --- a/hw/fpga/super6502.sv +++ b/hw/fpga/super6502.sv @@ -40,10 +40,12 @@ assign cpu_data = cpu_rwb ? cpu_data_out : 'z; logic [7:0] rom_data_out; logic [7:0] ram_data_out; +logic [7:0] uart_data_out; logic ram_cs; logic rom_cs; logic hex_cs; +logic uart_cs; cpu_clk cpu_clk( .inclk0(clk_50), @@ -65,7 +67,8 @@ addr_decode decode( .addr(cpu_addr), .ram_cs(ram_cs), .rom_cs(rom_cs), - .hex_cs(hex_cs) + .hex_cs(hex_cs), + .uart_cs(uart_cs) ); @@ -74,6 +77,8 @@ always_comb begin cpu_data_out = ram_data_out; else if (rom_cs) cpu_data_out = rom_data_out; + else if (uart_cs) + cpu_data_out = uart_data_out; else cpu_data_out = 'x; end @@ -112,11 +117,11 @@ uart uart( .rst(rst), .rw(cpu_rwb), .data_in(cpu_data_in), - .cs(), + .cs(uart_cs), .addr(cpu_addr[1:0]), .RXD(UART_RXD), .TXD(UART_TXD), - .data_out() + .data_out(uart_data_out) ); endmodule