From d37e32ec64abce402415257d51a9a33ec17df070 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Mon, 18 Sep 2023 23:27:54 -0700 Subject: [PATCH] Add sim cpu --- .gitmodules | 3 +++ hw/efinix_fpga/simulation/sim_top.sv | 12 ++++++++++++ hw/efinix_fpga/simulation/verilog-6502 | 1 + 3 files changed, 16 insertions(+) create mode 100644 hw/efinix_fpga/simulation/sim_top.sv create mode 160000 hw/efinix_fpga/simulation/verilog-6502 diff --git a/.gitmodules b/.gitmodules index 21b2181..6d2a279 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "sw/cc65"] path = sw/cc65 url = https://git.byronlathi.com/bslathi19/cc65 +[submodule "hw/efinix_fpga/simulation/verilog-6502"] + path = hw/efinix_fpga/simulation/verilog-6502 + url = https://git.byronlathi.com/bslathi19/verilog-6502 diff --git a/hw/efinix_fpga/simulation/sim_top.sv b/hw/efinix_fpga/simulation/sim_top.sv new file mode 100644 index 0000000..81ceefc --- /dev/null +++ b/hw/efinix_fpga/simulation/sim_top.sv @@ -0,0 +1,12 @@ +module sim_top(); + +//TODO: this +cpu_65c02 u_cpu(); + +//TODO: also this +super6502 u_dut(); + +//TODO: decide what to do here +memory u_mem(); + +endmodule \ No newline at end of file diff --git a/hw/efinix_fpga/simulation/verilog-6502 b/hw/efinix_fpga/simulation/verilog-6502 new file mode 160000 index 0000000..a5f605d --- /dev/null +++ b/hw/efinix_fpga/simulation/verilog-6502 @@ -0,0 +1 @@ +Subproject commit a5f605d00d22095532cc32aa7a481465b1bdca17