From d3aa195adf417900f3e6232459e88f16717f8046 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sat, 23 Sep 2023 10:49:44 -0700
Subject: [PATCH] Add updated sim cpu with fix

---
 hw/efinix_fpga/simulation/Makefile         |  3 ++-
 hw/efinix_fpga/simulation/src/sim_top.sv   | 11 ++++++-----
 hw/efinix_fpga/simulation/src/verilog-6502 |  2 +-
 3 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/hw/efinix_fpga/simulation/Makefile b/hw/efinix_fpga/simulation/Makefile
index 0385b34..4927c98 100644
--- a/hw/efinix_fpga/simulation/Makefile
+++ b/hw/efinix_fpga/simulation/Makefile
@@ -9,9 +9,10 @@ INC=$(shell find include/ -type f)
 TOP_MODULE=sim_top
 TARGET=sim_top
 INIT_MEM=init_hex.mem
+FLAGS=-DSIM
 
 all: $(INIT_MEM)
-	iverilog -g2005-sv -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
+	iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
 
 $(INIT_MEM):
 	cp ../$(INIT_MEM) .
diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv
index 703ba35..1e6664c 100644
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -55,17 +55,17 @@ logic w_cpu_reset;
 logic [15:0] w_cpu_addr;
 logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut;
 logic cpu_rwb;
+logic w_cpu_phi2;
 
 //TODO: this
 cpu_65c02 u_cpu(
-	.clk(r_clk_2),
-	// .reset(~w_cpu_reset),
-	.reset(~button_reset),
+	.phi2(w_cpu_phi2),
+	.reset(~w_cpu_reset),
 	.AB(w_cpu_addr),
 	.RDY('1),
 	.IRQ('0),
 	.NMI('0),
-	.DI(w_cpu_data_from_dut),
+	.DI_s1(w_cpu_data_from_dut),
 	// .DO(w_cpu_data_from_cpu),
 	.WE(cpu_rwb)
 );
@@ -92,7 +92,8 @@ super6502 u_dut(
 	.cpu_addr(w_cpu_addr),
 	.cpu_data_out(w_cpu_data_from_dut),
 	// .cpu_data_in(w_cpu_data_from_cpu),
-	.cpu_rwb(~cpu_rwb)
+	.cpu_rwb(~cpu_rwb),
+	.cpu_phi2(w_cpu_phi2)
 );
 
 
diff --git a/hw/efinix_fpga/simulation/src/verilog-6502 b/hw/efinix_fpga/simulation/src/verilog-6502
index a5f605d..001840c 160000
--- a/hw/efinix_fpga/simulation/src/verilog-6502
+++ b/hw/efinix_fpga/simulation/src/verilog-6502
@@ -1 +1 @@
-Subproject commit a5f605d00d22095532cc32aa7a481465b1bdca17
+Subproject commit 001840c64e5bb175672db899009fdea7a815003b