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Add updated sim cpu with fix

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This commit is contained in:
Byron Lathi
2023-09-23 10:49:44 -07:00
parent 00173f4e89
commit d3aa195adf
3 changed files with 9 additions and 7 deletions
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3
hw/efinix_fpga/simulation/Makefile
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@@ -9,9 +9,10 @@ INC=$(shell find include/ -type f)
TOP_MODULE=sim_top TOP_MODULE=sim_top
TARGET=sim_top TARGET=sim_top
INIT_MEM=init_hex.mem INIT_MEM=init_hex.mem
FLAGS=-DSIM
all: $(INIT_MEM) all: $(INIT_MEM)
iverilog -g2005-sv -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS) iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
$(INIT_MEM): $(INIT_MEM):
cp ../$(INIT_MEM) . cp ../$(INIT_MEM) .

11
hw/efinix_fpga/simulation/src/sim_top.sv
View File

@@ -55,17 +55,17 @@ logic w_cpu_reset;
logic [15:0] w_cpu_addr; logic [15:0] w_cpu_addr;
logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut; logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut;
logic cpu_rwb; logic cpu_rwb;
logic w_cpu_phi2;
//TODO: this //TODO: this
cpu_65c02 u_cpu( cpu_65c02 u_cpu(
.clk(r_clk_2), .phi2(w_cpu_phi2),
// .reset(~w_cpu_reset), .reset(~w_cpu_reset),
.reset(~button_reset),
.AB(w_cpu_addr), .AB(w_cpu_addr),
.RDY('1), .RDY('1),
.IRQ('0), .IRQ('0),
.NMI('0), .NMI('0),
.DI(w_cpu_data_from_dut), .DI_s1(w_cpu_data_from_dut),
// .DO(w_cpu_data_from_cpu), // .DO(w_cpu_data_from_cpu),
.WE(cpu_rwb) .WE(cpu_rwb)
); );
@@ -92,7 +92,8 @@ super6502 u_dut(
.cpu_addr(w_cpu_addr), .cpu_addr(w_cpu_addr),
.cpu_data_out(w_cpu_data_from_dut), .cpu_data_out(w_cpu_data_from_dut),
// .cpu_data_in(w_cpu_data_from_cpu), // .cpu_data_in(w_cpu_data_from_cpu),
.cpu_rwb(~cpu_rwb) .cpu_rwb(~cpu_rwb),
.cpu_phi2(w_cpu_phi2)
); );

2
hw/efinix_fpga/simulation/src/verilog-6502

Submodule hw/efinix_fpga/simulation/src/verilog-6502 updated: a5f605d00d...001840c64e