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Merge branch '14-terminal-driver' into 'master'

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Resolve "Terminal Driver"

Closes #14

See merge request bslathi19/super6502!58
This commit is contained in:
Byron Lathi
2023-12-01 09:13:39 +00:00
parent eb676da0d7 32c82044a7
commit d49fa64d34
13 changed files with 471 additions and 14 deletions
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2
hw/efinix_fpga/simulation/Makefile
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@@ -11,7 +11,7 @@ TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME)
STANDALONE_TB= interrupt_controller_tb mapper_tb rtc_tb uart_irq_tb
CODE_TB= interrupt_controller_code_tb mapper_code_tb rtc_code_tb \
devices_setup_code_tb
devices_setup_code_tb uart_irq_code_tb
#TODO implement something like sources.list

36
hw/efinix_fpga/simulation/tbs/uart_irq_code_tb.sv Normal file
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@@ -0,0 +1,36 @@
`timescale 1ns/1ps
module uart_irq_code_tb();
sim_top u_sim_top();
always begin
if (
u_sim_top.w_cpu_addr == 16'h0 &&
u_sim_top.w_cpu_we == '1
) begin
if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
$display("Good finish!");
$finish();
end else begin
$display("Bad finish!");
$finish_and_return(-1);
end
end
# 1;
end
initial begin
repeat(15000) @(posedge u_sim_top.r_clk_cpu)
u_sim_top.u_sim_uart.tx_en = 1;
@(posedge u_sim_top.r_clk_cpu);
u_sim_top.u_sim_uart.tx_data = 8'hAA;
repeat (100) @(posedge u_sim_top.r_clk_cpu);
$finish();
end
always @(u_sim_top.u_dut.u_rtc.r_output) begin
$display("counter: %d", u_sim_top.u_dut.u_rtc.r_output);
end
endmodule