From d5bccd46e35dbb6cb3033afb7c632445d95a5e6b Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 12 Jan 2023 14:04:44 -0600 Subject: [PATCH] Add write flag and reset logic for read flag --- hw/efinix_fpga/uart_wrapper.sv | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/efinix_fpga/uart_wrapper.sv b/hw/efinix_fpga/uart_wrapper.sv index 19fcf70..04d35e3 100644 --- a/hw/efinix_fpga/uart_wrapper.sv +++ b/hw/efinix_fpga/uart_wrapper.sv @@ -54,7 +54,12 @@ always_ff @(posedge clk_50) begin end always_ff @(negedge clk) begin + status[1] <= tx_busy | tx_en; + status[0] <= status[0] | rx_data_valid; + if (cs & ~addr & rwb) begin + status[0] <= 0; + end if (cs & ~rwb) begin case (addr)